Patent Application
20070228008
The present invention relates in general to semiconductor processing, and in particular, to the selective removal of surface layers from a workpiece, as for example, a semiconductor wafer in the manufacture of integrated circuits. It will be understood that while the following discussion is directed to semiconductor manufacturing proceses, the present invention may apply to various manufacturing processes and apparatus therefore such that the present invention shall not be limited to semiconductor manufacturing.
Photoresist masks define every layer of an integrated circuit (IC), from front-end-of-line (FEOL) ion implantation for isolation, P-or N-well doping, threshold voltage adjustment and source-drain contacts to back-end-of-line (BEOL) plasma etching or plating of metal and etching of interlevel dielectrics. These coatings must be removed efficiently and completely after each level in the semiconductor device is formed. In this context, resist removal may be variously described as resist ashing, stripping or etching. While the present discussion will make various references to “etching”, it will be understood that in the context of the present invention the term etching is used universally to refer to ashing, stripping or etching, and, where appropriate, may refer to various other processes where removal of a surface layer is implied. Presently, the utilization of a downstream plasma generating apparatus is the industry standard for removing resist. In this approach, a normally non-reactive gas, such as O2, flows through a microwave or radio-frequency discharge, where it is transformed into a plasma, defined as a mixture of excited molecules, radicals, ions, and electrons. The charged species in the plasma may recombine as they flow through a downstream distribution system. However, many radicals may have sufficient lifetimes to reach the wafer. For the example using oxygen as the flow gas, singlet sigma metastable oxygen molecules may persist and ultimately interact with the wafer surface, (J. T. Jeong et al., Plasma Sources Sci. Technol. 7, 282-285, 1998). High energy ion bombardment may cause unwanted damage to components of the semiconducting device or to the wafer substrate itself. The absence of charged particles may thus prevent electrical damage to the integrated circuits (ICs) in downstream ash tools.
The present description provides a novel plasma source never before used in semiconductor manufacturing processes, based on surface waveguide discharge technology. Previous implementation of plasma systems have employed a source of electromagnetic power to activate a plasma gas, such as the Surfaguide device developed by Moisson et al., (Moisson et al., IEEE Trans. Plasma Sci., PS-12, 203-214, 1984). However, the limited cooling efficiency of this apparatus effectively limited the power densities of the resulting plasma. Previously, oil-cooled plasma sources have commonly been implemented. However, operating a plasma at high energy involves very high temperatures. Cooling oil decomposes under these conditions, depositing a carbonized layer on the outside wall of the plasma discharge tube within the waveguide. Once initiated, the oil-based carbon layer grows rapidly with increasing microwave exposure; eventually, catastrophic arcing takes place within the waveguide and destroys the plasma discharge tube. Thus, oil-cooled systems are unsuitable for high energy plasma discharges. Air-cooled high power plasma systems have been reported, but their operation was limited to atmospheric pressure, i.e. in the high pressure regime, such that the resulting plasma would not contain reactive species necessary for selective removal of organic surface layers, such as photoresist, (Y. Okamoto, High-Power Microwave-Induced Helium Plasma At Atmospheric Pressure For Determination Of Halogens In Aqueous Solution, Jap. Journ. Appl. Phys. 38, L 338, 1999).
Typically, the wafers are heated to enhance the reaction rate during downstream plasma ashing. The application time in conventional processes for an unimplanted resist layer may be as low as 15 seconds at 270° C. for O2-based plasma chemistry. Once the resist layer has been subjected to ion implantation, as required for intermediate IC fabrication steps, the reaction mechanism using plasma becomes more complex. Ion implanted resist is much more difficult to remove than unimplanted resist, since the implantation process produces a carbonized crust mixed with metal ions that exhibits extremely low intrinsic etch rates, (G K. Vinogradova et al., J. Vac. Sci. Technol. B, 17, 1, January/Febuary 1999; S Fujimura et al. Nucl. Instrum. Methods B39, 1989, pp. 809; K J Orvek et al., Nucl. Instrum. Methods B7/8, 1985, P501; T Bausum et al., “Stripping High-Dose Implanted Resist for 300 mm Production,” Semiconductor International, Jun. 1, 2003; J. R. Wasson et al., “Ion Absorbing Stencil Mask Coatings For Ion Beam Lithography,” J. Vac. Sci. Technol. B, 15, 2214, 1997). The process throughput is further reduced because the wafer temperature must be kept below about 120° C. to prevent the ejection of particulates, which may occur when the crust explodes under the pressure of gas, mainly NH3, that is evolved in response to heating above the hardbake temperature. This phenomena is known as popping, (D. Fleming et al., Manufacturing Improvements Realized through an Optimized pre-Implant UV/Bake Process, Future Fab International, 4, 1, 1977, p 177). Ion implanted resist films, unlike graphite or photoresist, are essentially inert; they do not adsorb atmospheric oxygen, nitrogen, or water vapor. The activation energy for an ion implanted resist film reacting with atomic oxygen has been reported to be 2.4 eV versus 0.17 eV for unimplanted resist, (A. Joshi et al., J. Vac. Sci. Technol. A, 8, 3, May/June 1990, pp. 2137). This additional activation energy explains why ion implanted resist films are essentially unetchable in conventional downstream plasmas. Further, RF-bias and fluorine chemistry have been used to enhance the etch rate for ion implanted films, (K J Orvek and C Huffinan, Nucl. Instrum. Methods B7/8 (1985) P501; JI. McOmber et al., Nucl. Instrum. Methods B74 (1993) pp. 266-270; K Reinhardt et al., IBM Technical Symposium, France October 1999). However, these more aggressive removal methods invariably cause some degree of erosion of unprotected surfaces. Increasingly, such losses on wafer surfaces are becoming economically unacceptable as the thickness of gate oxide and contacts continue to shrink with each new generation of ICs.
Thus, there is a critical need for a new etching paradigm that can remove ion implanted photoresist layers with essentially perfect selectivity over silicon dioxide, silicon or other thin dielectric films, and that provides total independence from fluorine chemistry. There is also a need for a new technology that provides commercially viable removal rates while maintaining low substrate temperatures that may be applied on materials coated with inorganic or organic materials, including either implanted or unimplanted surface layers.
The present invention addresses the foregoing needs by providing a new approach for removing surface layers from semiconductor wafers. The present invention provides a method wherein reactant gases are activated by a medium pressure surface wave discharge. The method further involves the formation of volatile reactants in the plasma gas that can strip photoresist from the surface of a wafer. The plasma gas forms a reactive plasma jet that impinges on a substrate from which surface layers may be selectively, thus safely, etched with high efficiency. The method may be practiced in a commerically viable manner for stripping applied materials from large wafers by scanning them in front of the jet.
In particular, the present invention can be characterized generally as an apparatus for selectively removing surface layers from a workpiece in a manufacturing process, wherein the apparatus comprises: a process chamber; a plama applicator; and a cooling system. The process chamber defines a subatmospheric environment for receiving the workpiece to be processed such that a surface layer can be removed. The plasma applicator generates a plasma and includes a pressurized supply of reactant process gas, a plasma discharge tube in fluid communication with the pressurized supply of reactant process gas, an electromagnetic power source for directing electromagnetic power to the plasma discharge tube to generate a plasma therein, and a nozzle opening situated at an end of the plasma discharge tube for jetting the plasma gas into the process chamber in a direction toward the workpiece. Finally, the cooling system includes a conduit substantially surrounding the plasma discharge tube for circulating a gaseous coolant therethrough, thereby forming a cooling channel around the plasma discharge tube.
An embodiment of the present invention is provided as an apparatus for performing medium pressure (between about 10 Torr and about 500 Torr) plasma material removal on semiconductor wafers. The apparatus provides a system wherein reactant gases, such as O2, H2, H2O, N2, etc., may flow through a narrow discharge tube made of quartz , sapphire or other electromagnetic insensitive material, and wherein surface wave activation by an electromagnetic power source, such as a microwave or RF power source, may be applied. Additionally, a cooling system for the discharge tube using a gaseous coolant is provided, further comprising an integral cooling flange on the discharge tube, which may be attached to a cooling channel. The apparatus may further comprise a discharge nozzle from which the gas emerges from the tube and impinges on a substrate, such that resultant volatile reaction products, such as H2O, CO2, or low molecular weight hydrocarbons, may selectively strip material layers from the surface of a substrate wafer. The apparatus may further comprise a positioning system for supporting a wafer chuck, that provides wafer heating and positioning, and provides for high speed scanning of a wafer with the plasma source.
The use of surface wave discharges has the unique advantage of being able to guide the discharge from the point where excitation power is applied, to the wafer where it is used. Also, the method of providing a surface wave discharge may be practiced over a wide range of pressure without significant changes to the electromagnetic power system.
The ideal operating pressure range of the present invention is in the medium pressure regime (greater than about 10 Torr, but less than about 500 Torr). Medium pressure plasmas have the advantage that very high rates of electron-ion recombination and energetic particle thermalization may eliminate the high energy charged species present in low pressure plasmas. Eliminating these high energy species eliminates the possibility of potentially damaging substrate currents and sputter erosion. Further, plasma gas temperatures in the medium pressure regime are extremely high compared to low pressure plasmas. Higher plasma gas temperatures provide an additional source of heat in the reactive zone on the wafer, specifically there where it is most required. This focused thermal energy positively contributes to the reactive removal of organic material, wherein the reaction rate of material removal is increased, thereby increasing the speed (and so the commercial viability) of the process. In contrast, the use of low pressures (less than about 10 Torr) for this plasma jet system may not be desirable because, as pressure decreases, the geometry of the plasma jet may flare out, thereby making the “spot size” less controllable. The use of high pressures (greater than about 500 Torr) may not be advantageous because the reactive species needed for surface removal may recombine before reaching the wafer, thus reducing the effectiveness of the plasma for highly selective removal. Operation of the present invention over a wide pressure window may, however, enable atmospheric wafer exchange while the plasma source is still operating. Since ignition of the plasma normally requires low pressure (close to 1T), cycling the process pressure may be avoided if the power source can be maintained during wafer exchange at about 760 Torr (atmospheric pressure). This may avoid additionally having to vaccum pump down to low pressure for plasma ignition, and then repressurizing to medium pressure for processing each semicondutor wafer, thereby further saving valuable process time in an industrial setting.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
In the following description, numerous specific details are set forth such as specific process values or parameters, etc. to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well known components have been shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning specific semiconductor product applications and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art.
Referring now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views:
The high speed wafer scanning stage comprises a chuck 130 with a wafer holder which clamps the wafer. The wafer holder may be operated with the force of vacuum, chamber pressure, or electrostatically. The wafer holder may contact the wafer with a thermally conducting or insulating material, depending on the degree of contact conductance desired with the wafer. In one example, an insulating material layer is introduced between the wafer and the wafer holder to reduce thermal contact conductance, thereby increasing the wafer temperature by hindering dissipation of heat. Conversely, in one example, a conducting material layer is introduced between the wafer and the wafer holder to increase thermal contact conductance, thereby decreasing the wafer temperature by promoting dissipation of heat. Further, the chuck 130 may be connected to a power supply via coupling 133 for heating the wafer, or to an active cooling supply via coupling 132, such as water, for cooling the wafer. The chuck may also be equipped with a thermocouple sensor via coupling 135 or other temperature sensor for monitoring the chuck temperature.
The chuck and wafer holder may be mounted on a mechanical positioning system for scanning the wafer. In this regard, scanning the wafer refers to dynamicaly positioning the wafer while being impinged by the plasma jet, so as to expose a region of the wafer to the plasma treatment. The exposure by scanning may be uniform over an entire region on the wafer, or may involve selectively treating sections of the wafer to a differing level of exposure to the plasma. In
The present invention employs a cooling system using a gaseous coolant. A high velocity gas flowing in a direction 113 opposite the plasma gas 114 is used to cool the plasma discharge tube, whereby operation of the plasma applicator 101 at much higher power dissipation is made possible. In one example, a dry air or nitrogen coolant gas, confined by a concentric outer tube 116, cools the plasma discharge tube 106. As shown in
The present invention may further comprise a trap 120 incorporated below the flange of the inner tube so as to eliminate leakage of electromagnetic power into the processing chamber. In one example, a ¼ γ transformer based microwave trap is employed. The gaseous coolant may flow radially inward through channels in the lower surface of the trap 120 toward the plasma discharge tube 106 and enter the narrowed space 105 between the plasma discharge tube and the outer cooling conduit 116. The velocity of the coolant gas increases substantially as it enters this region, as the flow cross-section is reduced. The result is a signficantly enhanced cooling of the plasma discharge tube 106, particularly in the extremely hot zone within the waveguide 110. In one example embodiment, a 1 mm wide gap between the plasma discharge tube and the cooling conduit results in coolant gas velocities approaching Mach 1, whereby high microwave power levels near 2.5 kW may be sustained on a continuous basis. In contrast to oil-based cooling systems, the air cooling of the present invention does not leave deposits on the discharge tube and does not cause damage to the plasma discharge tube, even after extended, continuous operation of the plasma jet at high power levels.
The thermal power of the plasma jet provides the ability to heat the wafer locally, thus increasing etch rates by increasing reaction rates, while simultaneously delivering reactive species to feed the etching reaction of organic surface layers. The total thermal power P delivered to the substrate from the impinging plasma jet was determined by measuring the rate of temperature T rise vs. time t, dT/dt, of a thermally isolated aluminum block placed under the jet by the following equation:
P=Cρ V(dT/dt)
where the heat capacity is C=0.9 J/K.g, the density is ρ=2.7 g/cm3, and the volume is V=104.04 cm3. The results of these measurements are illustrated in the data plot of
K=A (T−T0)/P
where A is the area of contact between the block and the chuck, To is the chuck temperature; and P is the power. The measured value for thermal conductance was found to be K=55 mW/cm2 K when the chuck and block are in intimate contact, in good agreement with other reported values. As shown in
τ=C/K
where C is the heat capacity of the wafer per unit area. This time constant is about 2 seconds for a 300 mm silicon wafer in intimate contact with the chuck, increasing to about 10 seconds for a 0.01″ gap. The strong variation of contact conductance, and hence time constant, requires very precise gap control, implying the need for electrostatic or vacuum clamping of the wafer on the chuck. Thus another benefit of the present invention operable in the medium pressure regime, over conventional low pressure systems is the ability to allow the use of vacuum clamping of the wafer on the chuck instead of requiring electrostatic clamping.
To completely remove the resist, the wafer may be scanned in a serpentine raster pattern 1014 as shown in
The thermal processes involved in photoresist removal with a scanning plasma jet 1521 in an embodiment of the present invention are illustrated in
The chuck may be heated to increase resist etch rates on the wafer. The chuck may also dissipate the excess heat imparted by the plasma jet. The heat of the jet diffuses rapidly through the wafer, the diffusion length corresponding to the dwell time of the jet being greater than the wafer thickness for even the highest scanning speeds. In one example of the present invention, the lateral diffusion length is only 0.5 cm during a track scan time of about 0.2-0.4 seconds, increasing the width of the heated zone by about 50%. Thus, to a first approximation, the high speed scanning may be understood as the thermodynamic equivalent of a line heater moving across the wafer in the y-direction 1510, perpendicular to the high-speed scanning direction. In one example, vertical heat flow is a slow process with a 2-10 second time constant for a silicon substrate, and is negligible during the time required to scan a single track. There may be instances, however, where vertical heat flow becomes an important thermal factor after several tracks have been scanned.
The balance between jet power, scanning speed, and vertical heat flow may determine the effectiveness of a particular ashing process. To maximize throughput, embodiments of the present invention are operated using a high level of electromagnetic power to activate the plasma jet, which translates directly into a higher etch rate. Increased power also maximizes the generation of reactive gases in the plasma and provides the heat for activating the ashing reaction between the resist and etching gas.
In the case of ion implanted resist, the initial chuck temperature may be set just below the hardbake temperature of the resist. In one example, the initial chuck temperature is set to about 10° C. below the resist hardbake temperature, which may be about 125° C. The resist would be stable at this temperature and no popping should occur. Contact conductance between the wafer and chuck may be maximized, for example, with helium backside cooling to minimize wafer temperature for a given input power density. Finally, the scanning speed may be increased, thereby reducing effective power density in the wafer, to the point where the wafer can be scanned indefinitely without popping. The required speed may be significantly greater than 1 m/s. As scanning proceeds, the wafer temperature gradually rises and the scanning plasma jet creates minute holes in the implanted photoresist crust, making the crust permeable to the gases released from the base resist. Once permeability is achieved, the temperature may be allowed to rise by reducing the scanning speed or by reducing the contact conductance between the wafer holder and the chuck, thereby reducing the amount of heat dissipated through the wafer holder. The result of the pre-scanning process for permeating the photoresist crust may be a rapid removal of the resist from the wafer surface during a secondary scanning operation.
Etching unimplanted resist involves fewer thermal constraints; the initial chuck temperature may be higher, in one example around 200-350° C., and contact conductance and scan speed may be set to be much lower, all leading to higher wafer temperatures and, thus, higher etch rates. In the case of unimplanted resist, contact conductance could be reduced significantly. In one example, the wafer may be raised off the chuck by a few ten thousands of an inch.
As a result of the foregoing, the ashing of high-dose, ion-implanted photoresist may occur as a two-step process in which the crust is first rendered permeable by a low temperature pretreatment process followed by a high temperature resist removal process. The pretreatment process may take place with chuck temperatures below the bake temperature of the resist, in one instance 120° C. This relatively low temperature is required for preventing the ejection of particulates when the crust explodes due to gases evolved by thermal decomposition of the resist in the event that the carbonized crust has not been removed/punctured, a process also known as popping. Once the photoresist crust has been rendered permeable to gases by the pretreatment scanning of the present invention, the temperature of the wafer may be safely raised to enhance the rate of resist removal. Measurements have established and verified the conditions of pretreatment and resist removal in scanned plasma jet ashing of heavily implanted (P, 40 keV, 5×1015/cm2) I-line photoresist from silicon wafers.
To maximize throughput rates of material removal using embodiments of the present invention, the plasma jet may be operated at the maximum possible elecromagnetic power that can be applied. In order to prevent popping during a pretreatment process, it may be then necessary to scan the jet fast enough prevent excessive temperature rise. In one exemplary instance, multiple pretreatment scans may be required to achieve sufficient permeability to prevent popping during the resist removal step. In one example embodiment of the present invention, resist can be removed completely in a single scan at a speed on the order of 50-100 cm/s without changing the substrate temperature. Other settings for process parameters may be used to achieve similar results in differing, but related, embodiments of the present invention.
Other processes besides blister formation may lead to permeability of a crust in an ion implanted photoresist.
In an illustrative example embodiment for practicing the present invention, an optimized process was developed for implanted I-line photoresist (1.2 microns I-line base resist, hardbaked at 120° C., then implanted with phosphorus at an energy of 40 keV, and at a heavy implantation density of 5×1015/cm2) with multiple pretreatment scans (microwave power=2.15 kW, substrate temperature=100° C., scan speed=105 cm/s, O2:N2=9:1, flow=3 slpm, pressure=80 T). This pretreatment was followed by subsequent resist removal scans at 2.5 kW, and 40 cm/s (whereas the other conditions were kept the same as the pretreatment). All crust and base resist was removed off the wafer, and no residue was seen under the scanning electron microscope, as evident in
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
The present invention claims priority under 35 U.S.C. §119(e) to U.S. Provisional Application No. 60/633,673 filed on Dec. 6, 2004.
| Number | Date | Country | |
|---|---|---|---|
| 60633673 | Dec 2004 | US |
