The invention in generally relates to a high density memory device and method for forming the same, and more particularly to a three dimensional (3D) memory device a method for forming the same.
The 3D memory devices, such as a 3D non-volatile memory (NVM) which has a multi-layer stack structure may possess a higher density memory and excellent electrical characteristics, e.g. reliability in data storage and high operating speed, has been provided in order to accommodate the rising demand for superior memory. Moreover, the 3D NVM is a suitable architecture for AI (Artificial Intelligence) application.
A typical method for forming a 3D memory device includes a source/drain formation. The source/drain formation may be performed by implantation through holes. However, it is challenging to evenly apply the implants through the holes having a high aspect ratio by the traditional implantation step, and the source/drain may not be properly formed.
Therefore, there is a need for providing an improved 3D memory device and the method for forming the same to obviate the drawbacks encountered from the prior art.
The invention is directed to a memory device and a method for forming the same. The present disclosure provides a method for forming drain and source regions in the memory device in a better way, so as to provide the memory device having a good electrical property with a reduced production cost.
According to one aspect of the present disclosure, a method for forming a memory device is provided. The method for forming the memory device, comprising: forming a ridge-shaped stack including a plurality of conductive strips stacked on the substrate along a first direction and extending along a second direction; forming a memory layer stacked on a vertical sidewall of the ridge-shaped stack along a third direction; forming a channel layer stacked on a vertical sidewall of the memory layer along the third direction and having a narrow sidewall with a long side extending along the first direction; forming a capping layer stacked on the ridge-shaped stack in the first direction, the capping layer covering the memory layer and the channel layer; and forming a conductive connecting layer stacked on the narrow sidewall along the second direction.
The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings,
It is to be noted that the following descriptions of preferred embodiments of this disclosure are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed. Also, it is also important to point out that there may be other features, elements, steps and parameters for implementing the embodiments of the present disclosure which are not specifically illustrated. Thus, the specification and the drawings are to be regarded as an illustrative sense rather than a restrictive sense. Various modifications and similar arrangements may be provided by the persons skilled in the art within the spirit and scope of the present disclosure. In addition, the illustrations may not be necessarily be drawn to scale, and the identical elements of the embodiments are designated with the same reference numerals.
The method for fabricating a 3D memory device 100 comprises several steps as follows: Firstly, a multi-layer stack 110′ is formed on a substrate 101.
The conductive layers 112′, 114′, 116′ can be formed of a conductive semiconductor material, such as n-type poly-silicon, or n-type epitaxial single crystal silicon, doped with phosphorus or arsenic. Alternatively, the conductive layers 112′, 114′, 116′ can be formed of p-type poly-silicon, or p-type epitaxial single crystal silicon, doped with boron. Still alternatively, the conductive layers 112′, 114′, 116′ can be formed of un-doped semiconductor material, such as un-doped In the present embodiment, the conductive layers 112′, 114′, 116′ are preferably formed of un-doped poly-silicon.
The insulating layers 111′, 113′, 115′, 117′ can be formed of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicate, or others. The thickness of each one of the insulating layers 111′, 113′, 115′, 117′ can be about 20 nm to 40 nm. In some embodiments of the present disclosure, the conductive layers 112′, 114′, 116′ and the insulating layers 111′, 113′, 115′, 117′ can be formed by a deposition process, for example, a low pressure chemical vapor deposition (LPCVD) process.
Next, the multi-layer stack 110′ is patterned to form a plurality of ridge-shaped stacks 110.
In one embodiment, a non-straight angle θ1 (e.g. about 90°) can be formed by the first direction (Z orientation) and the second direction (the Y orientation), a non-straight angle non-straight angle θ2 (e.g. about 90°) can be formed by the third direction (X orientation) and the first direction (the Z orientation), a non-straight angle non-straight angle θ3 (e.g. about 90°) can be formed by the third direction (the X orientation) and the second direction (Y orientation).
The memory material layer 120 may be formed of a composite layer (i.e., an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, by a LPCVD process. However, the structure of the memory material layer 120 is not limited to this regards. In some embodiments, the memory material layer 140 may be selected from a group consisting of an oxide-nitride-oxide-nitride-oxide (ONONO) structure, a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a bandgap engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS) structure, a tantalum nitride-aluminum oxide-silicon nitride-silicon oxide-silicon (TANOS) structure and a metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon (MA BE-SONOS) structure.
The conductive layer 130 may include an electrically conductive material, such as n+-type poly-silicon (n-type epitaxial single crystal silicon) is doped with phosphorus or arsenic, p+-type poly-silicon (p-type epitaxial single crystal silicon) doped with boron or un-doped polysilicon. Alternatively, the conductive layer 130 may be formed of silicide, such as TiSi, CoSi, or SiGe, oxide semiconductor, such as InZnO or InGaZnO, metal, such as Al, Cu, W, Ti, Co, Ni, TiN, TaN, or TaAIN, or a combination of two or more of these materials.
A top portion and a bottom portion of the conductive layer 130 are removed, That is, portions of the conductive layer 130 and the memory material layer 120 covering the top surface 110a of the ridge-shaped stacks 110 and contacting or adjacent to the barrier layer 103 are partially removed, so as to expose the top surface 110a of the ridge-shaped stacks 110 and the barrier layer 103 from the conductive layer 130 and the memory material layer 120. The conductive layer 130 stacked on the memory material layer 120 in the third direction (i.e. X orientation) is remained.
The insulation material layer 140 may be made of an oxide material, such as a material including silicon dioxide. The insulation material layer 140 is filled in the trenches 110t and disposed between the conductive layers 130. The memory material layer 120, the conductive layer 130 and the insulation material layer 140 can be regarded as stacking on the vertical sidewall 110s of the ridge-shaped stacks 110 in sequence along a third direction (i.e. the X orientation).
In the present embodiment, a top portion of insulation material layer 140 may be removed by an etching process, so as to form shallow trenches 140st to expose the insulation material layer 140. A top surface 140a of the etched insulation material layer 140 is regarded as a bottom of the shallow trench 140st. Subsequently, the conductive body 150 is formed in the shallow trench 140st and covering the top surface 140a. The top surface 140a has a vertical height from the substrate 101 smaller than that of the top surface 110a of the ridge-shaped stack 110. A top surface 150a of the conductive body 150 has a same height with the top surface 110a of the ridge-shaped stack 110 measured from the substrate 101.
The conductive body 150 may be formed of conductive semiconductor material, such as n+-type poly-silicon (n-type epitaxial single crystal silicon) doped with phosphorus or arsenic, p+-type poly-silicon (p-type epitaxial single crystal silicon) doped with boron or un-doped polysilicon. In the present embodiment, the conductive body 150 is formed of un-doped polysilicon.
The capping layer 160 entirely covers the top surface 150a of the conductive body 150, the top surface 110a of the ridge-shaped stack 110 and the memory material layer 120. In some embodiments, the capping layer 160 may include a material of SiN, oxide, SiON, or any other material which has a high selectivity for the following chemical dry etching (ODE) process. The capping layer 160 may have a thickness in a range of 100-200 angstroms.
An opening etching process is performed to remove portions of the memory material layer 120, the conductive layer 130, the insulation material layer 140 and the capping layer 160, so as to form a plurality of openings 160t exposing barrier layer 103. The remained portions of the memory material layer 120, the conductive layer 130, the insulation material layer 140 and the capping layer 160 can be divided into a plurality of regions R1-R8 arranged in a twisted layout. In other words, regions R1 and R2 are disposed in a first line L1 parallel to the second direction (Y orientation); regions R3 and R4 are disposed in a second line L2 parallel to the second direction (Y orientation); regions R5 and R6 are disposed in a third line L3 parallel to the second direction (Y orientation); regions R7 and R8 are disposed in a fourth line L4 parallel to the second direction (Y orientation). The regions in adjacent lines are offset in a distance along the second direction (Y orientation). For example, the regions R1 and R3 are respectively aligned with the regions R5 and R7 in the second direction (Y orientation), and the regions R1 and R5 are respectively offset from the regions R3 and R7 in a distance D1 along the second direction (Y orientation).
A memory cell 180 thus can be formed by the remained memory material layer 120 (thereinafter referred to as a memory layer 121) and the remained conductive layer 130 (thereinafter referred to as a channel layer 131) and the corresponding conductive strips 112, 114, 116 disposed on each level of the ridge-shaped stacks 110 on the intersection point thereof.
The conductive connecting layers 171 are stacked on the channel layer 131 and the conductive body 150 in the second direction (i.e. Y orientation). More detailed description about the forming of the conductive connecting layers 171 are described in the following paragraphs corresponding to
Referring to
Referring to
Referring to
Referring to
Since the conductive material 170 can be directly deposited in the notches 130t, the bottom of the notches 130t in the first direction (i.e. Z orientation) can also be filled by the conductive material 170 even if the openings 160t or the notches 130t have a high aspect ratio.
Referring to
During the processes exemplarily shown in
The contacts 190 are formed on the conductive connecting layers 171. The capping layer 160 is penetrated by the contacts 190, and the contacts 190 are surrounded by the capping layer 160. Each of the regions R1-R8 may correspond to two conductive connecting layers 171 having an inverted-U shape, served as a source region Sr and a drain region Dr, respectively. The conductive lines BL1-BL4, SL1-SL4 are formed on and electrically connected to the contacts 190. The contacts 190 and the conductive lines BL1-BL4, SL1-SL4 may be formed of metal. The conductive line BL1 can be used as a bit line to be electrically connected to the drain regions Dr of regions R4 and R8. The conductive line BL2 can be used as a bit line to be electrically connected to the drain regions Dr of regions R2 and R6. The conductive line BL3 can be used as a bit line to be electrically connected to the drain regions Dr of regions R3 and R7. The conductive line BL4 can be used as a bit line to be electrically connected to the drain regions Dr of regions R1 and R5. The conductive line SL1 can be used as a source line to be electrically connected to the source regions Sr of regions R4 and R3. The conductive line SL2 can be used as a source line to be electrically connected to the source regions Sr of regions R2 and R6. The conductive line SL3 can be used as a source line to be electrically connected to the source regions Sr of regions R3 and R7. The conductive line SL4 can be used as a source line to be electrically connected to the source regions Sr of regions R1 and R5. The source lines (e.g. conductive lines SL1-SL4) currents may be summed together for sensing in the AI application.
The 3D memory device 200 is similar to the 3D memory device 100, and the difference is in that the memory layer 221 is remained in the opening 260t after the opening etching process. FIGS, 11A-11D are top views similar to
Referring to
Referring to
Referring to
Referring to
In a first comparative example, source and drain regions are formed by implantation, but the implants may not be able to reach a bottom of the opening having a high aspect ratio. In a second comparative example, source and drain regions are formed by plasma doping without a capping layer stacked on the entire structure. The dopants may be applied to the top conductive body (or plug), and a current path may be generated between the source and drain regions.
The present disclosure discloses a 3D memory device including a capping layer covering the ridge-shaped stack and conductive body, the whole structure can be well protected by the capping layer during the following process, such as the chemical dry etching process, and the 3D memory device of the present disclosure may not be easily damaged and have a better performance. Further, the present disclosure can provide a method to form the source and drain regions of the 3D memory device by depositing the conductive connecting structure stacked on the sidewall of the channel, but not formed by implantation nor the plasma doping method. Therefore, in comparison with the first and second comparative examples, the present disclosure can provide a method to form the source and drain regions in a better way, to make sure that the source and drain regions can be properly formed even if the opening has a high aspect ratio, some elements in the memory device, such as the conductive strips and the conductive body, may not be affected by the implants and the dopants, and the current leakage may not be easily produced. As such, the 3D memory device of the present disclosure has a good electrical property and the method for forming the source and drain regions can be simpler and the production cost can also be reduced.
While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.