Patent Application
20240347423
The present application relates to manufacturing of semiconductor integrated circuits. More particularly, it relates to a metal connection made through a diffusion break area and method of manufacturing the same.
With the introduction of backside power distribution network (BSPDN), power connection between a frontside and a backside of a semiconductor chip or substrate has been actively studied, investigated and various structures have been proposed. For example, one existing approach is to connect frontside active devices to BSPDN through buried power rail (FSBPR) at the frontside and through-silicon-via (TSV) such as nano TSV (nTSV) at the backside. However, this approach only applies to situations where all power lines come from the BSPDN at the backside and no power line exists, at the frontside, at the back-end-of-line (BEOL) level. Moreover, this approach may introduce limitation on the routing capability of the chip, especially for stacked transistors.
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes an array of transistors on a semiconductor substrate, the array of transistors including a first transistor and a second transistor, the second transistor being next to the first transistor; and a metal connection between the first transistor and the second transistor, wherein the metal connection connects a first metal contact at a frontside of the array of transistors to a second metal contact at a backside of the array of transistors.
In one embodiment, a source/drain region of the first transistor and a source/drain region of the second transistor are replaced by the metal connection, rendering the first transistor being a first dummy transistor and the second transistor being a second dummy transistor.
In another embodiment, the first dummy transistor includes a first dummy gate that surrounds a first set of nanosheets, the first set of nanosheets has a first section adjacent to the metal connection and a second section adjacent to a source/drain region of an active transistor, wherein the first section and the second section of the first set of nanosheets comprise different material.
In yet another embodiment, the first section of the first set of nanosheets includes a dielectric material and the second section of the first set of nanosheets includes a silicon material, and the first section of the first set of nanosheets electrically isolates the metal connection from the second section of the first set of nanosheets.
In one embodiment, the metal connection is further electrically isolated from the first dummy gate by a plurality of inner spacers between the first set of nanosheets and by a sidewall spacer above the first set of nanosheets.
In another embodiment, the metal connection includes a first portion between the first and the second dummy gate and the first and the second set of nanosheets, and a second section that is surrounded by a backside interlevel dielectric layer underneath the first and the second dummy transistor.
According to one embodiment, the first dummy transistor includes a first dummy gate that surrounds an end of a first set of nanosheets, and the metal connection is separated from the end of the first set of nanosheets at least by the first dummy gate.
In one embodiment, the metal connection includes a first portion between the first and the second dummy transistor, and a second portion that is surrounded by a dummy diffusion break, and the dummy diffusion break is further surrounded by a backside interlevel dielectric layer underneath the first and the second dummy transistor.
Embodiments of present invention provide a method of forming a semiconductor structure. The method includes forming an array of transistors on a substrate, the array of transistors including a first transistor and a second transistor, the second transistor being next to the first transistor; forming a sacrificial placeholder in the substrate between the first and the second transistor; forming a first portion of a metal connection above the sacrificial placeholder between the first and the second transistor; and forming a second portion of the metal connection in a backside interlevel dielectric layer directly underneath the first portion of the metal connection.
In one embodiment, forming the array of transistors includes forming a raw stack of nanosheets on top of the substrate; and recessing the raw stack of nanosheets to create a first set of nanosheets and a second set of nanosheets, the first transistor includes the first set of nanosheets, and the second transistor includes the second set of nanosheets.
In another embodiment, forming the array of transistors further includes performing a selective etching process of the first and the second set of nanosheets via an opening between the first and the second transistor to create a first set of indentations at the first set of nanosheets and a second set of indentations at the second set of nanosheets.
In one embodiment, the method further includes depositing a dielectric layer into the first and the second set of indentations at the first and the second set of nanosheets and on top of the sacrificial placeholder, wherein forming the first portion of the metal connection comprises forming the first portion of the metal connection in the dielectric layer.
In another embodiment, forming the second portion of the metal connection includes replacing the sacrificial placeholder with the second portion of the metal connection through a deposition process from a backside of the array of transistors.
According to one embodiment, the method further includes forming a dummy diffusion break in the substrate between the first and the second transistor; and forming the sacrificial placeholder in the dummy diffusion break to be surrounded by the dummy diffusion break.
In one embodiment, forming the second portion of the metal connection includes selectively removing the sacrificial placeholder from the dummy diffusion break, and filling an opening created by the removal of the sacrificial placeholder with the second portion of the metal connection.
The present invention will be understood and appreciated more fully from the following detailed description of embodiments of present invention, taken in conjunction with accompanying drawings of which:
It will be appreciated that for simplicity and clarity purpose, elements shown in the drawings have not necessarily been drawn to scale. Further, and if applicable, in various functional block diagrams, two connected devices and/or elements may not necessarily be illustrated as being connected. In some other instances, grouping of certain elements in a functional block diagram may be solely for the purpose of description and may not necessarily imply that they are in a single physical entity, or they are embodied in a single physical entity.
In the below detailed description and the accompanying drawings, it is to be understood that various layers, structures, and regions shown in the drawings are both demonstrative and schematic illustrations thereof that are not drawn to scale. In addition, for the ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given illustration or drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present such as, by way of example only, 1% or less than the stated amount. Likewise, the terms “on”, “over”, or “on top of” that are used herein to describe a positional relationship between two layers or structures are intended to be broadly construed and should not be interpreted as precluding the presence of one or more intervening layers or structures.
Moreover, although various reference numerals may be used across different drawings, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus detailed explanations of the same or similar features, elements, or structures may not be repeated for each of the drawings for economy of description. Labelling for the same or similar elements in some drawings may be omitted as well in order not to overcrowd the drawings.
Embodiments of present invention further provide forming or patterning a raw stack of nanosheets 201 on top of the substrate 110. Subsequently, a set of sacrificial gates 301 may be formed on top of the raw stack of nanosheets 201. The set of sacrificial gates 301 may be formed through a lithographic patterning and etching process such as, for example, by patterning or forming a set of hard masks 401 on top of a layer of dummy gate material and etch the layer of dummy gate material, using the hard masks 401 in a selective etching process, to form the set of sacrificial gates 301. In one embodiment, the set of sacrificial gates 301 may be polysilicon in material. The hard masks 401 may be, for example, silicon-nitride (SiN).
On the other hand, in forming the array of transistors 501, the plurality of stacks of nanosheets may each include a set of nanosheets 202 and a set of sacrificial sheets 203 that is vertically between the set of nanosheets 202. For example, the first dummy transistor 510 may include a first set of nanosheets 202 and the second dummy transistor 520 may include a second set of nanosheets 202. Embodiments of present invention may further provide forming inner spacers 204 at the two ends of the set of sacrificial sheets 203. The inner spacers 204 may be created by first recessing the sacrificial sheets 203 at the two ends thereof, and then depositing a layer of dielectric material in the recessed areas.
In one embodiment, the sidewall spacers 302 and the inner spacers 204 may be nitride such as silicon-nitride (SiN); the set of nanosheets 202 may be silicon (Si) or silicon-germanium (SiGe) with a first germanium (Ge) concentration level; and the set of sacrificial sheets 203 may be SiGe with a second Ge concentration level. The Ge concentration level of the set of nanosheets 202 may range, for example, from 25% to 35% and may be different from the Ge concentration level of the set of sacrificial sheets 203, which may range, for example, from 45% to 55%, such that the set of sacrificial sheets 203 may be selectively removed or etched away in the presence of set of nanosheets 202, as being described below in more details.
Embodiments of present invention further provide recessing an end portion of the exposed first set of nanosheets 202 of the first dummy transistor 510 to create indentations 211 and recessing an end portion of the exposed second set of nanosheets 202 of the second dummy transistor 520 to create indentations 212. In the meantime, the recessing creates a second portion 231 of the first set of nanosheets 202 of the first dummy transistor 510 next to a source/drain region 311 of the first active transistor 530 and creates a second portion 232 of the second set of nanosheets 202 of the second dummy transistor 520 next to a source/drain region 311 of the second active transistor 540. The recessing may be made through an opening 331, between the sacrificial gates 301 of the first and the second dummy transistor 510 and 520, in a selective etching process.
Following the formation of the dielectric layer 601, one or more openings may be created, via a lithographic patterning and etching process, through the dielectric layer 601 and through the dielectric layer 322 to expose the underneath sacrificial placeholder 104, and through the dielectric layer 321 to expose one or more of the source/drain regions 311 of other active transistors such as the first active transistor 530 and/or the second active transistor 540. Next, a conductive material such as, for example, metal may be used to fill the opening or openings to form a first portion 611 of a metal connection 610 between the first and the second dummy transistor 510 and 520 and, for example, a source/drain contact 621 above one of the source/drain regions 311 of an active transistor such as the first active transistor 530.
Embodiments of present invention further provide forming other middle-of-line (MOL) structures and a back-end-of-line (BEOL) 701 on top of the dielectric layer 601 in contact with one or more of the source/drain contacts 621 and in contact with the first portion 611 of the metal connection 610 from the frontside of the semiconductor structure 10. For example, the BEOL 701 may include a metal contact that is in contact with the metal connection 610. A carrier wafer 801 is then bonded onto the semiconductor structure 10 for the purpose of further processing the semiconductor structure 10 from a backside thereof.
Embodiments of present invention may further provide forming one or more backside contacts such as metal contacts in the backside interlevel dielectric layer 602 and at least one of the backside contacts, such as a backside contact 631, known as a backside contact via or metal contact, is in contact with the second portion 612 of the metal connection 610. A backside interconnect structure 702 may subsequently be formed above the one or more backside contacts and above the backside interlevel dielectric layer 602.
As is illustrated in
Embodiments of present invention further provide forming a dummy diffusion break 105 in the silicon layer 103. The dummy diffusion break 105 may be formed after forming the raw stack of nanosheets 201 by breaking the raw stack of nanosheets 201 into two raw stacks of nanosheets, thereby creating an opening between the two raw stacks of nanosheets to expose the underneath silicon layer 103. The dummy diffusion break 105 may then be formed in the exposed portion of the silicon layer 103 through a patterning, etching, and deposition process. However, embodiments of present invention are not limited in this aspect and the dummy diffusion break 105 may be created or formed in the silicon layer 103 before forming the raw stack of nanosheets 201.
Subsequently, a set of sacrificial gates 301 may be formed on top of the raw stack of nanosheets 201. The set of sacrificial gates 301 may be formed through a lithographic patterning and etching process such as, for example, by patterning or forming a set of hard masks 401 on top of a layer of dummy gate material and then selectively etching the layer of dummy gate material to form the set of sacrificial gates 301. One of the sacrificial gates 301 may cover an end of one of the two raw stacks of nanosheets, and another one of the sacrificial gates 301 may cover an end of the other one of the two raw stacks of nanosheets.
In one embodiment, the sidewall spacers 302 and the inner spacers 204 may be nitride such as SiN; the set of nanosheets 202 may be Si or SiGe with a first Ge concentration level; and the set of sacrificial sheets 203 may be SiGe with a second Ge concentration level. The Ge concentration level of the set of nanosheets 202 may range, for example, from 25% to 35% and may be different from the Ge concentration level of the set of sacrificial sheets 203, which may range, for example, from 45% to 55% such that the set of sacrificial sheets 203 may be selectively etched away in the presence of set of nanosheets 202.
Following the formation of the source/drain regions 311, embodiments of present invention provide filling the space or opening above the source/drain regions 311 between the sacrificial gates 301 with a dielectric layer 321. In one embodiment, the dielectric layer 321 may be an interlevel dielectric layer made of a material, such as SiO2, that provide etch selectivity with the sidewall spacers 302 and the underneath sacrificial placeholders 104. A chemical-mechanic-polishing (CMP) process may be applied to planarize a top surface of the semiconductor structure 20, resulting in at least some portion of the hard masks 401 and sidewall spacers 302 being removed.
Embodiments of present invention further provide etching the dummy diffusion break 105 underneath the dielectric layer 321 to create an opening 332 in the dummy diffusion break 105 that exposes the underneath silicon layer 103. The dummy diffusion break 105 and the sidewall spacers 302 may be of different materials such as, for example SiO2 and SiN respectively, such that the exposed portion of dummy diffusion break 105 may be removed in a selective etching process, resulting in the opening 332 that is surrounded by the remaining portion of the dummy diffusion break 105.
Next, embodiments of present invention provide forming, such as through deposition, a dielectric layer 601 above the semiconductor structure 20, covering the replacement metal gates 341, the dielectric layer 321, and the sacrificial placeholder 104 between the first and the second dummy transistor 510 and 520. Following the formation of the dielectric layer 601, one or more openings may be created, through a lithographic patterning and etching process, through the dielectric layer 601, through the dielectric layer 321 to expose one or more source/drain regions 311 of other active transistors, and partially into the sacrificial placeholder 104 between the first and the second dummy transistor 510 and 520. In one embodiment, the opening created in the sacrificial placeholder 104 between the first and the second dummy transistor 510 and 520 may have a depth substantially close to a top surface of the silicon layer 103. Next, a conductive material such as, for example, metal may be used to fill the opening or openings to form a first portion 611 of a metal connection 610 between the first and the second dummy transistor 510 and 520 and, for example, form a source/drain contact 621 above one of the source/drain regions 311 of an active transistor such as the first active transistor 530. The first portion 611 of the metal connection 610 may be between the first and the second dummy gate of the first and the second dummy transistor 510 and 520 and may be electrically isolated from the first and the second dummy gate. In other words, the end of the first and the second set of nanosheets 202 of the first and the second dummy transistor 510 and 520 may be separated and/or insulated from the metal connection 610, and in particular from the first portion 611 of the metal connection 610 by at least the sidewall spacers 302.
Embodiments of present invention further provide forming other middle-of-line (MOL) structures and a back-end-of-line (BEOL) 701 on top of the dielectric layer 601 in contact with one or more of the source/drain contacts 621 and in contact with the first portion 611 of the metal connection 610. For example, at least one metal contact in the BEOL 701, at the frontside of the semiconductor structure 20, is in contact with the metal connection 610 or more particularly with the first portion 611 of the metal connection 610. A carrier wafer 801 is then bonded onto the semiconductor structure 20 for further device processing from a backside of the semiconductor structure 20.
Embodiments of present invention may further provide forming one or more backside contacts in the backside interlevel dielectric layer 602 and at least one of the backside contacts, such as a backside contact 631, which may be a metal contact, is in contact with the second portion 612 of the metal connection 610. A backside interconnect structure 702 may subsequently be formed above the one or more backside contacts or metal contacts and above the backside interlevel dielectric layer 602.
It is to be understood that the exemplary methods discussed herein may be readily incorporated with other semiconductor processing flows, semiconductor devices, and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
Accordingly, at least portions of one or more of the semiconductor structures described herein may be implemented in integrated circuits. The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip may be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other high-level carrier) or in a multichip package (such as a ceramic carrier that has surface interconnections and/or buried interconnections). In any case the chip may then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product, such as a motherboard, or an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions above have been presented for the purposes of illustration of various embodiments of present invention and they are not intended to be exhaustive and present invention are not limited to the embodiments disclosed. The terminology used herein was chosen to best explain the principles of the embodiments, practical application or technical improvement over technologies found in the marketplace, and to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. Such changes, modification, and/or alternative embodiments may be made without departing from the spirit of present invention and are hereby all contemplated and considered within the scope of present invention. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the spirit of the invention.
