Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide

Abstract
Embodiments of the present invention are directed to metallic solderability preservation coating on connectors of semiconductor package to prevent oxide. Singulated semiconductor packages can have contaminants, such as oxides, on exposed metal areas of the connectors. Oxidation typically occurs on the exposed metal areas when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the connectors from soldering well. An anti-tarnish solution of the present invention is used to coat the connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution is a metallic solution, which advantageously allows the semiconductor packages to not need be assembled immediately after fabrication.
Description
FIELD OF THE INVENTION

The present invention is related to the field of semiconductor device manufacturing. More specifically, the present invention relates to metallic solderability preservation coating on metal part of semiconductor package to prevent oxide.


BACKGROUND

A semiconductor device array contains individual integrated circuits or semiconductor packages. Connectors 105 of the semiconductor packages are exposed at the top of the semiconductor array 100, as illustrated in FIG. 1A. The connectors 105 are typically made of copper. To prevent oxidation on the copper surface, the connectors 105 are plated with a lead finished material, such as matte tin (Sn), using electroplating. As a result, the top surfaces of the connectors 105′ are thereafter tin plated, as illustrated in FIG. 1B.


Singulation is a process of separating each semiconductor package from a molded sheet. Dicing or sawing is a process that singulates the semiconductor array 100′ into individual or singulated semiconductor packages. Conventionally, the electroplated semiconductor array 100′ is diced into singulated semiconductor packages to be shipped to customers for assembly onto printed circuit boards. FIG. 1C illustrates a saw 115 dicing the semiconductor array 100′. The saw 115 typically follows a saw path 110 across the plated connectors 105′, resulting in connectors on peripheral edges of the singulated semiconductor packages.



FIG. 2A illustrates a singulated semiconductor package 200 having a plurality of connectors 205 on the peripheral edges. Although tops of the connectors 205a are tin plated, sidewalls of the connectors 205b are exposed (e.g., without tin plating), because the dicing occurred after the semiconductor array 100 was electroplated with the lead finished material. If the singulated semiconductor package 200 is stored in inappropriate environments and/or conditions (e.g., moisture in the air, acids, bases, salts, oils, aggressive metal polished, and other solid and liquid chemicals) after singulation, then the exposed surfaces 205b become sites for potential corrosion 210 such as copper oxide, as illustrated in FIG. 2B. This aging process is known as oxidation. The exposed surfaces 205b, usually deposited with pollutant layers of oxide and other nonmetallic compound 210, often interfere with or inhibit solder wettability. The resulting oxide layer reduces solderability because contamination 210 prevents the metal from soldering well. The rate of oxidation can increase with an increase in temperature or humidity. Solder problems are a common cause for device failures.


A perfectly clean surface is required for assembly of singulated semiconductor packages 200 onto printed circuit boards. Since metal oxides form a barrier that prevents molten solder from forming a true metallurgical bond, the metal oxides must be removed prior to soldering or must be avoided in the first place.


The present invention addresses at least these limitations in the prior art.


SUMMARY OF THE DISCLOSURE

A first aspect of the present invention is for a method of preventing contaminants from forming on metal surfaces of semiconductor package connectors. The method includes performing a first cleaning of a semiconductor package using a cleaner agent, thereby reducing surface tension of unexpected material. Performing the first cleaning includes immersing the semiconductor package in the cleaner agent. In some embodiments, the semiconductor package is immersed in the cleaner agent for five minutes at 50° C. In some embodiments, the cleaner agent is acid. The method further includes performing a first DI water rinsing of the semiconductor package, thereby removing the undesired material and the cleaner agent. The method further includes performing a second cleaning of the semiconductor package. In some embodiments, the second cleaning is micro-etching, wherein the micro-etching creates a uniform topography on the surfaces of the metal connectors. In some embodiments, the second cleaning includes immersing the semiconductor package in a chemical bath. The chemical bath is hydrogen peroxide, sulphuric acid, sodium persulfate, or any suitable chemical bath. In some embodiments, the semiconductor package is immersed in the chemical bath for about 60 seconds at 40° C. The method further includes performing a second DI water rinsing of the semiconductor package, thereby ensuring exposed surfaces of metal connectors are clean and ready for treatment. The semiconductor package is predipped, thereby activating the surfaces. In some embodiments, the predipping includes removing oxides and wetting the clean surfaces for 30 seconds at 30° C. in a predip solution, wherein the wet surfaces promotes a homogeneous metallic surface finishing. The predip solution is preferably an organic aqueous dispersion that has an efficient anti-tarnishing effect. The method further includes treating the semiconductor package with an anti-tarnish solution. In some embodiments, the treating step includes spraying the semiconductor package with the anti-tarnish solution. Alternatively, the treating step includes dipping the semiconductor package with the anti-tarnish solution. The anti-tarnish solution is preferably a metallic solution. In some embodiments, the anti-tarnish solution is applied to the semiconductor package at 45-52° C. or at 63-68° C. The anti-tarnish solution is applied to the semiconductor package for four to twelve minutes. The method further includes performing a third DI water rinsing of the semiconductor package, thereby cleaning excess chemical and ionic contaminants, and postdipping the semiconductor package, thereby protecting a metallic coating. The metallic coating prevents oxidation. A postdip solution is one of acid or alkaline base. The method further includes preforming a fourth DI water rinsing of the semiconductor package, and drying the semiconductor package. In some embodiments, the method further includes soldering the semiconductor package to a printed circuit board.


A second aspect of the present invention is for a method of preventing contaminants from forming on metal surfaces of semiconductor package connector. The method includes treating a semiconductor package with an anti-tarnish solution. In some embodiments, the treating step includes spraying the semiconductor package with the anti-tarnish solution. Alternatively, the treating step includes dipping the semiconductor package with the anti-tarnish solution. The anti-tarnish solution is preferably a metallic solution. In some embodiments, the anti-tarnish solution is applied to the semiconductor package at 45-52° C. or at 63-68° C. The anti-tarnish solution is applied to the semiconductor package for four to twelve minutes. The method further includes performing a first DI water rinsing of the semiconductor package, thereby cleaning excess chemical and ionic contaminants, and drying the semiconductor package. In some embodiments, the method further includes soldering the semiconductor package to a printed circuit board.


A third aspect of the present invention is also for a method of preventing contaminants from forming on metal surfaces of semiconductor package connector. The method includes creating a mixture for use during singulation, and spraying a semiconductor array with the mixture during singulation, thereby treating a plurality of semiconductor packages. This creating step includes adding an anti-tarnish solution to a cutting fluid. The anti-tarnish solution is a metallic solution. In some embodiments, the anti-tarnish solution is applied to the plurality of semiconductor packages at 45-52° C. or at 63-68° C. The anti-tarnish solution is applied to the plurality of semiconductor packages for four to twelve minutes. The method further includes performing a first DI water rinsing of at least one semiconductor package, and drying the at least one semiconductor package. In some embodiments, the method further includes soldering the at least one semiconductor package to a printed circuit board.


A fourth aspect of the present invention is for a method of preserving metallic solderability of a semiconductor package. The method includes coating connectors with a metallic solution, wherein the coating occurs during or after sawing a semiconductor array, wherein the sawing creates a plurality of semiconductor packages, wherein the metallic solution is configured to prevent metal oxidation. The metallic solution is an anti-tarnish solution. The metallic solution is tin, silver, gold, nickel-gold, or any suitable metallic solution. In some embodiments, the coating is applied via dipping the semiconductor package in the metallic solution or by spraying the semiconductor package with the metallic solution when the coating occurs after sawing the semiconductor array. In some embodiments, the coating is applied via spraying when the coating occurs during sawing of the semiconductor array. In some embodiments, the coating occurs at 45-52° C. or at 63-68° C. The coating is applied for four to twelve minutes. In some embodiments, the method includes, before the coating, performing at least one cleaning and at least one rinsing of the semiconductor package when the semiconductor package is exposed to contaminants. In some embodiments, the method further includes soldering the semiconductor package to a printed circuit board.


A fifth aspect of the present invention is for a metallic solderability preservation method. A semiconductor array is loaded into a singulation machine. The semiconductor array includes a plurality of semiconductor packages. The semiconductor packages are treated with an anti-tarnish solution, thereby plating all exposed surfaces of semiconductor connectors. In some embodiments, the loading step includes mixing the anti-tarnish solution with a cutting fluid, such that the treating occurs when the mixture is sprayed on the semiconductor array during dicing. Alternatively, the semiconductor packages are sprayed with the anti-tarnish solution after singulation. Alternatively, the semiconductor packages are dipped into the anti-tarnish solution after singulation. In some embodiments, the anti-tarnish solution is a metallic solution. The metallic solution is one of tin, silver, gold, and nickel-gold. In some embodiments, the anti-metallic solution is applied at 45-52° C. or at 63-68° C. The anti-metallic solution is applied for four to twelve minutes. In some embodiments, the method further includes soldering the semiconductor package to a printed circuit board.





BRIEF DESCRIPTION OF THE DRAWINGS

The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures.



FIG. 1A illustrates an exemplary semiconductor array.



FIG. 1B illustrates the semiconductor array with connectors coated with tin.



FIG. 1C illustrates the semiconductor array being diced with a saw.



FIG. 2A illustrates a singulated semiconductor package having a plurality of connectors on peripheral edges.



FIG. 2B illustrates the plurality of connectors with contaminants.



FIG. 3 illustrates an exemplary method of protecting a singulated semiconductor package in one embodiment of the present invention.



FIG. 4 illustrates another exemplary method of protecting a singulated semiconductor package in one embodiment of the present invention.



FIG. 5 illustrates yet another exemplary method of protecting a singulated semiconductor package in one embodiment of the present invention.



FIG. 6A illustrates metallic coating to singulated semiconductor packages via a spraying technique in some embodiments of the present invention.



FIG. 6B illustrates metallic coating to singulated semiconductor packages via a dipping technique in some embodiments of the present invention.



FIG. 7 illustrates a treated singulated semiconductor package in some embodiments of the present invention.





DETAILED DESCRIPTION

In the following description, numerous details are set forth for purposes of explanation. However, one of ordinary skill in the art will realize that the invention can be practiced without the use of these specific details. Thus, the present invention is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features described herein or with equivalent alternatives.


Reference will now be made in detail to implementations of the present invention as illustrated in the accompanying drawings. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.


Embodiments of the present invention are directed to a metallic solderability preservation (MSP) coating on metallic contacts of semiconductor package to prevent formulation of oxides. Singulated semiconductor packages can have unexpected material or contaminants, including fingerprints and oxides, on exposed metal areas of semiconductor connectors, including top surfaces and sidewalls. For example, oxidation typically occurs on exposed copper areas of these connectors when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the metal from soldering well.


An anti-tarnish solution of the present invention is used to coat the metal connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution in some embodiments is a metallic solution, such as tin, silver, gold, nickel-gold, or any suitable solution. Coating the exposed copper areas with an anti-tarnish solution protects the exposed copper from oxidation. Such coating advantageously allows the semiconductor packages to not need be assembled (e.g., soldered to printed circuit boards) immediately after fabrication.


As discussed above, singulated semiconductor packages can be protected from oxidation during or after a sawing process of a semiconductor array, regardless whether the semiconductor array has been previously electroplated. If a singulated semiconductor package is assembled some time after the sawing process, then it is likely that the singulated semiconductor package has been exposed to contaminants, especially if the singulated semiconductor package had not been stored properly. As such, additional measures are taken to ensure that the connectors are free from debris before the preservation of metallic solderability. If the singulated semiconductor package is assembled immediately after the sawing process, then additional measures need not be taken since the singulated semiconductor package has not been exposed to contaminants. Each of the scenarios of metallic solderability preservation is explored in detail below.


Scenario 1: Preservation after Sawing and Exposure to Contaminants


In some embodiments, an anti-tarnish solution is coated on exposed metal areas of connectors after a singulated semiconductor package has been exposed to contaminants, such as oxides. As discussed above, oxidation occurs when the semiconductor package is not stored in an appropriate environment after fabrication. Exposed metal areas of the connectors include at least sidewalls of the connectors. Top surfaces of the connectors are also exposed if the semiconductor array had not been previously electroplated.


Assuming that the semiconductor package has been singulated from a semiconductor array and has not yet been assembled (e.g., soldered to a printed circuit board), FIG. 3 illustrates an exemplary method 300 of protecting a singulated semiconductor package in one embodiment of the present invention. The process starts at Step 305 with a first cleaning of the semiconductor package using a cleaner agent. The cleaner agent helps reduce surface tension of unexpected material on the semiconductor package. In some embodiments, the semiconductor package is immersed in the cleaner agent for five minutes at a temperature of 50° C. In some embodiments, the cleaner agent is acid, which acts as a detergency and emulsification to effectively remove contaminants, such as oxides and fingerprints.


At a Step 310, a first deionized (DI) water rinse is performed. The DI water is used to rinse the semiconductor package to remove contaminants and the cleaner agent.


At a Step 315, a second cleaning step is performed. In some embodiments, the second cleaning step is micro-etching. Preferably, micro-etching creates a uniform topography on the surfaces of the metal connectors. Various chemical baths can be used for micro-etching the connectors, such as hydrogen peroxide, sulphuric acid, sodium persulfate, or any suitable chemical. In some embodiments, the semiconductor package is immersed in the chemical bath for about 60 seconds at a temperature of 40° C.


At a Step 320, a second DI water rinse is performed. The second DI water rinse ensures that exposed surfaces of the metal connectors are clean and are ready for treatment and protection.


However, before treatment and protection, at a Step 325, a predip is performed to activate the surfaces of the metal connectors. In some embodiments, the process time of removing the remaining oxides and/or contaminants and wetting the surfaces is performed for 30 seconds at a temperature of 30° C. The “wet” surfaces promote a homogeneous metallic surface finishing. In some embodiments, the predip solution is an organic aqueous dispersion that has an efficient anti-tarnishing effect.


At a Step 330, a metallic coating is applied using an anti-tarnish solution. The anti-tarnish solution in some embodiments is a metallic solution, such as tin, silver, gold, nickel-gold, or any suitable solution. Depending on the desired thickness of the metallic film, the metallic coating can be applied in either a high or low temperature for four to twelve minutes via a dipping method or a spraying method. In some embodiments, at a relatively low temperature of 45-52° C., the metallic film thickness is about 0.35 micron. In some embodiments, at a relatively high temperature of 63-68° C., the metallic film thickness is about 1 micron.


The metallic coating can be applied to singulated semiconductor packages 605 via spraying the singulated semiconductor packages 605 using the anti-tarnish solution 610, as illustrated in FIG. 6A, or via dipping the singulated semiconductor packages 605 in the anti-tarnish solution 610, as illustrated in FIG. 6B. The MSP spraying and the MSP dipping, as illustrated, are electrodeless plating techniques. Other electrodeless plating techniques to apply the metallic coating on the semiconductor package are contemplated.


Although the singulated semiconductor packages 605 are shown in FIGS. 6A-6B as having been through electroplating (e.g., top surfaces of connectors are plated), the methods of protecting a singulated semiconductor package described in FIGS. 3-5 also apply to semiconductor arrays that have not been electroplated (e.g., top surfaces of connectors are not plated), in which both top surfaces and sidewalls are coated at the same time via the MSP process. In some embodiments, metallic coating on the top surfaces of connectors by electroplating has a thickness of about 10 microns, while metallic coating on sidewalls of connectors by MSP has a thickness of 1 micron.


Metal whiskering is the spontaneous growth of filiform hairs from a metallic surface. Whiskers cause short circuits and arcing in electrical circuits. If the semiconductor array had been previously electroplated with tin, then tin whiskering may occur. If metallic ion is tin deposit, then tin whiskering is a concerned element. Tin whiskers act like miniature antennas, affecting circuit impedance. Tin whiskers can reduce the conductivity of tin plating. Using a silver (Ag) derivative as an additive in a tin bath helps prevent whisker growth by creating an Ag film on the clean exposed surfaces. The Ag film advantageously decreases both stress formation and velocity of intermetallic layer build up. By the way, whisker growth is not issue for silver, gold, nickle-gold coating.


It should be understood that embodiments of the present invention can be applied to semiconductor packages that have been previously coated with, for example, tin. In such a case, the metallic solution of the present invention would also be used as a “filler.” Since the metallic solution can be used as a filler, costs can be minimized because a thinner film of the metallic solution can be applied rather than a thicker film on the surfaces.


In some embodiments, a separate rinse is not required between the Step 330 and the Step 325 because the predip solution does not contain additives. In some embodiments, the predip solution and the metallic coating use the same components. In other embodiments, a separate rinse is able to be performed between the Step 330 and the Step 325.


At a Step 335, a third DI water rinse is performed. The third DI water rinse cleans excess chemicals and any ionic contaminants before the metallic coating is protected with a postdip solution. In some embodiments, the DI water used at the Step 335 is hot.


At a Step 340, a postdip is performed to prevent oxidation reaction on the metal coating by using an acid or alkaline base. The postdip is performed for treatments of both spraying and dipping.


At a Step 345, a fourth DI water rinse is performed. In some embodiments, the DI water used at the Step 345 is hot. In other embodiments, the DI water used at the Step 345 is at room temperature.


At a Step 350, the semiconductor package is placed in a dryer. In some embodiments, the dryer is an oven. The process 300 terminates after the Step 350. At any time after preserving the metallic solderability, the semiconductor package can be soldered to a printed circuit board since the connectors have been protected or preserved, which advantageously prevents metal oxidation.


Scenario 2: Preservation Immediately after Sawing but Before Exposure to Contaminants


In some embodiments, an anti-tarnish solution is coated on exposed metal areas of connectors of a singulated semiconductor package immediately after sawing a semiconductor array but before the singulated semiconductor package has been exposed to contaminants. Since the semiconductor package has not been exposed to contaminants during fabrication, cleaning the semiconductor package prior to treatment is therefore not necessary. Such cleaning is to remove possible contaminants.


Assuming that the semiconductor package has been singulated from a semiconductor array and has not yet been assembled (e.g. soldered to a printed circuit board), FIG. 4 illustrates another exemplary method 400 of protecting the singulated semiconductor package in one embodiment of the present invention. The process starts at a Step 405 by applying a metallic coating to the recently singulated semiconductor package using an anti-tarnish solution. Since the Step 405 is similar to the Step 330 discussed above, the Step 405 is not detailed here.


At a Step 410, a first DI water rinse is performed. The first DI water rinse cleans excess chemicals and any ionic contaminants. The Step 410 is similar to the Step 335.


In some embodiments, a post dip and a second DI water rinse are performed after the first DI water rinse. Although these steps are not illustrated, they are similar to the Steps 340 and 345 described above.


At a Step 415, the semiconductor package is placed in a dryer. In some embodiments, the dryer is an oven. The process 400 terminates after the Step 415. At any time after preserving the metallic solderability, the semiconductor package can be soldered to a printed circuit board since the connectors have been protected or preserved, which advantageously prevents metal oxidation.


Scenario 3: Preservation During Sawing


In some embodiments, singulated semiconductor packages can be protected from oxidation during a sawing process. Since the semiconductor packages would not have been exposed to contaminants during fabrication, cleaning the semiconductor packages prior to treatment is therefore not necessary. Such cleaning is to remove possible contaminants.


Assuming that the semiconductor packages have not yet been singulated from a semiconductor array, FIG. 5 illustrates yet another exemplary method 500 of protecting singulated semiconductor packages in one embodiment of the present invention. The process starts at a Step 505 by loading the semiconductor array that needs to be diced in a singulation saw machine.


At a Step 510, an anti-tarnish solution, such as the ones discussed above, is applied to a cutting fluid to form a mixture. The cutting fluid is typically used to cool the blade of the singulation saw machine during sawing. In some embodiments, the Step 505 and the Step 510 are interchangeable or can be performed simultaneously.


At a Step 515, the mixture is sprayed during the sawing process of the semiconductor array. The sawing process dices the semiconductor array into a plurality of singulated semiconductor packages. Each singulated semiconductor package is thereby treated with the anti-tarnish solution. In other words, each singulated semiconductor package is coated with a layer of metal, such as tin, silver, gold, nickel-gold, or any suitable solution.


At a Step 520, a first DI water rinse is performed. The first DI water rinse cleans excess chemicals and any ionic contaminants. In some embodiments, the DI water used at the Step 520 is hot. After preserving the metallic solderability, the semiconductor packages can be soldered to printed circuit boards.


In some embodiments, a post dip and a second DI water rinse are performed after the first DI water rinse. Although these steps are not illustrated, they are similar to the Steps 340 and 345 described above.


At a Step 525, the singulated semiconductor packages are placed in a dryer. In some embodiments, the dryer is an oven. The process 500 terminates after the Step 525. At any time after preserving the metallic solderability, the semiconductor package can be soldered to a printed circuit board since the connectors have been protected or preserved, which advantageously prevents metal oxidation.


It should be understood that MSP can be applied in other scenarios to prevent contaminations, such oxides, on metal parts by coating the metal parts with an anti-tarnish solution.


Singulated Semiconductor Packages with MSP Coating


Embodiments of the present invention advantageously improves the quality of package soldering to printed circuit boards since contaminants are removed prior to soldering. Further, each of the above described methods advantageously prevents oxidation on the metal conductors of a semiconductor packages.



FIG. 7 illustrates a treated singulated semiconductor package 700 in some embodiments of the present invention. It is possible to distinguish between a semiconductor package with and a semiconductor package without MSP. Particularly, a semiconductor package without MSP has connectors that are copperish in color, specifically at least the sidewalls of the connectors, as illustrated in FIG. 2A. In contrast, a semiconductor package with MSP has connectors that are entirely metallically coated. As illustrated in FIG. 7, top surfaces and sidewalls of the connectors 705 have the same metallic color. However, the colors will be different if two types of metal are used, for example, tin for the top surfaces and gold for the side walls.


The metallic coating in some embodiments is a dense metal grain deposit with large and polygonized crystal structures that preserve metallic solderability. The metallic coating can be of tin, silver, gold, nickel-gold, or any suitable metallic coating. Metallic solderability preservation protects the connectors of the semiconductor package from moisture, thereby preventing metal oxidation. Metallic solderability preservation allows a full semiconductor array to be diced prior to shipping.


While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art will understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.

Claims
  • 1. A method of preventing contaminants from forming on metal surfaces of connectors of a semiconductor package, wherein each connector includes a first surface exposed at and flushed with a first package surface before singulation, the method comprising: a. exposing a second surface of each connector after singulation such that the second surface is flushed with a second package surface;b. upon singulation, treating the first surface and the second surface with an anti-tarnish solution;c. performing a first DI water rinsing of the semiconductor package, thereby cleaning excess chemical and ionic contaminants; andd. drying the semiconductor package.
  • 2. The method of claim 1, wherein the treating includes spraying the semiconductor package with the anti-tarnish solution.
  • 3. The method of claim 1, wherein the treating includes dipping the semiconductor package with the anti-tarnish solution.
  • 4. The method of claim 1, wherein the anti-tarnish solution is a metallic solution.
  • 5. The method of claim 1, wherein the anti-tarnish solution is applied to the semiconductor package at 45-52° C. or at 63-68° C.
  • 6. The method of claim 1, wherein the anti-tarnish solution is applied to the semiconductor package for four to twelve minutes.
  • 7. The method of claim 1, further comprising coupling the semiconductor package to a PCB.
  • 8. The method of claim 1, wherein the first DI water is hot.
  • 9. The method of claim 1, further comprising, after cleaning and before drying: a. preventing oxidation reaction on the first surface and the second surface treated with the anti-tarnish solution; andb. rinsing the semiconductor package with a second DI water.
  • 10. The method of claim 1, wherein the first surface and the second surface are not cleaned prior to treatment.
  • 11. The method of claim 1, wherein the first surface and the second surface are treated once.
RELATED APPLICATIONS

This application is a Divisional Application of co-pending U.S. patent application Ser. No. 12/579,574 filed Oct. 15, 2009 and titled “Metallic Solderability Preservation Coating on Metal Part of Semiconductor Package to Prevent Oxide,” which in turn claims benefit of priority under 35 U.S.C. section 119(e) of the U.S. Provisional Patent Application Ser. No. 61/210,125 filed Mar. 12, 2009, entitled “Metallic Solderability Preservation (MSP) Coating on Metal Part of Semiconductor Package to Prevent Oxide,” all of which are hereby incorporated by reference in its entirety.

US Referenced Citations (137)
Number Name Date Kind
3611061 Segerson Oct 1971 A
4411719 Lindberg Oct 1983 A
4501960 Jouvet et al. Feb 1985 A
4801561 Sankhagowit Jan 1989 A
4855672 Shreeve Aug 1989 A
5247248 Fukunaga Sep 1993 A
5248075 Young et al. Sep 1993 A
5396185 Honma et al. Mar 1995 A
5397921 Karnezos Mar 1995 A
5455455 Badehi Oct 1995 A
5479105 Kim et al. Dec 1995 A
5535101 Miles et al. Jul 1996 A
5596231 Combs Jan 1997 A
5843808 Karnezos Dec 1998 A
5866949 Schueller Feb 1999 A
5990692 Jeong et al. Nov 1999 A
6072239 Yoneda et al. Jun 2000 A
6111324 Sheppard et al. Aug 2000 A
6136460 Chen et al. Oct 2000 A
6159770 Tetaka et al. Dec 2000 A
6229200 Mclellan et al. May 2001 B1
6242281 Mclellan et al. Jun 2001 B1
6284569 Sheppard et al. Sep 2001 B1
6285075 Combs et al. Sep 2001 B1
6294100 Fan et al. Sep 2001 B1
6304000 Isshiki et al. Oct 2001 B1
6326678 Karnezos et al. Dec 2001 B1
6329711 Kawahara et al. Dec 2001 B1
6353263 Dotta et al. Mar 2002 B1
6376921 Yoneda et al. Apr 2002 B1
6392427 Yang May 2002 B1
6400004 Fan et al. Jun 2002 B1
6414385 Huang et al. Jul 2002 B1
6429048 McLellan et al. Aug 2002 B1
6451709 Hembree Sep 2002 B1
6455348 Yamaguchi Sep 2002 B1
6489218 Kim et al. Dec 2002 B1
6498099 McLellan et al. Dec 2002 B1
6506314 Whitney, Jr. et al. Jan 2003 B1
6507116 Caletka et al. Jan 2003 B1
6545332 Huang Apr 2003 B2
6545347 McClellan Apr 2003 B2
6552417 Combs Apr 2003 B2
6552423 Song et al. Apr 2003 B2
6566740 Yasunaga et al. May 2003 B2
6573121 Yoneda et al. Jun 2003 B2
6585905 Fan et al. Jul 2003 B1
6586834 Sze et al. Jul 2003 B1
6635957 Kwan et al. Oct 2003 B2
6639308 Crowley et al. Oct 2003 B1
6660626 Lin Dec 2003 B1
6667191 McLellan et al. Dec 2003 B1
6686667 Chen et al. Feb 2004 B2
6703696 Ikenaga et al. Mar 2004 B2
6724071 Combs Apr 2004 B2
6734044 Lin et al. May 2004 B1
6734552 Combs et al. May 2004 B2
6737755 McLellan et al. May 2004 B1
6764880 Wu et al. Jul 2004 B2
6781242 Fan et al. Aug 2004 B1
6800948 Fan et al. Oct 2004 B1
6812552 Islam et al. Nov 2004 B2
6818472 Fan et al. Nov 2004 B1
6818978 Fan Nov 2004 B1
6818980 Pedron, Jr. Nov 2004 B1
6841859 Thamby et al. Jan 2005 B1
6876066 Fee et al. Apr 2005 B2
6897428 Minamio et al. May 2005 B2
6933176 Kirloskar et al. Aug 2005 B1
6933594 McLellan et al. Aug 2005 B2
6940154 Pedron et al. Sep 2005 B2
6946324 McLellan et al. Sep 2005 B1
6964918 Fan et al. Nov 2005 B1
6967126 Lee et al. Nov 2005 B2
6969638 Estepa et al. Nov 2005 B2
6979594 Fan et al. Dec 2005 B1
6982491 Fan et al. Jan 2006 B1
6984785 Diao et al. Jan 2006 B1
6989294 McLellan et al. Jan 2006 B1
6995460 McLellan et al. Feb 2006 B1
7008825 Bancod et al. Mar 2006 B1
7009286 Kirloskar et al. Mar 2006 B1
7049177 Fan et al. May 2006 B1
7060535 Sirinorakul et al. Jun 2006 B1
7071545 Patel et al. Jul 2006 B1
7091581 McLellan et al. Aug 2006 B1
7101210 Lin et al. Sep 2006 B2
7102210 Ichikawa Sep 2006 B2
7205178 Shiu et al. Apr 2007 B2
7224048 McLellan et al. May 2007 B1
7247526 Fan et al. Jul 2007 B1
7274088 Wu et al. Sep 2007 B2
7314820 Lin et al. Jan 2008 B2
7315080 Fan et al. Jan 2008 B1
7320937 Pal et al. Jan 2008 B1
7342305 Diao et al. Mar 2008 B1
7344920 Kirloskar et al. Mar 2008 B1
7348663 Kirloskar et al. Mar 2008 B1
7358119 McLellan et al. Apr 2008 B2
7371610 Fan et al. May 2008 B1
7372151 Fan et al. May 2008 B1
7381588 Patel et al. Jun 2008 B1
7399658 Shim et al. Jul 2008 B2
7408251 Hata et al. Aug 2008 B2
7411289 McLellan et al. Aug 2008 B1
7449771 Fan et al. Nov 2008 B1
7482690 Fan et al. Jan 2009 B1
7595225 Fan et al. Sep 2009 B1
7714418 Lim et al. May 2010 B2
20030006055 Chien-Hung et al. Jan 2003 A1
20030045032 Abe Mar 2003 A1
20030071333 Matsuzawa Apr 2003 A1
20030143776 Pedron, Jr. et al. Jul 2003 A1
20030178719 Combs et al. Sep 2003 A1
20030201520 Knapp et al. Oct 2003 A1
20030207498 Islam et al. Nov 2003 A1
20040014257 Kim et al. Jan 2004 A1
20040046237 Abe et al. Mar 2004 A1
20040046241 Combs et al. Mar 2004 A1
20040080025 Kasahara et al. Apr 2004 A1
20040110319 Fukutomi et al. Jun 2004 A1
20040209443 Cadieux Oct 2004 A1
20050003586 Shimanuki et al. Jan 2005 A1
20050037618 Lee et al. Feb 2005 A1
20050077613 McLellan et al. Apr 2005 A1
20060192295 Lee et al. Aug 2006 A1
20060223229 Kirloskar et al. Oct 2006 A1
20060223237 Combs et al. Oct 2006 A1
20060273433 Itou et al. Dec 2006 A1
20070001278 Jeon et al. Jan 2007 A1
20070090497 Abbott Apr 2007 A1
20070090529 McCarthy et al. Apr 2007 A1
20070200210 Zhao et al. Aug 2007 A1
20070235217 Workman Oct 2007 A1
20080048308 Lam Feb 2008 A1
20080150094 Anderson Jun 2008 A1
20080246132 Kasuya et al. Oct 2008 A1
Non-Patent Literature Citations (6)
Entry
Michael Quirk and Julian Serda, Semiconductor Manufacturing Technology, Pearson Education International, Pearson Prentice Hall , 2001, p. 587-588.
Final Office Action dated Nov. 8, 2011, U.S. Appl. No. 12/579,600, filed Oct. 15, 2009, Woraya Benjavasukul et al.
Non-Final Office Action dated May 26, 2011, U.S. Appl. No. 12/579,600, filed Oct. 15, 2009, Woraya Benjavasukul et al.
Non-Final Office Action dated Feb. 15, 2012, U.S. Appl. No. 12/579,600, filed Oct. 15, 2009, Woraya Benjavasukul et al.
Office Action dated Jun. 22, 2012, U.S. Appl. No. 12/579,600, filed Oct. 15, 2009, Woraya Benjavasukul et al.
Office Action dated Jul. 9, 2012, U.S. Appl. No. 12/579,574, filed Oct. 15, 2009, Woraya Benjavasukul.
Related Publications (1)
Number Date Country
20110232693 A1 Sep 2011 US
Provisional Applications (1)
Number Date Country
61210125 Mar 2009 US
Divisions (1)
Number Date Country
Parent 12579574 Oct 2009 US
Child 13156257 US