Patent Application
20250081579
The present disclosure relates to semiconductor power devices, and in particular to metallizations for power semiconductor devices.
Power semiconductor devices typically have relatively thin top side (or top side) and back side metallizations. This is the result of a number of factors, including metal deposition process capabilities, process time and cost, and stress induced warpage of the wafer. For high current power devices, however, these thin metallization layers introduce limitations to performance and reliability of the product. This is particularly so for wide band gap devices which offer considerably higher potential current densities. These higher densities require advancements in the devices and their associated packages to achieve their full potential.
The presence of thin layers may limit performance and reliability at both the device and package levels. For example, at the device level, thin metal layers may result in high current concentrations, uneven current distribution, localized heating and/or localized thermal stresses. At the package level, thin metal layers may result in limitations in the power interconnection size (wire diameter, ribbon thickness, etc.), limitations in the power interconnection material (softer materials vs. harder materials), a higher risk of device damage during wire/ribbon bonding, localized thermal stresses at the interconnection interface and/or limiting the allowable current (i.e. the device is not fully utilized).
Thicker metallization, particularly on the top side metal layer, may help address these issues on multiple fronts. For example, the use of thicker metallization (particularly top side metallization) may allow buffering the current to a more even distribution, and/or may reduce the localized heating and spreading it away from critical interfaces. Additionally, the use of thicker metallization may help to improve robustness for larger size power interconnections and/or may provide a capability to apply compatible materials for different power interconnection materials.
Creating the thicker metallization on a semiconductor wafer, however, has challenges which limit to what is practical and possible. Wafers are relatively thin at the time of processing, and may encounter multiple high temperature conditions as the devices are formed. Thicker metal layers, particularly if only on one side, can introduce warpage and distortion that are often too high for usage.
A method according to some embodiments includes providing a plurality of semiconductor devices on a semiconductor structure, providing a top side metallization on a first side of the semiconductor structure, wherein the top side metallization comprises a plurality of bond pads on each of the semiconductor devices, and providing a back side metallization on a second side of the semiconductor structure opposite the first side of the semiconductor structure, wherein the back side metallization is not provided on portions of the second side of the semiconductor structure corresponding to dicing streets between the semiconductor devices.
The method may further include singulating the semiconductor structure along the dicing streets.
In some embodiments, singulating the semiconductor structure may include sawing the semiconductor structure along the dicing streets.
In some embodiments, providing the back side metallization may include providing a blanket metallization on the second side of the semiconductor structure and selectively removing metal from portions of the second side of the semiconductor structure corresponding to dicing streets.
In some embodiments, selectively removing metal may include selectively ablating the back side metallization with a laser.
Providing the back side metallization may include selectively depositing metal on the second side of the semiconductor structure other than in portions of the second side of the semiconductor structure corresponding to dicing streets.
In some embodiments, providing the back side metallization may include forming contact pads on back sides of the semiconductor devices, wherein corners of the contact pads are shaped to reduce stress at corners of the contact pads caused by mounting the semiconductor devices.
The corners of the contact pads may be rounded. In some embodiments, corners of one of the contact pads are rounded with a radius that is less than about one half of the length of a shortest side of the one of the contact pads.
In some embodiments, the corners of the one of the contact pads are rounded with a radius that is from about 10% to 50% of the length of the shortest side of the one of the contact pads, and in some embodiments from about 40% to 50% of the length of the shortest side of the one of the contact pads.
In some embodiments, the corners of the contact pads are chamfered, and in some embodiments the corners of the contact pads have polygonal shapes. After shaping of the corners of the contact pads, the contact pads may have no peripheral angles less than 120 degrees.
Shaping the corners of the contact pads is performed by selectively depositing a plurality of metal layers.
The back side metallization may not be provided on edges of the semiconductor devices.
The method may further include selectively removing the back side metallization from portions of the second side of the semiconductor structure other than the portions of the second side of the semiconductor structure corresponding to the dicing streets between the semiconductor devices.
Providing the back side metallization may include depositing a plurality of metal layers on the second side of the semiconductor structure.
Providing the back side metallization may include performing patterned deposition of metal on the second side of the semiconductor structure.
In some embodiments, providing the back side metallization may include performing depositing metal on the second side of the semiconductor structure and selectively etching portions of the deposited metal.
A method according to some embodiments includes providing a plurality of semiconductor devices on a semiconductor structure, providing a top side metallization on a first side of the semiconductor structure, wherein the top side metallization comprises a plurality of bond pads on each of the semiconductor devices, and providing a back side metallization on a second side of the semiconductor structure opposite the first side of the semiconductor structure, wherein portions of the second side of the semiconductor structure are free of the back side metallization.
The method may further include selectively removing the back side metallization from portions of the second side of the semiconductor structure.
Providing the back side metallization may include depositing metal on the second side of the semiconductor structure other than the portions of the second side of the semiconductor structure that are free of the back side metallization.
The portions of the second side of the semiconductor structure that are free of the back side metallization may include edges of the semiconductor structure.
Selectively removing the back side metallization from portions of the second side of the semiconductor structure may include selectively removing the back side metallization from portions of the second side of the semiconductor structure corresponding to dicing streets between the semiconductor devices.
In some embodiments, selectively removing the back side metallization from portions of the second side of the semiconductor structure may include selectively removing the back side metallization from portions of the second side of the semiconductor structure near corners of the semiconductor devices.
In some embodiments, selectively removing the back side metallization from portions of the second side of the semiconductor structure may include selectively removing the back side metallization from portions of the second side of the semiconductor structure to form circular features in the back side metallization near corners of the semiconductor devices.
The method may further include forming a protective overlay on the top side metallization, wherein the protective overlay may include an opening aligned with at least one of the bond pads, wherein the opening has rounded corners.
The protective overlay may include polyimide.
A semiconductor device according to some embodiments includes a semiconductor structure, a top side metallization on a first side of the semiconductor structure, wherein the top side metallization comprises a plurality of bond pads, and a back side metallization on a second side of the semiconductor structure opposite the first side of the semiconductor structure. Edges of the back side metallization are inset from edges of the semiconductor structure.
The back side metallization may include rounded, chamfered or polygonal corners.
The back side metallization may include a first metal layer and a second metal layer on the first metal layer, wherein edges of the first metal layer are inset from edges of the semiconductor structure and edges of the second metal layer are inset from the edges of the first metal layer.
The semiconductor device may further include a protective overlay on the top side metallization, wherein the protective overlay may include an opening aligned with at least one of the bond pads, wherein the opening has rounded corners.
The back side metallization may include raised regions near corners of the back side metallization.
The raised regions comprise linear and/or circular regions of metal.
The back side metallization may include regions of removed material near corners of the back side metallization. The regions of removed regions material comprise linear and/or circular regions where metal has been removed from the back side metallization.
A method according to some embodiments includes providing a plurality of semiconductor devices on a semiconductor structure, providing a top side metallization on a first side of the semiconductor structure, wherein the top side metallization comprises a plurality of bond pads on each of the semiconductor devices, and forming a protective overlay on the top side metallization, wherein the protective overlay comprises an opening aligned with at least one of the bond pads, wherein the opening has rounded corners.
The method may further include providing a back side metallization on a second side of the semiconductor structure opposite the first side of the semiconductor structure, wherein portions of the second side of the semiconductor structure are free of the back side metallization.
The opening in the protective overlayer may be formed by two edges of the opening in the protective overlayer, and the corners of the overlayer may be rounded with a radius that is less than about one half of the length of a shorter of the two edges of the opening.
In some embodiments, the corners of the overlayer are rounded with a radius that is from about 10% to 50% of the length of the shorter of the two edges, and in some embodiments the corners of the overlayer are rounded with a radius that is from about 40% to 50% of the length of the shorter of the two edges.
Wide Band Gap power devices, including devices based on silicon carbide (SiC), gallium nitride (GaN), and the like offer a high level of performance benefits, including high voltage blocking, low on-resistance, high current, fast switching, low switching losses, high junction temperatures, and high thermal conductivity. Ultimately, these characteristics result in a notable increase in potential power density, which is power processed per area or volume.
Achieving this potential, however, requires addressing significant challenges at the package and system level. The higher voltages, currents, and switching speeds manifest into significantly higher physical stresses applied onto smaller and more constrained areas. To fully take advantage of what SiC technology has to offer, several challenges must be addressed both at the device and the package level, including the formation of electrical interconnections from the device top sides to the package substrate or terminals. Other challenges include waste heat removal, including conduction and switching losses from the devices, and effective electrical isolation between high voltage potentials. Wide bandgap power devices should also have the capability to handle high steady state currents, capability to handle high transient current events, mechanical robustness to reliably operate in high stress, high temperature, high vibration environments. Such devices should be compatible with advanced interconnection materials, structures, and techniques, as well as with advanced device attach materials, structures, and techniques.
Power packages contain power semiconductor devices, including metal-oxide semiconductor field effect transistors (MOSFETs), junction field effect transistors (JFETs), insulated gate bipolar transistors (IGBTs), diodes, and the like, arranged into a variety of circuit topologies. A device package serves many functions, including electrical interconnection, electrical isolation, heat transfer, and mechanical structure. The package protects devices from environmental contamination and moisture, and provides external electrical and thermal connection interfaces. The package should also provide compliance with safety standards, such as voltage creepage and clearance distances.
Generally speaking, power packages can be categorized as either a discrete package, housing a single device, or a power module, housing multiple devices. Power modules may place multiple devices in parallel and arrange them into various circuit topologies. As an example, a single switch position package that houses one device would be categorized a discrete, and one that houses multiple devices in parallel (to increase output current) would be considered a power module.
Packages conventionally use, but are not limited to, some combination of the following components, each providing multiple functions. These are summarized in the following table. The terms used in this disclosure, unless otherwise indicated, follow the definitions outlined in Table 1 below.
Some typical design requirements for power device packages include high power density (small package size), high current, high voltage, high temperature operation, low thermal resistance, low stray inductance, fast and clean switching, high efficiency through low on-resistance, high efficiency through high speed switching, thoughtful external terminal layout for effective interconnection, compliance with creepage and clearance standards, moisture sensitivity level (MSL) compliance, and low cost.
A power semiconductor device is typically vertical, meaning power flows from top the back side to the top side of the chip (or vice versa). While there are many types of power devices where this technique applies, a MOSFET will be used for the purposes of explanation and illustration.
A power MOSFET is a three terminal device: (1) gate, (2) source, and (3) drain. Often an additional kelvin connection to the source terminal is made to optimize switching performance to isolate the power and signal loops. The gate and source are located on what will be referred to as the device top side, while the drain is located on the device back side. The high current path flows from the drain to source or source to drain, through the area of the device. An example MOSFET device is depicted in
Referring to
The top side and back side metallizations that form the source pads 16, the gate pad 18 and the drain pad 14 generally include stack of metals to provide a variety of functions, such as ohmic contact, diffusion barrier, seed layers for plating or adhesion, and a capping bonding layer. The top side bonding layer is generally the thickest and is designed to be metallurgically compatible with the desired top side interconnection method. For example, the top side bonding layer may be aluminum to be most compatible with aluminum wire bonding or copper to be compatible with copper wire bonding. The back side metallization is also a stack of metals serving similar functions. Back side attaches tend to be a soldered, brazed, or sintered, rather than connected to wire bonds. The thickness of each layer is generally selected based on what is practical and cost effective to fabricate, what operating conditions are expected, and what performance requirements must be met.
While a power semiconductor device operates as a single device, the physical chip layout is a large array of paralleled device ‘cells’ interconnected through the top side metallization and other functional layers. This is illustrated in
Note that there are many more features and functional layers than depicted in
In many cases, only a portion of the source pad 16 can be used for interconnection through wire bonds or ribbons. Hence, current must spread from these sites out towards the device cells 26. To effectively obtain the most performance out of the device 10, each of these device cells 26 should be fully utilized by carrying as much current as possible. Accordingly, distributing the current from the interconnection sites to each and every cell 26 is important for full device utilization. Distributing current equally among the cells also helps to spread heat evenly across the device.
Using thicker metal may reduce the sheet resistance of the top side metallization 22, and may provide more cross sectional area through which current can readily spread. Increasing the thickness of the top side metallization layer 22 may allow for more cells to access a low resistance, efficient path to the input and output sites for current flow. This buffering effect may reduce high current concentrations and/or may reduce localized heating at the bonding interfaces.
With a thin metallization 22A, there is limited room to laterally spread current and the resulting heat at the interface. These localized high current and heat densities can act to stress and weaken the interface. A thicker metallization 22B helps to buffer the current and heat to better distribute the energy away from the interfaces and evenly towards the device cells 26.
The application of a thicker top side metal may also improve device robustness for more aggressive interconnection methods. For example, copper wire is substantially harder than aluminum, and could cause damage to the sensitive device during the wire bonding process. Thicker metals can buffer out the energy applied to form the metallurgical bonds, and a ‘cushioning’ effect adding resilience and wider process windows. Thus, it may be preferable for the thicker top side metal 22A, 22B to improve the performance and bondability of copper wires. Moreover, due to the high conductivity of copper, the use of copper in the top side metal 22A, 22B can enable the use of fewer wire bonds, or may allow higher currents for a given number of wire bonds. The use of thick top side metal may also accommodate larger wire bond footprints, which can allow for more current.
While there are numerous benefits to thicker metallization layers, there are also many processing challenges. For example, there is a large coefficient of thermal expansion (CTE) imbalance between the semiconductor wafer and the metal layers. As the wafer experiences exposures to high temperatures during processing, the metal and semiconductor expand and contract at different rates, creating thermal stress. These thermal stresses can manifest as warpage of the wafer once cooled.
Warpage is a major problem which may reduce yield or render the wafer useless for further processing. Various types of warpage of wafers 30 are illustrated in
To address the issue of wafer warpage while delivering the benefits of thick metallization, some embodiments apply thick metal selectively using multiple masked deposition processes. That is, instead of applying thick metal on all conductive surfaces, the thick metal is applied selectively only where it is needed. These localized thick plateaus of metal provide buffering and robustness but are small enough that the metal loading is greatly reduced, and the expansion stresses are lessened. This approach is shown on an example power device in
Referring to
Referring still to
The thick metal layer 32A is formed where needed for a desired performance, interconnection scheme, and interconnection material. It may be deposited through similar processes as the thin metal layer 32B. A mask or similar may be used to only apply the metal where desired to form the bond pads 35. The bond pads 35 may also be formed by plating a thick layer of metal over the thin metal layer 32B and etching or selectively depositing the plated metal to form the bond pads 35. Plating is a practical and cost effective to form relatively thick layers.
The thin metal layer 32B may have a thickness of about 1 micron to 5 microns, while the thick metal layer 32A may have a thickness of about 20 microns or more. In some embodiments, the thick metal layer 32A may have a thickness that is at least 1.5 times the thickness of the thin metal layer. In further embodiments, the thick metal layer 32A may have a thickness that is at least 2 times the thickness of the thin metal layer. In still further embodiments, the thick metal layer 32A may have a thickness that is at least 5 times the thickness of the thin metal layer. In still further embodiments, the thick metal layer 32A may have a thickness that is at least 10 times the thickness of the thin metal layer. In still further embodiments, the thick metal layer 32A may have a thickness that is at least 20 times the thickness of the thin metal layer.
By forming a thin layer of metal on the semiconductor die 20, the design rule for manufacturing the semiconductor die 20 may be tightened, which means that it maybe possible to form smaller or more dense features in the semiconductor die 20 than would be possible if only a single thick metal stack were formed thereon. It will be appreciated that the design rule for a semiconductor die determines how closely or densely features can be formed on the die. When the initial metal layer on the die is thick, a larger design rule is required due to lateral variations in the thick metal layer to discourage the initial metal layer from undesirably contacting unintended features on the die. According to some embodiments, by forming an initial metal layer as a thin layer 32B having a thickness of less than 5 microns, the design rule for the semiconductor die may be reduced.
As seen in
Referring to
The capping layer 48 may be a metal that is metallurgically compatible with the desired material for the thick metal layer 32A, which typically includes copper but may include aluminum. For example, the capping layer 48 may include copper, aluminum copper, aluminum, or any other suitable metal.
The thick metal layer 32A may include a material with a high mechanical strength. Generally, copper may be desirable to use for the thick metal layer 32A, due to its mechanical strength and/or hardness, to support the formation of copper wire bonds to the bond pads 35. The force of forming a wire bond to the bond pad 35 may displace softer metals, such as aluminum, pushing it to undesired locations on the die.
Copper is also desirable for use as the thick metal layer 32A due to its high electrical and thermal conductivity. However, in some cases other metals may be desirable. The thick metal layer 32A may be left bare, or in some cases it may be further plated with a more oxidation resistant material such as nickel, palladium, gold, etc.
The intermediate layer 44 may include a diffusion barrier layer which serves the purpose of obstructing inter-diffusion of soluble metals. As an example, if the capping layer 48 contains copper, then without a diffusion barrier, copper may spread into and contaminate the underlying metals and also likely diffuse into the underlying insulating layers, interconnects, gate oxides, and substrate of the die 20. This ultimately may inhibit or destroy the function of the device 100A. Adding an insoluble diffusion barrier layer of, for example, TiN may obstruct this from occurring. The intermediate layer may include other layers, such as adhesion layers, seed layers, etc.
Even if a diffusion barrier is used, however, diffusion may still be possible at the edges of the interface. That is, metal can diffuse around the edges where there is no diffusion barrier in the vertical direction. This is illustrated in
Moreover, the bond pad 35 of the thick metal layer 32A is inset such that the edge 49 diffusion barrier layer 44 extends past the edge 39 of the bond pad 35 to further reduce the possibility of edge diffusion from the bond pad 35.
There are many implementations of top side metallization using the selective metal approach according to various embodiments of the inventive concepts. The specific approach could be tailored to accommodate a number of factors, including one or more of device size, device aspect ratio, device shape, pad size, interconnection method, interconnection material, bonding direction, bonding pattern, package features and/or product application.
Example top side features are described in the following for a reference device. These may be used by themselves or in combination with back side features depending on many of the factors listed above. Interconnection in the examples includes signal and power bonds. Individual interconnection bonds for each thick pad are illustrated. However, the pads may be stitch bonded together as well, which is not pictured but is also possible with this method.
Note that a specific implementation is not limited to these examples, and ultimately is driven by product and application factors. Also note that there is an unused bond pad in the examples (on the upper left side) that could be used as an alternative site for source kelvin bonding. It could also be used as a bonding site for on-chip sensors like temperature, current, and the like. Additional bonding pads would be configured to match the specific needs of that particular device.
In some cases, as much of the device top side area as possible is used for bonding.
In some cases, the pads could be staggered or not in-line. This could be used to match a specific bonding pattern, or to specifically address a warpage or stress issue, such as removing thick metal from the corners.
Another staggered pattern is depicted in
In many package types, the gate wire bonds 64 (i.e., those formed to the gate contact and that carry a signal) are formed in one direction, and the source wire bonds 55 (i.e., those formed to a source contact and that carry power) are formed in another direction. Often, they are orthogonal to each other. In other cases, they are bonded off in arbitrary angles. The size and location of the thick square or rectangular pads can be arranged to accommodate these bond angles. An example pattern for orthogonal bonding for a device 100F is illustrated in
Staggered angled or orthogonal patterns may also find use as shown in
The bond pads 35 may typically be sized to match the bond foot at the desired bonding angle.
In some embodiments, the pads bond pads 35 may have a shape that is non-rectangular. For example, the bond pads 35 may be circular in shape so that bonding at any angle would be possible, such as illustrated in the device 100H
Selective metallization is also highly compatible with ribbon bonding. With ribbons, a rectangular cross section is used for the interconnect instead of a circular wire. This significantly enhances the ampacity and ruggedness of the bond. Examples for in-line and orthogonal bonding are shown in
Note that a circular cross section may be used for the gate signal bonds to the gate pads 18, as pictured, since they are not carrying high currents. They may also be square or rectangular in cross section, however, in some applications where the robustness of that shape of wire is needed.
Top side enhancements are not limited to wire and ribbon interconnects. For example, using a three-dimensional structure clip attach structure may also improve the reliability and ruggedness of a metallurgical bond (solder, sinter, etc.) or an adhesive bond (epoxy, etc.). Here, the three-dimensional structure acts as an anchoring feature. The three-dimensional structure adds significant strength to the attach in comparison to two flat surfaces bonded together. An example surface intended to provide structure to enhance soldering is shown in
The specific implementation of an enhancing surface for a clip attach will depend on the size, layout, and aspect ratio of the device and the design of the clip. A waffled pattern, as shown in
A clip interconnect 61 may also be used for a flip chip or double-sided package. In this application, the thick metal would act as a physical spacer to provide sufficient room for encapsulation or underfill to cover critical voltage blocking regions such as the edge termination.
In particular,
There are many implementations of back side metallization using a selective metal approach according to some embodiments. The specific approach could be tailored to accommodate a number of factors, including one or more of device size, device aspect ratio, device shape, pad size, interconnection method, interconnection material, bonding direction, bonding pattern, package features and/or product application.
Example back side features are described in the following for a reference device. These may be used by themselves or in combination with top side features depending on many of the factors listed above. Note that specific implementation is not limited to these examples, and ultimately is driven by product and application factors.
Thicker metal on the device back side can provide benefits such as thermal buffering, added mechanical robustness, and compatibility with some attach methods (diffusion bonding, for example). Similar to the top side metallization, warpage issues limit what is practical. A selective approach is an attractive solution, as the metal plane can be broken up such that the copper fields have room to expand without creating warpage in the wafer.
In some embodiments, the thick portion 44A and the thin portion 34B of the metal layer 34 are provided by separate layers that are formed from different metals. For example, the thick portion 34B may be copper, while the thin portion may be aluminum copper.
Additionally, providing thicker metal on both sides of the wafer can manifest in a stress balance such that the warpage induced by the patterns could ‘equal out’, resulting in a net flattening effect on the final distorted shape.
The selective pattern could also be used as a means to enhance the reliability of the device attach. For example, thin regions in the corner could be used to increase the surface area of a solder bond, as it is known that device corners may be a weak spot at which metal delamination may occur. As shown in
Recessed features could also be used as a manner of bond line control. In this case, pressure during the attach process could ‘flatten out’ the bond line by pressing the thick regions directly against the power substrate.
Thin corner and edge features add robustness in the attach layers where stress is the highest, while leaving the central area thick for optimal heat spreading/thermal performance. An arrayed approach could get the most rugged attach at the tradeoff of reduced thermals.
Thin circular features could potentially be of varying diameter. In this implementation, the diameter of the feature and the associated strengthening/anchoring geometry could vary based on the stress pattern of the device. For example, smaller diameter circles in the middle and larger diameter circles in the corners.
Linear features could also be beneficial, particular on the perimeter.
Depending on process and method, edge linear recessed features may have challenges in wafer dicing or device segmentation. In this case, the triangular recessed features 75 could be inset inside of the corners of the thick metal region 51 as shown in
Many of the features described above can be used in combination. For example, the recessed circular features 43 shown in
As shown in
Moreover, in any of the described embodiments, a single device may include one or more recessed features 50 that extend completely or partially through a given layer 54, 54A, 54B and one or more other recessed features 50 that do not extend completely or partially through the given layer 54, 54A, 54B.
Some further embodiments described herein provide various techniques and/or geometries for forming top side and back side metallizations for semiconductor devices. Some embodiments described herein may reduce damage in the back side metallization during wafer singulation processes (sawing, dicing, laser scoring, and the like).
Moreover, some embodiments described herein may reduce imperfections in the back side metal edge quality (edge tags, peeling, etc.) due to metal tearing during the wafer singulation process.
Some embodiments described herein may reduce stress concentrations at metallization corners through edge transition features, and/or smooth out stress gradients to distribute the peak stress regions across a larger area instead of a single point.
Some embodiments described herein may reduce damage in the back side metallization during wafer singulation processes (sawing, dicing, laser scoring, and the like).
In some embodiments, an offset region on the back side attach layer may act as a mechanical anchor to enhance adhesion of an encapsulation or mold compound.
Semiconductor devices are fabricated in the format of a wafer in which many chips are manufactured on a single semiconductor substrate. Numerous manufacturing processes are used in the fabrication of semiconductor devices, including crystal growth, epitaxial growth, deposition of various materials (metals, glasses, ceramics, dielectrics, etc.), patterning using various methods, etching or material removal using various methods, singulation, and the like.
The devices are separated from the wafer in a process known as singulation. Generally, this involves a mechanical sawing or dicing operation or a lasering process in which a laser ablates the material away. to separate the devices. Lasering may involve a variety of methods, including full depth, partial depth and perforation, as described below.
In a full depth laser singulation process, the laser scribes completely through the wafer surface in lines, often in a series of passes or layers. Chips are fully singulated at this stage, and further separated through a separate process such as tape expansion.
In a partial depth laser singulation process, the laser scribes partially through the wafer surface in lines, often in a series of passes or layers. Chips are not fully singulated at this stage and are ‘snapped’ apart through a separate process such as tape expansion, mandrel bending, etc.
In a perforation laser scribing process, the laser scribes completely or partially through the wafer surface in patterns, such as a series of dots, often in a series of passes or layers. Chips are not fully singulated at this stage and are ‘snapped’ apart through a separate process such as tape expansion, mandrel bending, etc.
The physical material that is removed as a result of singulation is generally referred to as ‘kerf’. The amount, or width, of kerf differs depending on the singulation process. The path of the kerf is generally referred to as the ‘street’. In the case of a wafer, the streets are typically arranged as a linear grid in both directions, but in principle could follow any arbitrary geometric pattern. Material in the kerf is sacrificial and lost during the singulation processes. Accordingly, processes which reduce the amount of kerf needed, such as laser dicing, may increase the amount of usable material for devices on the wafer.
Generally, on the wafer top side, the kerf region is left blank, (i.e., is not covered with a metal), with a tolerance, such that minimal damage to the sensitive semiconductor structure or edge termination may be introduced during singulation. However, the wafer back side, which for power devices is fully metallized, typically has no such removal for kerf. The metal region is cut through in the same process as the substrate. That is, dicing streets are not conventionally formed on the back side of the wafer, and the back side metallization is cut through in the same process as the substrate. This is illustrated for a generic wafer and generic array of devices in
Referring to
Singulation by sawing is illustrated in
For any singulation process, there is a chance that the back side metal is damaged during the operation. Damage may manifest in a reduction of metal adhesion, flakes or missing metal in the chip area, flakes or tags that extend past the edge of the chip, cracks, and the like. This damage could occur during sawing or dicing due to dullness or vibration in the cutting tool or similar process related defect. It could occur during lasering due to improper ablation of the metal region or excessive tearing during the final separation process (tape expansion or similar). If the metal adhesion to the device is weak or otherwise flawed, that weakness may become worse after the singulation process.
To this end, if the metal was not present in the kerf region, this damage could be reduced or prevented entirely. In turn, the shape and edge quality of the metal would be determined not by the singulation process, but as an intentional pattern. This general concept is illustrated in
In particular, as shown in
The singulation process for the wafer 200 shown in
The back side dicing streets 232 can be defined by an additive manufacturing process or a subtractive manufacturing process. In an additive manufacturing process, the back side metallization is deposited in such a manner that no metal is deposited in the dicing streets. For example, a deposition mask may be selectively formed on the back side of the wafer 200 to cover the dicing streets, and the back side metal may be deposited on portions of the back side 220 of the wafer 200 that are not covered by the deposition mask. In a subtractive manufacturing process, the entire back side 220 of the wafer 200 may be covered with a metal and portions of the metal corresponding to the dicing street may be selectively removed. For example, an etch mask may be formed to cover portions of the back side 220 of the wafer 200 corresponding to the back side metal contacts 258, and portions of the metal layer other than those covered by the etch masked may be etched from the wafer 200. Additive and subtractive processes for forming metal layers on semiconductor structures are well known in the art.
In addition to improving the quality and adhesion of the back side metal, other benefits can be introduced using the concept of selectively metallization the back side. Here, stress concentrations can be reduced and the stress pattern can be smoothed out by shaping the pads accordingly.
In the case of a power module, most of the attaches are conductive and metallic. Common attach techniques include soldering, brazing, and sintering. For each of these methods, the attach layer will generally conform to the shape of the pad to which it is attaching to.
Solder/Braze—In a solder/brazing process, molten material will ‘wet’ the metal surface and self-conform to its shape through capillary action. Areas where the solder are not able to wet (such as a bare semiconductor surface) the solder will pull away from.
Sinter—In a sinter process, deposited metal is heated to cause it to bond to the underlying surface. The material will only sinter to and form a bond with a compatible metal surface. Areas that are not compatible will self-sinter but not form a bond to the surface, resulting in a weak region and a crack propagation site. Accordingly, the material is applied such that it matches the surface it is being bonded to.
For the purposes of this description, any metallurgical attach method can find benefit, with the general assumption being the shape of the attach will follow the shape of the pad.
Accordingly, the shape of the pad on the device can be used to control the shape of the attach, which is fundamental in controlling the edge transitions to buffer and reduce stresses. By contouring edge transitions to better distribute stresses and reduce highly local concentrations, product reliability can be improved, and lifetime can be extended.
As an example, brief reference is made to
A finite element analysis (FEA) simulation is used to compare the stress gradient at the corners for a conventional full backside coverage vs. an approach with an inset of the metallization with rounded corners for the generic example shown above. The simulation assumes the assembly is stress free at room temperature, and then reports the strains and stresses at an elevated temperature.
The resulting stress gradient under the same color scale is shown in
Notably, failure in a device attach very often manifests as a crack or delamination in the corner. By implementing an edge transition, such as a rounded corner, in the above example back side metallization of the device, the reliability and/or lifetime of that attach can be significantly improved.
Conventionally, the back side metallization extends across the device's entire back surface. When the devices are singulated from a wafer, they are diced, sawn, laser scored, or otherwise cut through. If, however, the back side metallization was patterned, then the possibility for shaping the pads to reduce stress is achieved.
The metallization coverage may be configured in various embodiments with full coverage or inset coverage as described below.
The metallization coverage may be configured in various embodiments with full coverage or inset coverage as described below. In particular,
For full coverage, the backside (e.g., device 225), the back side metallization covers the entire device back side and is cut through directly during wafer singulation.
For inset coverage, (e.g., device 250), the back side metallization is inset such that it is not cut through during wafer singulation. This would be useful in cases there the metal adhesion to the device back side is not strong enough to withstand the singulation cutting processes, or alternatively, if the singulation cutting process is too damaging to the back side metallization. An example of this would be laser dicing in which the laser process damages the adhesion of the metal or creates rough edges, such as metal tags, left over after singulation.
The two approaches with rounded corners are compared to a generic power device
Patterning may be implemented through a subtractive technique, an additive technique with a single layer, an additive technique with a plurality of layers, or a combination of these techniques.
In a subtractive, the full back side metallization is applied. The back side metallization is selectively removed through etching, laser scribing, and the like.
In an additive, single layer technique, a mask is used to apply back side metallization selectively and not apply metallization in regions that are ‘masked off’.
In an additive, multiple layer technique, a first layer of the back side metallization is applied, either as full coverage or selectively. Then, additional metallization is applied selectively to build a three-dimensional structure. This achieves both stress reduction at the corners as well as bond enhancement through mechanical anchoring and increased bonding contact area.
The three approaches are illustrated in
In a single metal process, a single layer of metal is selectively deposited on a back side of the semiconductor structure other than at the edges (i.e., in dicing streets) and at the corners of the device to form a back side contact 258 on the back side of the device 250.
In a dual metal process, a first layer of metal is selectively deposited on a back side of the semiconductor structure other than at the edges (i.e., in dicing streets) and at the corners of the device 250 (selective deposition 1). A second layer of metal is then selectively deposited on the first layer of metal, again leaving the edges and corners of the substrate uncovered (selective deposition 2). The first and second layers of metal together form a single metal contact layer on the device 250.
Note that for each of these cases, there may be a number of associated processes (mask deposition, mask patterning, mask liftoff, etc.) that are not outlined, for simplicity. Note that in some cases, the scale of the features is exaggerated to show detail. Specific embodiments may have more or less rounding or offsets depending on the particular device and package structure. Note that while rounded corners are shown for simplicity, other embodiments are presented in a later section.
Patterning may also occur as a combination of techniques. For example, additive deposition followed by subtractive patterning. Specific implementation depends on the device design, wafer fabrication processes, and the structure being formed on the device.
A secondary benefit of inset approach is found in the anchoring effect the structured surface could have on surrounding encapsulation materials or mold compounds found in conventional power modules. This ‘undercut’ region provides geometry for the adhesive materials to grip to, adding strength to their attach and acting to inhibit delamination from the surfaces as they are stressed in service.
This is illustrated in
Here, the die attach 318 follows the inset metal pattern, creating a small region around the perimeter where there is a region where the encapsulation or mold compound can fill in underneath the device. This additional structure creates an anchoring or locking effect on the material, enhancing its bond strength. Note that layer thicknesses in the figure are used to show the detail of this approach and may be scaled differently in many cases.
Conventionally, top side metallization covers multiple terminals on the device (gate and source, in the case of a MOSFET) forming ‘pads’ of metal to bond to. The metallization covers all active areas as well as signal bonding regions, gate runners, sensors, etc. This metallization as well as the edge terminations around the perimeter of the device are covered in a protective overlay isolating material with openings to allow for electrical interconnection to the pads (wire bonds, ribbon, clips, lead frames, etc.).
In cases where a solder, sinter, or similar metallurgical attach is used on the device top side, then a similar motivation exists to reduce stress concentrations through corner transitions. Top side metallurgical attaches are common in packages where the device top sides are attached to a clip, lead frame, or power substrate. In some cases, only the power connection to the source pad is made, while the signal pads are wire bonded. In other cases, all pads are attached to.
Consequently, corner transitions in the metallization instilling a matching corner transition in the top side metallurgical attach achieves similar reliability and lifetime benefits as was demonstrated in the back side metallurgical attach.
While creating a corner transition on the metal itself is not desired, as it would limit the active area of the device, the openings of the overlay metal can indeed be rounded for a similar effect as the back side metallization. The additional overlay material in the corners or edge transitions conformally shapes the metallurgical attach during processing, as described previously, such that the transition is naturally formed. Two example approaches of this technique compared to a traditional device are illustrated in
Top side surface enhancements can be achieved, for example, through an additive overlay technique or an additive multiple layer technique.
In an additive overlay technique, the protective overlay material is masked and patterned to achieve the desired corner transition feature. Effectively, this changes the ‘shape’ of the exposed metal pad without sacrificing active device area.
In an additive, multiple layer technique, an additional metallization could be applied selectively to build a three-dimensional structure. This may achieve both stress reduction at the corners as well as bond enhancement through mechanical anchoring and increased bonding contact area.
These are illustrated in
In some embodiments, the corners of a contact pad may be rounded with a radius that is related to the size of an edge of the contact pad that forms the corner in question. For example, when a corner of the contact pad is formed by two edges of the contact pad, the corner may be rounded with a radius that is less than about one half of the length of the shorter of the two edges. In some embodiments, the corner may be rounded with a radius that is from about 10% to 50% of the length of the shorter of the two edges. In some embodiments, the corner may be rounded with a radius that is from about 30% to 50% of the length of the shorter of the two edges, and in some embodiments from about 40% to 50% of the length of the shorter of the two edges.
In some embodiments, the corners of the contact pads are rounded with a radius that is less than about one half of the length of the shortest side of the contact pad. In some embodiments, the corner may be rounded with a radius that is from about 10% to 50% of the length of the shortest side of the contact pad. In some embodiments, the corner may be rounded with a radius that is from about 30% to 50% of the length of the shortest side of the contact pad, and in some embodiments from about 40% to 50% of the length of the shortest side of the contact pad.
For example, referring still to
Rather than rounding the metal contacts, in some embodiments, openings in the protective overlayer that expose the underlying contact pads are rounded to reduce stress in the semiconductor device.
For example,
In some embodiments, the corners the opening in the protective overlayer may be rounded with a radius that is related to the size of an edge of the opening in the protective overlayer that forms the corner in question. For example, when a corner of the opening in the protective overlayer is formed by two edges of the opening in the protective overlayer, the corner may be rounded with a radius that is less than about one half of the length of the shorter of the two edges. In some embodiments, the corner may be rounded with a radius that is from about 10% to 50% of the length of the shorter of the two edges. In some embodiments, the corner may be rounded with a radius that is from about 30% to 50% of the length of the shorter of the two edges, and in some embodiments from about 40% to 50% of the length of the shorter of the two edges of the opening in the protective overlayer.
Depending on the fabrication process and particular device design, the order of operations and associated processes (masking, exposure, demasking, etc.) may vary. For example, for a multiple layer approach, the additional metal layers could be applied before or after the overlay deposition.
The previously described examples exhibit rounded corners for simplicity. Full rounded corners are the most basic and effective approach to reduce the corner stress concentration with a smooth, constant radius.
In some cases, other corner transitions may be desired based on the manufacturing processes, stress profile, device aspect ratio, etc. As an example, if the metal is selectively removed using laser ablation, it would be more effective to have a linear chamfered transition vs. rounded in some cases, as some lasers raster in straight lines. Laser scribers could be used to achieve the rounded geometry any many of the more complex designs shown below. Example corner transitions are depicted in
Note that the shapes could be formed with any of the previously described approaches and could be formed on the device top side and/or back side.
If a more rounded shape is needed with linear removal processes such as lasering, a rounded corner could be approximated using polygonal shapes. This approach, shown in
Patterning could find embodiments inside the metal pad also. Here, metal would be removed or deposited such that there are regions within the pad that are metal free or have additional metal thickness. These techniques could be used to improve the adhesion of the metal layer on the device and to prevent delamination when stressed.
Within metallization examples are depicted in
Within metallization examples are depicted in
Multiple layer structures could be added for a variety of functions, including increasing surface area to enhance bonding, creating an anchoring effect to enhance strength, and to act as a means of bond line control of the attach layer. Example of methods to implement this are shown in
The additional metal layers could be placed all over (with an edge offset) (282A), as full or partial ‘rails’ (282B) following the contour, localized features (282C) in the corner of various geometries, and patterned raised features (282D) to enhance the strength all over.
For the above single layer or multiple layer features, they could be implemented locally where the stresses are the highest. Or, alternatively, they could follow the entire perimeter of the device to reduce concentrations across the entire outer edge. The use of local vs. edge following perimeter features 272, 282 on either top side contacts 254 or back side contacts 258, respectively, is illustrated in
While the above-described power semiconductor devices and the other devices described herein are shown as being silicon carbide-based semiconductor devices, it will be appreciated that embodiments of the present inventive concepts are not limited thereto. Instead, the semiconductor devices may comprise any wide bandgap semiconductor that is suitable for use in power semiconductor devices including, for example, gallium nitride-based semiconductor devices, gallium nitride-based semiconductor devices and II-VI compound semiconductor devices.
The inventive concepts have been described above with reference to the accompanying drawings, in which embodiments of the inventive concepts are shown. The inventive concepts may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concepts to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout, except where expressly noted.
It will be understood that although the terms first and second are used herein to describe various regions, layers and/or elements, these regions, layers and/or elements should not be limited by these terms. These terms are only used to distinguish one region, layer or element from another region, layer or element. Thus, a first region, layer or element discussed below could be termed a second region, layer or element, and similarly, a second region, layer or element may be termed a first region, layer or element without departing from the scope of the present inventive concepts.
Relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the drawings. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower” can, therefore, encompass both an orientation of “lower” and “upper,” depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof.
Embodiments of the inventive concepts are described herein with reference to cross-sectional illustrations that are schematic illustrations. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the inventive concepts should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the inventive concepts.
It will be understood that the embodiments disclosed herein can be combined. Thus, features that are pictured and/or described with respect to a first embodiment may likewise be included in a second embodiment, and vice versa.
While the above embodiments are described with reference to particular figures, it is to be understood that some embodiments of the present inventive concepts may include additional and/or intervening layers, structures, or elements, and/or particular layers, structures, or elements may be deleted. Although a few exemplary embodiments of the inventive concepts have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the inventive concepts. Accordingly, all such modifications are intended to be included within the scope of the inventive concepts as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of the present inventive concepts and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The inventive concepts are defined by the following claims, with equivalents of the claims to be included therein.
This application is a continuation-in-part of U.S. patent application Ser. No. 18/612,302, entitled “POWER DEVICES WITH MULTIPLE METAL LAYER THICKNESSES” (Attorney Docket 5308-3412US1), filed on Mar. 21, 2024, and assigned to the same assignee as the present application and is incorporated herein by reference as if set forth in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 18612302 | Mar 2024 | US |
| Child | 18950476 | US |
