Patent Application
20080217294
The present invention relates to a method and system for etching a hafnium containing layer, whereby the hafnium containing layer is treated in a first step and then etched in a second step.
As is known to those in the semiconductor art, the reduction in size of semiconductor devices has been indispensably necessary in order to cause an increase in device performance and a decrease in power consumption. Accordingly, process development and integration issues are key challenges for new gate stack materials and silicide processing, with the imminent replacement of SiO2 and Si-oxynitride (SiNxOy) with high-permittivity dielectric materials (also referred to herein as “high-k” materials), and the use of alternative gate electrode materials to replace doped poly-Si in sub-0.1 μm complementary metal-oxide semiconductor (CMOS) technology.
Dielectric materials featuring a dielectric constant greater than that of SiO2 (k˜3.9) are commonly referred to as high-k materials. In addition, high-k materials may refer to dielectric materials that are deposited onto substrates (e.g., HfO2, ZrO2) rather than grown on the surface of the substrate (e.g., SiO2, SiNxOy). High-k materials may incorporate metallic silicates or oxides (e.g., Ta2O5 (k˜26), TiO2 (k˜80), ZrO2 (k˜25), Al2O3 (k˜9), HfSiO, HfO2 (k˜25)).
Oxides of hafnium, such as HfOx and HfSiOy are being considered and tested to replace SiO2 as the gate dielectric. Although these materials have the high-k values needed to provide a large equivalent oxide thickness, these materials are very refractory and difficult to etch by wet and dry methods. For example, known plasma dry etch techniques have poor selectivity with respect to the underlying substrate, and therefore plasma etching of the high-k layer results in damage such as Si recess damage in the source and drain regions of the substrate beneath the high-k layer. While wet etch techniques using HF solutions, for example, can reduce Si recess damage, such etch processes are isotropic and can therefore undesirably etch or undercut the high-k gate dielectric layer beneath the conductor in the gate stack. Further, it has been found that as-deposited high-k films can be dissolved in dilute HF solutions to facilitate etching, however annealed high-k films such as HfSiO are difficult to etch under the same conditions.
In the accompanying drawings:
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as a particular geometry of the plasma processing system and descriptions of various processes. However, it should be understood that the invention may be practiced in other embodiments that depart from these specific details.
In material processing methodologies, pattern etching includes the application of a thin layer of light-sensitive material, such as photoresist, to an upper surface of a substrate that is subsequently patterned to provide a mask for transferring this pattern to the underlying thin film on a substrate during etching. The term “substrate” is used broadly herein to describe a semiconductor wafer to which photoresist can be applied to process the wafer. Thus, a substrate may be a bare semiconductor wafer, or a previously processed wafer including a SOI layer or a multi-gate transistor body for example. The term “substrate” is used broadly herein to describe a wafer to which photoresist can be applied to process the wafer. Thus, a substrate may be a bare semiconductor wafer, or a previously processed wafer including a SOI layer or a multi-gate transistor body, for example. The patterning of the light-sensitive material generally involves exposure by a radiation source through a reticle (and associated optics) of the light-sensitive material using, for example, a photo-lithography system, followed by the removal of the irradiated regions of the light-sensitive material (as in the case of positive photoresist), or non-irradiated regions (as in the case of negative resist) using a developing solvent. Moreover, this mask layer may include multiple sub-layers.
During pattern etching, an anisotropic plasma etch process is often utilized, wherein plasma is formed from a process gas by coupling electro-magnetic (EM) energy, such as radio frequency (RF) power, to the process gas to heat electrons and cause subsequent ionization and dissociation of the atomic and/or molecular composition of the process gas.
For example, as shown in
According to one embodiment, the pattern etching process for transferring a pattern into high-k dielectric layer 120 includes treating the high-k dielectric layer 120 using a plasma etch process, and then exposing the treated layer to a wet etch process. In one embodiment, the polysilicon and/or metal layer are removed down to the high-k dielectric layer 120, and the high-k dielectric layer 120 is etched by first plasma treating the high-K layer with a HBr gas containing plasma, and then exposing the high-K layer to a wet etch process. In another embodiment where a polysilicon layer is provided on the high-K layer, an anisotropic etch process using a HBr containing plasma is used to etch and over-etch the polysilicon layer 130 during the polysilicon etch process resulting in the altering or treatment of the surface of the high-k dielectric layer 120 prior to etching the high-k dielectric layer with a dilute HF(aq) solution. Thus, the present inventors discovered that a two-step process using HBr plasma treatment followed by wet etch can provide improvements in the speed of the high-k dielectric etching.
An ionizable process gas 42 is introduced via the gas injection system 40 and the process pressure is adjusted. The flow rate of the process gas can be between about 10 sccm and about 5000 sccm, alternately between about 20 sccm and about 1000 sccm, and still alternately between about 50 sccm and about 500 sccm. The chamber pressure can, for example, be between about 1 mTorr and about 200 mTorr, alternately between about 5 mTorr and about 100 mTorr, still alternately between about 10 mTorr and about 50 mTorr. The controller 55 can be used to control the vacuum pumping system 50 and gas injection system 40. Substrate 25 is transferred into process chamber 10 through a slot valve (not shown) and chamber feed-through (not shown) via a (robotic) substrate transfer system where it is received by substrate lift pins (not shown) housed within substrate holder 20 and mechanically translated by devices housed therein. Once the substrate 25 is received from the substrate transfer system, it is lowered to an upper surface of the substrate holder 20.
In an alternate embodiment, the substrate 25 is affixed to the substrate holder 20 via an electrostatic clamp (not shown). Furthermore, the substrate holder 20 further includes a cooling system including a re-circulating coolant flow that receives heat from the substrate holder 20 and transfers heat to a heat exchanger system (not shown), or when heating, transfers heat from the heat exchanger system. Moreover, gas may be delivered to the backside of the substrate to improve the gas-gap thermal conductance between the substrate 25 and the substrate holder 20. Such a system is utilized when temperature control of the substrate is required at elevated or reduced temperatures. For example, temperature control of the substrate may be useful at temperatures in excess of the steady-state temperature achieved due to a balance of the heat flux delivered to the substrate 25 from the plasma and the heat flux removed from substrate 25 by conduction to the substrate holder 20. In other embodiments, heating elements, such as resistive heating elements, or thermoelectric heaters/coolers are included in the substrate holder 20.
The plasma processing system 1 of
With continuing reference to
Vacuum pump system 50 can include a turbo-molecular vacuum pump (TMP) capable of a pumping speed up to 5000 liters per second (and greater), and a gate valve for throttling the chamber pressure. In conventional plasma processing devices utilized for dry plasma etch, a 1000 to 3000 liter per second TMP (in combination with a mechanical pump) is employed. TMPs are useful for low pressure processing, typically less than 50 mTorr. For high pressure processing (i.e. greater than 100 mTorr), a mechanical booster pump and dry roughing pump are used.
A controller 55 includes a microprocessor, a memory, and a digital I/O port capable of generating control voltages sufficient to communicate and activate inputs to the plasma processing system 1 as well as monitor outputs from the plasma processing system 1. Moreover, the controller 55 is coupled to and exchanges information with the RF generator 30, the impedance match network 32, the RF generator 72, the impedance match network 74, the gas injection system 40, plasma monitor system 57, and the vacuum pump system 50. A program stored in the memory is utilized to control the aforementioned components of a plasma processing system 1 according to a stored process recipe. One example of controller 55 is a digital signal processor (DSP); model number TMS320, available from Texas Instruments, Dallas, Tex.
The plasma monitor system 57 can include, for example, an optical emission spectroscopy (OES) system to measure excited particles in the plasma environment and/or a plasma diagnostic system, such as a Langmuir probe, for measuring plasma density. The plasma monitor system 57 can be used with controller 55 to determine the status of the etching process and provide feedback to ensure process compliance. Alternately, plasma monitor system 57 can include a microwave and/or a RF diagnostic system.
It is to be understood that the plasma processing systems depicted in
As noted above, the plasma treated high-k layer is etched in a wet etch process using an HF solution, for example. The wet etch process is typically performed in a separate processing tool from the plasma chamber. The wet etch process may be performed in a single wafer or batch wafer wet bath treatment system. For example, single wafer wet etch can be performed in a CELLESTA™ system, and a batch wafer etch may be performed in an EXPEDIUS™ or EXPEDIUS PLUS™ batch immersion system all of these systems being commercially available from Tokyo Electron Limited.
At 504, a process gas is provided to the process chamber and a plasma is created in the process chamber to expose the hafnium containing high-k layer to the plasma. Embodiments of the current invention can be applied to processing plasmas containing a process gas that includes an inert gas, a reactive gas, or both. The inert gas can contain He, Ne, Ar, Kr, or Xe, or a combination of two or more thereof. The reactive gas can include a HBr/O2/He. In this embodiment, HBr can be provided at a flow rate of about 40-500 sccm, O2 at about 1-20 sccm, and He at about 50-500 sccm. In one embodiment, Ar can be added at a flow rate of about 100-500 sccm. Further, the HBr plasma process can be performed for about 20-120 seconds at a chamber pressure of about 10-150 mT. RF power can be coupled to the plasma at about 0-300 W on the top electrode and about 50-300 W on the bottom electrode.
In one embodiment, step 504 is performed as an overetch after exposing the polysilicon layer to the plasma to dry etch the polysilicon. In this embodiment, the process step 504 is carried out for the desired amount of time to remove the polysilicon layer and to treat the high-k layer using a plasma etch surface treatment.
In 506, the thermally annealed high-k layer is wet-etched using a dilute HF(aq) (Hydrogen Fluoride) solution. Since the high-k layer was treated in step 504, the wet-etching step 506 quickly removes the treated high-k layer. In one embodiment the substrate having the treated high-k layer thereon is immersed in a bath of H2O:HF solution for a time period of about 10-120 seconds. The H2O:HF ration can be from about 100:1 to 400:1.
Although only certain embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention.
