Patent Application
20240213022
The present disclosure relates to a method of forming an epitaxial layer. More specifically, the disclosure relates to a method of forming a phosphorus doped silicon layer epitaxially on a substrate, a field effect transistor obtained thereof and a substrate processing apparatus for forming the phosphorus doped epitaxial silicon layer on the substrate.
With the progress in semiconductor industry, epitaxial growth of layers, particularly at lower process temperatures may become more critical. This may be due to the various novel integration schemes such as, for example, 3D stacking of devices, buried power rail (BPR) integration, formation of source/drain contact layers and high-k/metal gate first integration schemes.
The challenges introduced by low temperature epitaxial film growth may be related to defect formation and epitaxial breakdown of the layer that may result in amorphous material with poor electrical performance. Furthermore, low temperature epitaxy may pose challenges in terms of maintaining selectivity towards dielectric layers and in terms of achieving a high growth rate.
Therefore, there may be a need to provide methods capable of achieving the growth of monocrystalline epitaxial layers at lower process temperatures while overcoming the challenges.
This summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in further detail in the detailed description of example embodiments of the disclosure below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
It may be an object of the present disclosure to provide an improved method for growing epitaxial layers at lower process temperatures.
In a first aspect, the present disclosure relates to a method for epitaxially growing a phosphorus doped silicon layer on a substrate, The method may comprise providing a substrate to a process chamber. The substrate may comprise a first surface. The first surface may be monocrystalline. The method may also comprise exposing the substrate to a silicon precursor and to a phosphorus precursor, thereby epitaxially growing the phosphorus doped silicon layer on the monocrystalline surface. The phosphorus precursor may comprise a phosphorus halide. The exposure of the substrate to the phosphorus precursor may be done during an overlapping period with the exposure to the silicon precursor.
The method according to embodiments of the first aspect of the present disclosure may advantageously lead to the growth of epitaxial layer at lower process temperatures. Particularly, it may be an advantage to grow phosphorus doped silicon epitaxial layers at lower process temperatures. This may particularly be advantageous for process temperatures lower than 600° C. and particularly lower than 500° C.
It may also be an advantage that incorporation of active dopant in the epitaxial layer may be increased. This may further allow for reduction in the resistivity of the epitaxial layer. This may particularly lead to a reduction in contact resistance when the epitaxial layer is forms the source/drain of a field effect transistor.
It may be an advantage that crystallinity of the epitaxial layer may be improved.
It may further be an advantage that selectivity of epitaxial layer growth at low temperature with respect to non-monocrystalline surfaces may be improved. This may be advantageous for process temperatures lower than 600° C. and particularly lower than 500° C.
It may further be an advantage that the phosphorus doped silicon epitaxial layer remains fully crystalline on all crystal facets of a silicon substrate.
It may also be an advantage that high growth rate of the epitaxial layer may be maintained at lower process temperatures, lower than 600° C. and particularly lower than 500° C. This may further provide the advantage of maintaining a high process throughput at lower process temperatures.
It may be an advantage that selective epitaxial growth of phosphorus doped silicon layer may be achieved. It may further be advantageous that selective epitaxial growth of phosphorus doped silicon layer may be achieved at lower process temperatures, lower than 600° C. and particularly lower than 500° C.
In a second aspect, the present disclosure relates to a field effect transistor. The field effect transistor may comprise a source/drain region. The source/drain region may comprise a phosphorus doped silicon layer gown that may be grown according to embodiments of the first aspect of the present disclosure. The field effect transistor may comprise a fin, a nanosheet or a nanowire.
The field effect transistor according to embodiments of the second aspect of the present disclosure may be advantageous in terms of having a layer with a high active dopant concentration in the source/drain regions.
It may thus, provide an advantage of being a transistor with a high performance.
It may further be an advantage that the transistor may allow for a reduced contact resistance.
Furthermore, it may also be an advantage of having a source/drain region with a reduced parasitic resistance thanks to the reduced contact resistance, where the parasitic resistance may include the contact resistance between the metal contact and the source/drain regions of the transistor.
In a third aspect the present disclosure relates to a substrate processing apparatus. The substrate processing apparatus may comprise at least one process chamber and a controller configured to enable the substrate processing apparatus to perform a method according to embodiments of the first aspect of the present disclosure.
The substrate processing apparatus according to embodiments of the third aspect of the present disclosure may allow for epitaxial growth of a phosphorus doped silicon epitaxial layer selectively on a substrate at lower process temperatures.
It may further be an advantage that the substrate processing apparatus may provide for epitaxial growth at lower process temperatures while maintaining a high growth rate, thereby helping to improve process throughput and overall semiconductor manufacturing throughput.
It will be appreciated that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of illustrated embodiments of the present disclosure.
Like reference numbers will be used for like elements in the drawings unless stated otherwise. Reference signs in the claims shall not be understood as limiting the scope.
Although certain embodiments and examples are disclosed below, it will be understood by those in the art that the invention extends beyond the specifically disclosed embodiments and/or uses of the invention and obvious modifications and equivalents thereof. Thus, it is intended that the scope of the invention disclosed should not be limited by the particular disclosed embodiments described below.
As used herein, the term “substrate” may refer to any underlying material or materials, including any underlying material or materials that may be modified, or upon which, a device, a circuit, or a film may be formed. The “substrate” may be continuous or non-continuous; rigid or flexible; solid or porous; and combinations thereof. The substrate may be in any form, such as, a plate, or a workpiece. Substrates in the form of a plate may include wafers in various shapes and sizes. Substrates may be made from semiconductor materials, including, for example, silicon, silicon germanium, silicon oxide, gallium arsenide, gallium nitride and silicon carbide.
A porous substrate may comprise polymers. Examples of workpieces may include medical devices (for example, stents and syringes), jewelry, tooling devices, components for battery manufacturing (for example, anodes, cathodes, or separators) or components of photovoltaic cells, etc.
A continuous substrate may extend beyond the bounds of a process chamber where a deposition process occurs. In some processes, the continuous substrate may move through the process chamber such that the process continues until the end of the substrate is reached. A continuous substrate may be supplied from a continuous substrate feeding system to allow for manufacture and output of the continuous substrate in any appropriate form.
Non-limiting examples of a continuous substrate may include a sheet, a non-woven film, a roll, a foil, a web, a flexible material, a bundle of continuous filaments or fibers (for example, ceramic fibers or polymer fibers). Continuous substrates may also comprise carriers or sheets upon which non-continuous substrates are mounted.
The illustrations presented herein are not meant to be actual views of any particular material, structure, or device, but are merely idealized representations that are used to describe embodiments of the disclosure.
The particular implementations shown and described are illustrative of the invention and its best mode and are not intended to otherwise limit the scope of the aspects and implementations in any way. Indeed, for the sake of brevity, conventional manufacturing, connection, preparation, and other functional aspects of the system may not be described in detail. Furthermore, the connecting lines shown in the various figures are intended to represent exemplary functional relationships and/or physical couplings between the various elements. Many alternative or additional functional relationship or physical connections may be present in the practical system, and/or may be absent in some embodiments.
It is to be understood that the configurations and/or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various acts illustrated may be performed in the sequence illustrated, in other sequences, or omitted in some cases.
The subject matter of the present disclosure includes all novel and nonobvious combinations and sub-combinations of the various processes, systems, and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof.
It is to be noticed that the term “comprising”, as used herein, should not be interpreted as being restricted to the means listed thereafter. It does not exclude other elements or steps. It is thus, to be interpreted as specifying the presence of the stated features, steps or components as referred to. However, it does not prevent one or more other steps, components, or features, or groups thereof from being present or being added.
It is to be noticed that the term “comprise substantially” used in the claims refers that further components than those specifically mentioned can, but not necessarily have to, be present, namely those not materially affecting the essential characteristics of the material, compound, or composition referred to.
Reference throughout the specification to “embodiments” or “one embodiment” or “an embodiment” means that a particular structure, feature step described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, phrases appearing such as “in an embodiment” or “in one embodiment” in different places throughout the specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics maybe combined in any suitable manner, as would be apparent to one of the ordinary skill in the art from the disclosure, in one or more embodiments.
Reference throughout the specification to “some embodiments” means that a particular structure, feature, step described in connection with these embodiments is included in some of the embodiments of the present invention. Thus, phrases appearing such as “in some embodiments” in different places throughout the specification are not necessarily referring to the same collection of embodiments, but may.
Furthermore, the terms first, second, third, and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking, or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other sequences than described or illustrated herein.
The following terms are provided only to help in the understanding of the disclosure.
As used herein and unless provided otherwise, the term “process throughput” may refer to the number substrates processed in a semiconductor processing apparatus in a given period.
As used herein and unless provided otherwise, the term “fully crystalline” may refer to the fact that the thickness of the epitaxial layer maintains its monocrystalline structure throughout its thickness.
The disclosure will now be described by a detailed description of several embodiments of the disclosure. It is clear that other embodiments of the disclosure can be configured according to the knowledge of persons skilled in the art in the absence of departure from the technical teaching of the disclosure. The disclosure is limited only by the terms of the claims included herein.
Described herein is a method (100) for epitaxially growing a phosphorus doped silicon layer on a substrate.
The method (100) may comprise providing (110) a substrate to a process chamber. The substrate may comprise a first surface. The first surface may be monocrystalline.
In some embodiments, the process chamber may be a single process chamber that may be comprised in a semiconductor processing apparatus. In some embodiments, the process chamber may be one of at least two process chambers that may be comprised in a semiconductor processing apparatus. The method according to embodiments of the first aspect is run in a single chamber; however, the same method may be run simultaneously in more than one process chamber of the semiconductor processing apparatus.
The method (100) may also comprise exposing (120) the substrate to a silicon precursor and to a phosphorus precursor. This may allow for growing epitaxially the phosphorus doped silicon layer on the monocrystalline surface. The exposure of the substrate to the phosphorus precursor may be done during an overlapping period with the exposure to the silicon precursor. The phosphorus precursor may comprise a phosphorus halide.
The disclosed method according to embodiments of the first aspect of the disclosure may allow for improving crystallinity of the epitaxial phosphorus doped silicon layer formed. Furthermore, it may provide the advantage of facilitating the epitaxial phosphorus doped silicon layer growth at a lower process temperature.
In embodiments, the monocrystalline surface may comprise a monocrystalline silicon surface.
In embodiments, the monocrystalline silicon surface may comprise at least one of a first monocrystalline silicon surface and a second monocrystalline silicon surface. The second monocrystalline silicon surface may be different than the first monocrystalline surface. This may enable the growth of the phosphorus doped epitaxial silicon layer on monocrystalline silicon surfaces having either of the two monocrystalline silicon surface. It may also enable growing the phosphorus doped epitaxial silicon layer independent of the crystal orientation of the silicon surface when the monocrystalline silicon surface comprises both of the first and the second monocrystalline silicon surface. This may provide the advantage of growing the phosphorus doped epitaxial silicon layer continuously on the silicon surface that may comprise silicon surfaces having different crystal orientations. In semiconductor manufacturing, this may prove to be advantageous when growing such as, for example, source/drain regions of field effect transistors (FETs) comprising fins, nanosheets, nanowires, such as for example in fin-type field effect transistor (FinFET), complementary field effect transistor (CFET), gate-all-around field effect transistor (GAA-FET) or nanosheet FET.
In some embodiments, the first monocrystalline silicon surface may comprise a Si {100} crystal facet and the second monocrystalline silicon surface may comprise a high order silicon crystal facet.
In some embodiments, the first monocrystalline silicon surface may consist of a Si {100} crystal facet and the second monocrystalline silicon surface may consist of a high order silicon crystal facet.
The high order silicon facet may, in some embodiments, be a Si {110} crystal facet or a Si {111} facet.
In embodiments, the exposure of the substrate to the silicon precursor and to the phosphorus precursor may overlap at a value up to 100%. This may infer that a total time of exposure of the substrate to the phosphorus precursor may be at a value of up to 100% overlapping with a total time of exposure of the substrate to the silicon precursor.
In some embodiments, the substrate may be exposed to the phosphorus precursor while it is being exposed to the silicon precursor. Thus, the exposure of the substrate to the phosphorus precursor may be done substantially simultaneously with the exposure to the silicon precursor. In other words, there may be a 100% overlap of the two exposures with each other. Thus, the phosphorus precursor may be co-flown with the silicon precursor into the process chamber.
In embodiments, the silicon precursor may comprise a high order silicon precursor.
In embodiments, high order silicon precursor may be represented by SinH2n+2, where n is equal to at least 2.
In embodiments, the high order silicon precursor may thus, be such as, for example, Si2H6, Si3H8 and Si4H10. High order silicon precursor may provide the advantage of enabling epitaxial film growth at lower process temperatures as disclosed in the present disclosure. Furthermore, high order silicon precursor may also allow for maintaining a high growth rate of the epitaxial layer at lower temperatures as disclosed in the present disclosure. This may thus, be advantageous for not only enabling low temperature epitaxy, but also reduces the compromise from process throughput at lower temperatures.
In some embodiments, the silicon precursor may be a mixture of high order silicon precursor. In other words, more than one high order silicon precursor may be co-flown into the process chamber.
In embodiments, the flow rate of Si2H6 may be in a range of 50 sccm to 700 sccm. In some embodiments, the flow rate of Si2H6 may be in a range of 100 sccm to 600 sccm. In some embodiments, the flow rate of Si2H6 may be in a range of from at least 100 sccm to at most 200 sccm, or from at least 200 sccm to at most 300 sccm, or from at least 300 sccm to at most 400 sccm, or from at least 400 sccm to at most 500 sccm, or from at least 500 sccm to at most 600 sccm.
Si3H8 is in liquid form and the temperature of the vessel holding Si3H8 may vary in a range of 10° C. to 50° C. In some embodiments, the temperature of the vessel may beset to 18° C. The flow rate of Si3H8 may be in a range of 20 mg/min to 300 mg/min. In some embodiments, the flow rate may be in a range of 50 mg/min. to 200 mg/min.
In embodiments, the silicon precursor may comprise a chlorosilane.
The chlorosilane precursor may provide the advantage of enhancing selective growth.
The chlorosilane may, some in embodiments, be monochlorosilane, dichlorosilane, trichlorosilane, tetrachlorosilane, octachlorotrisilane or hexachlorodisilane.
In embodiments, the silicon precursor may be provided to the process chamber in the presence of a carrier gas.
In embodiments, a temperature of the process chamber may be at most 600° C. during the exposure of the substrate to the silicon precursor and to the phosphorus precursor. Facilitating epitaxial layer growth at process temperatures lower than 600° C. may be advantageous in increasing active dopant incorporation in the epitaxial layer. Resistivity of the layer formed may, thus, be reduced thanks to the increased active dopant concentration. This may further be advantageous for enabling novel integration schemes in semiconductor device manufacturing such as for example, 3D integration of devices, buried power rail implementation or source/drain engineering. Particularly for source/drain engineering, lower temperature epitaxy may advantageously lead to a reduction in contact resistivity.
In some embodiments, the process temperature may be measured via a pyrometer. The pyrometer may be suspended in the process chamber above the substrate.
In some embodiments, the process temperature may be measured by using a thermocouple positioned beneath a support, such as for example a susceptor, that supports the substrate in the process chamber during the process. It is to be noted that the substrate temperature measured by the pyrometer suspended above the substrate in the process chamber and that measured using a thermocouple may differ from each other, particularly at low process temperatures, such as for example, lower than 600° C. and particularly lower than 500° C.
In embodiments, the process temperature may be in a range of from at least 350° C. to at most 600° C. This may, particularly, be advantageous when the silicon precursor is a high order silane or a high order chlorosilane.
In some embodiments, the silicon precursor may comprise the high order silane precursor and the chlorosilane. In other words, the chlorosilane may be co-flown with the high order silane. This may be advantageous within the process temperature disclosed in the present disclosure. The chlorosilane may then be chosen from monochlorosilane, dichlorosilane, trichlorosilane or tetrachlorosilane.
It is to be noted that as the process temperature approaches 600° C. or even exceeds 600° C., the silicon precursor may comprise substantially the chlorosilane.
In embodiments, the process pressure may be in a range between 5 Torr to 80 Torr.
In some embodiments, the process pressure may be in a range of from 20 Torr to 60 Torr.
In embodiments, the phosphorus halide may comprise a phosphorus chloride.
In some embodiments, the phosphorus halide may be a phosphorus chloride with a formula PXn, with n being 3 or 5 and X being a halogen.
In some embodiments, the phosphorus halide may be a phosphorus chloride with a formula PmX2m with m being 2 and with X being a halogen.
In some embodiments, the phosphorus chloride may be phosphorus trichloride (PCl3). Phosphorus trichloride may provide the advantage of improving the crystallinity of the epitaxial layer grown. Improvement of crystallinity may particularly be advantageous at lower process temperatures such as, for example, lower than 600° C. and particularly lower than 500° C. Furthermore, it may be an advantage of co-flowing PCl3 together with the silicon precursor that the critical thickness of the layer grown on Si {110} crystal facet may be increased. Increase in critical thickness may enable depositing a thicker epitaxial layer on Si {110} crystal facet before monocrystalline structure starts to loose periodicity. In other words, critical thickness may refer to the thickness beyond which, the monocrystalline epitaxial layer becomes amorphous. This may allow for depositing phosphorus doped silicon epitaxial layer on complex semiconductor device structures comprising fins, nanosheets or nanowires.
PCl3 is in liquid form and the temperature of the vessel holding PCl3 may be at a temperature in arrange of 0° C. to 50° C. Typically, the vessel temperature is between 5° C. to 40° C.
In embodiments, the flow rate of PCl3 may be in a range of 10 sccm to 500 sccm. In some embodiments, the flow rate may be in a range of 20 sccm to 200 sccm.
In embodiments, the substrate may further comprise a second surface. The second surface may be different than the first surface. The phosphorus doped silicon epitaxial layer may thus, be grown epitaxially and selectively on the first surface relative to the second surface. Phosphorus trichloride may thus, provide the advantage of enhancing growth selectivity of the epitaxial layer on the first surface. Furthermore, co-flowing of phosphorus trichloride with the silicon precursor into the process chamber may advantageously allow for improving selectivity at lower process temperatures such as, for example, lower than 600° C. and particularly lower than 500° C.
In some embodiments, the second surface may be different than the first surface such that it may also be a monocrystalline surface, however; with a different composition.
In embodiments, at least one of the first surface and the second surface may comprise a semiconductor material. The semiconductor material may be a Group IV material.
In some embodiments, the second surface may be different than the first surface such that it may be non-monocrystalline. The non-monocrystalline surface may be a polycrystalline surface or an amorphous surface.
In some embodiments, the non-monocrystalline surface may be a dielectric surface. The dielectric surface may comprise an oxide, a nitride, an oxynitride, an oxycarbide or an oxycarbonitride. In some embodiments, the oxide, the nitride, the oxynitride, the oxycarbide or the oxycarbonitride may comprise silicon.
The selectivity of the formation of the phosphorus doped epitaxial silicon layer may change depending on the difference in the chemical behavior of the silicon precursor with respect to the first surface and the second surface. This may lead to a difference in growth rate of the phosphorus doped epitaxial silicon layer as a function of the difference in crystal orientation. Nucleation delay during the growth of the epitaxial layer may play a role, thereby retarding the growth on the second surface. It is thus, to be noted that in some embodiments, there may also be formation of the phosphorus doped epitaxial silicon layer on the second surface. This may be represented by a selectivity value of lower than or equal to 1 with regarding the formation of the phosphorus doped epitaxial silicon layer on the first surface compared to its formation on the second surface.
We now return to
In embodiments, the method (100) may further comprise exposing the substrate to an etching gas (130). This may allow for improving selectivity of phosphorus doped epitaxial silicon layer growth on the first surface relative to the second surface. The exposure of the substrate to the etching gas may remove the phosphorus doped epitaxial silicon layer that may be grown on the second surface. This removal may thus, allow for achieving a selectivity value of higher than one regarding the formation of the phosphorus doped epitaxial silicon layer on the first surface compared to its formation on the second surface.
In some embodiments, the exposure of the substrate to the etching gas (130) may be performed alternatingly and repeatedly with the exposure of the substrate to the silicon precursor and to the phosphorus precursor (120) as schematically represented in
Thus, in some embodiments, exposing the substrate to the etching gas (130) may remove the phosphorus doped epitaxial silicon layer from the non-monocrystalline surface when the second surface is non-monocrystalline. In some embodiments, the exposure of the substrate (130) to the etching gas may remove the phosphorus doped epitaxial silicon layer from a monocrystalline surface when the second surface is monocrystalline with a composition different than that of the first surface.
In embodiments, the etching gas may comprise a halogen. In some embodiments, the etching gas may comprise chlorine gas. In some embodiments, the etching gas may substantially comprise chlorine gas.
In embodiments, the etching gas may be provided to the process chamber in the presence of a carrier gas.
In embodiments, the carrier gas may comprise N2, and noble gases such as for example, Ar, Ne, He, Xe and Kr.
In some embodiments, the carrier gas may substantially comprise N2, Ar, He, or combinations thereof.
In embodiments, the exposure of the substrate to the etching gas (130) may be done while maintaining the process temperature and process pressure used when exposing (120) the substrate to the silicon precursor and to the phosphorus precursor.
In embodiments, the flow rate of the chlorine gas may be in a range of 10 sccm to 200 sccm.
In embodiments, the flow rate of the chlorine gas may be in a range of from at least 10 sccm to at most 20 sccm, or from at least 20 sccm to at most 40 sccm, or from at least 40 sccm to at most 60 sccm, or from at least 60 sccm to at most 80 sccm, or from at least 80 sccm to at most 100 sccm, or from at least 100 sccm to at most 120 sccm, or from at least 120 sccm to at most 140 sccm, or from at least 140 sccm to at most 160 sccm, or from at least 160 sccm to at most 180 sccm, or from at least 180 sccm to at most 200 sccm.
In embodiments, the phosphorus precursor may further comprise phosphine. This may allow for increasing the phosphorus dopant concentration in the phosphorus doped silicon epitaxial layer formed. Increase in dopant concentration may help to reduce the resistivity of the epitaxial layer. This may further be advantageous when the phosphorus doped silicon epitaxial layer is used for source/drain regions of an n-type metal oxide semiconductor device.
In embodiments, the flow rate of phosphine may be in a range of 50 sccm to 900 sccm. In some embodiments, the flow rate may be in a range of 200 sccm to 600 sccm. In some embodiments, it may be in a range from at least 200 sccm to at most 300 sccm, or from at least 300 sccm to at most 400 sccm, or from at least 400 sccm to at most 500 sccm, or from at least 500 sccm to at most 600 sccm.
In embodiments, phosphine may be co-flown with the phosphorus halide. Thus, in some embodiments, phosphine may be co-flown with PCl3.
In an embodiment, the method may comprise exposing the substrate to Si2H6 precursor while co-flowing PCl3 and PH3 thereby, growing epitaxially the phosphorus doped silicon layer. The method may further comprise exposing the substrate to Cl2 gas, being the etching gas, in the presence of N2, being the carrier gas.
Further described herein is a field effect transistor (FET). The field effect transistor may comprise a source/drain region. The source/drain region may comprise a phosphorus doped silicon epitaxial layer that may be grown by the method described herein according to embodiments of the first aspect of the present disclosure. The field effect transistor may comprise a fin, a nanosheet or a nanowire. The fin, the nanosheet or the nanowire may act as the gate of the field effect transistor. Thus, the field effect transistor may be a fin FET, nanosheet FET or a gate-all-around (GAA) FET.
We now return to
Thus, further described herein, is a substrate processing apparatus (200). The substrate processing apparatus (200) may comprise at least one process chamber (230). The apparatus may also comprise a controller (240). The controller (240) may be configured to enable the substrate processing apparatus (200) to perform a method according to embodiments of the first aspect of this disclosure.
The semiconductor processing apparatus may further comprise a silicon precursor storage module (210) and a phosphorus precursor storage module (220). The silicon precursor storage module (210) may comprise a high order silicon precursor. It (210) may further comprise a chlorosilane. The phosphorus precursor storage module (220) may comprise at least one of a phosphorus halide precursor and phosphine.
In embodiments, the high order silicon precursor may be at least one of Si2H6, Si3H8 and Si4H10.
In some embodiments, the silicon precursor may be a mixture of high order silicon precursor. In other words, more than one high order silicon precursor may be co-flown into the process chamber.
In embodiments, the chlorosilane may be monochlorosilane, dichlorosilane, trichlorosilane, tetrachlorosilane, octachlorotrisilane or hexachlorodisilane.
The apparatus (200) may further comprise a heater (not shown in the figure) that may be configured to heat and maintain a process temperature in the process chamber (230). A pressure controller (not shown in the figure) may be further be comprised in the apparatus (200). The pressure controller may be configured to reach to the process pressure in the process chamber (230) and to main the process pressure.
The controller (240) may be operably connected to the silicon precursor storage module (210) and to the phosphorus precursor storage module (220). The controller (240) may be configured to execute instructions that may be stored in a non-transitory computer readable medium.
In some embodiments, the controller may be configured to include a processor for executing instructions that may be stored in the non-transitory computer readable medium.
The semiconductor apparatus (200) may advantageously allow for enabling epitaxial growth of a phosphorus doped silicon epitaxial layer at lower process temperatures, whereby the risk of decrease in process throughput may be reduced.
The embodiments of the present disclosure do not limit the scope of invention as these embodiments are defined by the claims appended herein and their legal equivalents. Any equivalent embodiments are intended to be within the scope of this invention. Modifications of the disclosure that are different from one another, in addition to those disclosed herein, may become apparent to those skilled in the art. Such modifications and the embodiments originating therefrom, are also intended to fall within the scope of the claims appended herein.
This Application claims the benefit of U.S. Provisional Application 63/476,468 filed on Dec. 21, 2022, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63476468 | Dec 2022 | US |
