Patent Application
20240321639
This application claims the priority benefit of French Application for Patent No. 2302754,filed on Mar. 23, 2023, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.
Embodiments and implementations relate to microelectronics and, in particular, dicing in a semiconductor wafer of semiconductor devices including ultra-low dielectric constant (referred to in the art as “ultra low-k”) layers.
Semiconductor devices are typically manufactured from a semiconductor wafer and are separated (commonly referred to as “singulated”) during a cutting step.
Semiconductor devices particularly typically comprise an interconnection network (commonly referred to a Back-End Of Line (BEOL) on a semiconductor part particularly including electronic components such as transistors (also referred to as Front-End Of Line (FEOL).
The interconnection network typically includes metal layers and can advantageously include ultra-low dielectric constant layers.
Usually, “ultra-low dielectric constant dielectric material” refers to dielectrics which have a dielectric constant “k” or “kappa” less than 95% of the dielectric constant value of silicon oxide.
The dicing step, during which the semiconductor devices are singulated, is typically preceded by a step of forming a hard mask for exposing dicing lines on the semiconductor wafer, i.e., the regions of the wafer wherein dicing is to be performed.
The hard mask makes it possible to protect the interconnection network on the rest of the semiconductor wafer from etching. Metal blocks of the semiconductor device are exposed by forming an opening in the hard mask, but have little or no reaction to the etching of the step of singulating the semiconductor devices.
The dicing lines and the opening in the hard mask to expose the metal blocks can be etched simultaneously in the hard mask. However, the etching time to form the dicing lines can be longer than the sufficient time to expose the metal blocks, since layers of the interconnection network are also etched in the dicing lines in addition to the hard mask layer. The etching of the opening, when it is performed at the same time as that forming the dicing lines, can therefore be extended onto the uncovered metal blocks and produce sputtering of the metal contaminating the vacuum chambers wherein the etchings are carried out.
The etchings to form the dicing lines and expose the metal blocks can also be carried out independently. In this case, a thick mask of photosensitive resin is used to delimit the openings exposing metal blocks. Nevertheless, the mask is liable to have a poor adherence on the wafer, and during the steps of removing this temporary mask, delaminations can appear in the dielectric layers of the interconnection network located at the edge of the dicing lines. Furthermore, a step of chemical treatment of the metal blocks typically takes place after removing this temporary mask and is also liable to cause delaminations. These delaminations, in addition to damaging the dielectric layers of the interconnection network, can permit moisture penetration into these layers which can result in a drift of the characteristics and performances of the semiconductor devices. The delamination risk is even more likely when the dielectric layers of the interconnection network are of the “ultra-low dielectric constant” type.
Thus, these is a need to limit the risk of degradation of the ultra-low dielectric constant dielectric constant.
According to an aspect, a method is proposed for dicing a semiconductor wafer including a semiconductor substrate, an interconnection network provided with metal layers and at least one ultra-low dielectric constant dielectric layer, at least one contact region and at least one dicing region, having for example a width less than 100 μm, the method comprising: forming a hard mask wherein the pattern defines the dicing line, wherein forming the hard mask comprises: forming dielectric layers on the wafer in the contact region and in the dicing region; a first etching producing an opening in the dicing region via said layers of the interconnection network; a second etching producing an opening in the contact region uncovering a metal contact of the interconnection network; and cleaning the uncovered surface of the metal contact using a chemical treatment.
The method further comprises depositing a vertical dielectric layer covering the edges of the opening defining the dicing line, before said chemical treatment of cleaning the metal contact.
Thus, it is proposed according to this aspect, to protect the ultra-low dielectric constant dielectric layer(s), which is exposed at the edge of the dicing line of the wafer, particularly during the chemical treatment of cleaning the metal contact. The term “formation of a hard mask” denotes an embodiment in several steps for shaping a mask including a dielectric layer, generally made of silicon nitride, acting as a hard mask per se, but also including one or more passivation layers, generally silicon oxide, for protecting the wafer against corrosion for example. The hard mask thus formed by the method according to this aspect makes it possible to prevent, during the chemical treatment of the metal contact, damage of the ultra-low dielectric constant dielectric layer by delaminations capable of allowing moisture to enter this layer.
According to one implementation, said first etching is performed after said forming the dielectric layers, and through said dielectric layers and said layers of the interconnection network until the semiconductor substrate is uncovered, so as to shape said pattern of the hard mask defining the dicing line.
The first etching is advantageously configured not to produce delaminations in the ultra-low dielectric constant dielectric layers of the interconnection network. In this regard, the etching and masking techniques used to carry out this first etching can be the same techniques as those provided for the formation of the layers of the interconnection network, and particularly for the formation of the ultra-low dielectric constant dielectric layers.
According to one implementation, the first etching comprises forming a specific first temporary mask, the first temporary mask covering the dielectric layers in the contact region and uncovering the dielectric layers in the dicing region, and removing the dielectric layers and said layers of the interconnection network in the dicing region until the semiconductor substrate is uncovered in the pattern of the hard mask.
The formation of the first temporary mask, for example conventionally made of photosensitive lithographic resin, makes it possible to carry out the etching in the dicing region independently of the etching in the contact region. Indeed, the method according to this aspect enables an etching of the hard mask in two steps, making it possible to prevent the metal dispersion phenomenon, without causing damage of the dielectric layers of the interconnection network caused in the opening step uncovering the contact, given that the latter are protected by the vertical dielectric layer.
According to one implementation, depositing the vertical dielectric layer comprises depositing a conforming layer of a material chosen from silicon nitride or silicon oxide on the entire wafer.
The deposition of a conforming layer of silicon nitride or silicon oxide makes it possible to cover the surface of the wafer uniformly, in particular in the dicing region so that a vertical portion of the layer covers the layers of the interconnection network of the dicing region laterally. Silicon nitride, in addition to protecting the ultra-low dielectric constant dielectric layers from the risk of delamination, also offers superior adherence to the temporary mask.
According to one implementation, the second etching comprises: forming a specific second temporary mask covering the dicing region and uncovering the dielectric layers in the contact region, and removing the dielectric layers until a surface of the metal contact is uncovered.
The formation of the second temporary mask, for example conventionally made of photosensitive lithographic resin, makes it possible to carry out the etching in the contact region independently of the etching in the dicing region. The second etching being carried out independently of the first etching according to this aspect, can thus be optimized and configured specifically for the manufacture of the metal contact, without for all that causing damage to the dielectric layers of the interconnection network, given that the latter are protected by the vertical dielectric layer.
According to one implementation, said first etching is performed before said forming the dielectric layers.
Thus, the dielectric layers of the hard mask will have the same structure formed inside the etched part during the first etching step and above the contact.
According to one implementation, the first etching comprises: forming a specific third temporary mask covering the interconnection network in the contact region and uncovering the interconnection network in the dicing region, and removing said layers of the interconnection network in the dicing region until the semiconductor substrate is uncovered in the dicing region.
The formation of the third temporary mask, for example conventionally made of photosensitive lithographic resin, makes it possible to carry out “pre-etching” in the dicing region, independently of the etching in the contact region, removing in advance the layers of the interconnection network in the dicing region, before the formation per se of the opening of the dicing line.
According to one implementation, depositing the vertical dielectric layer is performed during said step of forming the dielectric layers.
Indeed, when said first etching is performed before hand, the formation of the dielectric layers comprises the deposition of the vertical dielectric layer covering the edges of the opening defining the dicing line.
According to one implementation, the second etching simultaneously comprises: removing the dielectric layers in the contact region until said metal contact is uncovered, and removing the dielectric layers in the dicing region until the semiconductor substrate is uncovered, so as to shape said pattern of the hard mask defining the dicing line.
The second etching makes it possible to simultaneously remove the same thickness of dielectric layers in the contact region and in the dicing region in a single step. The second etching can then be completed when the metal contact in the contact region and the substrate in the dicing region are uncovered, without for all that exposing the contact to prolonged etching and thus not causing metal dispersion in the vacuum chambers.
According to one implementation, the second etching comprises forming a fourth temporary mask having an opening in the contact region defining the uncovered region of the metal contact, and forming an opening in the dicing region defining the pattern of the hard mask such that a vertical portion of the dielectric layers covers the interconnection network laterally on an edge of the dicing region, in the pattern of the hard mask.
The dimensions of the opening of the fourth temporary mask in the dicing region (smaller and located inside the location of the opening of the third temporary mask) make it possible to keep, at the end of the removal of the dielectric layers, a vertical portion of dielectric layers protecting the interconnection network in the dicing line.
According to one implementation, the first etching is carried out by a reactive ion type plasma.
Reactive ion type plasma etching (referred to in the art as Reactive Ion Etching (RIE)) is a typical etching method using a chemical reaction between the material to be removed, i.e., that of the interconnection network layers and optionally the dielectric layers, and simultaneously with a firing of ions projected in a specific direction, usually perpendicular to the etched surface. The RIE process makes it possible, in particular, to remove material precisely and with no risk of damage of the neighboring material layers.
According to one implementation, the method further comprises plasma dicing of the semiconductor wafer into semiconductor chip devices singulated from one another, in the dicing line defined by the pattern of the hard mask.
According to another aspect, a semiconductor chip device delimited by an external edge is proposed, including a semiconductor substrate, an interconnection network provided with metal layers and at least one ultra-low dielectric constant dielectric layer, dielectric layers covering the interconnection network and having an opening uncovering a metal contact in a contact region, the interconnection network being covered by a vertical dielectric layer on the external edge of the chip.
According to one embodiment, the vertical dielectric layer is configured to cover the interconnection network on the external edge of the chip along the entire perimeter of the semiconductor device.
According to one embodiment, the vertical dielectric layer comprises a material chosen from silicon nitride or silicon oxide.
According to one embodiment, the vertical dielectric layer comprises a vertical portion of the dielectric layers covering the interconnection network on the external edge of the chip.
According to another aspect, a semiconductor wafer is proposed, capable of being diced into semiconductor chip devices singulated from each other, including a semiconductor substrate, an interconnection network provided with metal layers and at least one ultra-low dielectric constant dielectric layer, at least one contact region and at least one dicing region, the wafer including a hard mask wherein the pattern defines the dicing line, the hard mask comprising: dielectric layers disposed on the wafer in the contact region; an opening in the dicing region defining the dicing line; an opening in the contact region uncovering a metal contact of the interconnection network, the uncovered surface of the metal contact, the wafer furthermore including a vertical dielectric layer covering the edges of the opening defining the dicing line.
Other advantages and features of the invention will appear upon examining the detailed description of non-limiting embodiments and implementations, and from the appended drawings, wherein:
The step 100 comprises obtaining a semiconductor wafer WF including a semiconductor substrate SUB and an interconnection network INTRCX. The interconnection network INTRCX typically comprises at least one ultra-low dielectric constant dielectric layer formed from an “ultra-low dielectric constant dielectric material”, i.e. a material having a dielectric constant “k” or “kappa” less than 95% of the dielectric constant value of the silicon oxide.
Moreover, the semiconductor wafer WF includes several dicing regions SL_REG and several contact regions BOND_REG. The dicing regions SL_REG can have a width less than 100 μm and can be distributed on the wafer so as to form an array of semiconductor chip devices wherein each dicing region has a “row” or a “column” of the array. In particular, the dicing regions SL_REG are the regions of the wafer where the dicing is carried out for singulating the chips from the wafer and the contact regions BOND_REG are regions of the wafer where electric connections can be made, for example with a probe. For simplification purposes, only one dicing region SL_REG and one contact region BOND_REG have been represented in
The interconnection network INTRCX covers the substrate SUB of the wafer WF. In particular, the interconnection network INTRCX covering the substrate SUB in the regions BOND_REG, SR_REG1, SR_REG2 is equipped with metal levels singulated by inter-metal dielectric layers having an ultra-low dielectric constant. The interconnection network INTRCX covering the substrate SUB in the dicing region SL_REG comprises at least one ultra-low dielectric constant dielectric layer and is free from metal layers.
The semiconductor wafer WF also comprises a metal contact PAD located above the interconnection network INTRCX in the contact region BOND_REG.
For example, the material of the dielectric layers D1 and D3 is silicon oxide (SiO2) and the material of the dielectric layer D2 is silicon nitride (SiN). The dielectric layers D1, D2 and D3 have a thickness Ed together.
The first etching step 102 comprises more specifically a formation of a first temporary mask RES1 and a removal of the dielectric layers D1, D2, D3 and the layers of the interconnection network INTRCX in the dicing region SL_REG.
The temporary mask RES1, which is typically made of photosensitive resin, covers the dielectric layers D1, D2, D3 in the contact region BOND_REG and uncovers the dielectric layers D1, D2, D3 in the dicing region SL_REG.
The dielectric layers D1, D2, D3 and the layers of the interconnection network INTRCX are then removed until the semiconductor substrate SUB is uncovered. Advantageously, the removal of these layers is carried out by reactive ion etching.
Reactive ion etching (RIE) is an etching method, known to a person skilled in the art, making it possible to remove material precisely and with no risk of damage of the neighboring material layers. In other words, this etching method particularly makes it possible to remove the layers of the interconnection network INTRCX without any risk of forming delaminations in the layers of the interconnection network INTRCX located on the edges of the opening in the dicing region SL_REG.
Indeed, the etching of the layers of the interconnection network INTRCX of the step 102 can, for example, be identical or set in the same way as the etchings made in the ultra-low dielectric constant inter-metal dielectric regions, during the manufacture of said interconnection network.
Moreover, plasma etching has the advantage of forming a narrower dicing line than a dicing line that would have been produced indirectly by prior laser grooving.
The hard mask HM thus has a pattern resulting from the first etching step 102 and defining the dicing line in the dicing region SL_REG.
Alternatively, the step 103 is a step of depositing a conforming layer of silicon nitride on the entire semiconductor wafer WF.
The additional layer of silicon nitride or silicon oxide therefore makes it possible to protect an external edge FL of the layers of the interconnection network INTRCX located on the edges of the dicing line.
The second etching step 104 comprises a formation of a second temporary mask RES2 and a removal of the dielectric layers D1, D2, D3 at the contact region BOND_REG.
The second temporary mask RES2, typically made of photosensitive resin, covers the dicing region SL_REG and is particularly formed on the layer of silicon nitride or silicon oxide deposited in step 103. The layer of silicon nitride is typically a material which offers a superior adherence to the second temporary mask RES2 than other types of dielectric material such as silicon oxide or monocrystalline silicon of the substrate SUB. The second temporary mask RES2 uncovers, furthermore, the dielectric layers D1, D2, D3 as well as the layer of silicon nitride in the contact region BOND_REG.
The dielectric layers D1, D2, D3, the layer of silicon nitride or silicon oxide and the layers of the interconnection network INTRCX are then removed until a surface S_PAD of the metal contact PAD is uncovered.
The dicing method also comprises an intermediate step of removing the second temporary mask RES2 (not illustrated). The second temporary mask RES2 can be removed by wet chemistry not constrained by the risk of damage of the ultra-low dielectric constant dielectric layers. Indeed, the uniform layer of silicon nitride or silicon oxide which covers the edges of the dicing line makes it possible to protect the external edge FL of the layers of the interconnection network INTRCX, and therefore makes it possible to prevent delaminations in the layers of the interconnection network INTRCX.
The second etching, carried out independently of the first etching, can thus be optimized and configured specifically for the manufacture of the metal contact PAD, without for all that causing damage to the ultra-low constant dielectric layers, given that the latter are protected by the vertical dielectric layer BUFF1.
The first etching step 201 comprises a formation of a third temporary mask RES3 and a removal of the layers of the interconnection network INTRCX.
The third temporary mask RES3, typically made of photosensitive resin, covers the interconnection network INTRCX in the contact region BOND_REG and uncovers the interconnection network INTRCX in the dicing region SL_REG.
The layers of the interconnection network INTRCX are then removed until the substrate SUB is uncovered in the dicing region SL_REG. Advantageously, the removal of these layers is carried out by reactive ion etching (RIE).
In particular, a vertical portion of the dielectric layers D1, D2 and D3 covers the edge FL of the layers of the interconnection network INTRCX located on the edges of the opening of the dicing line made in step 201. The vertical portion of the dielectric layers D1, D2, D3 corresponds to the vertical dielectric layer BUFF2, which will have the same function of protecting the external edge FL of the layers of the interconnection network INTRCX described above in relation to
The dielectric layers D1, D2, D3 of the hard mask HM will have the same structure formed inside the etched part during the first etching step 201 and above the contact PAD.
The second etching step 203 comprises a formation of a fourth temporary mask RES4 on the dielectric layers D1, D2, D3 of the wafer. The fourth temporary mask RES4, typically made of resin, has an opening in the contact region BOND_REG and an opening in the dicing region SL_REG. More specifically, the fourth temporary mask RES4 covers the vertical portion of the dielectric layers D1, D2 and D3 in the dicing region SL_REG.
The second etching step 203 comprises a removal of the dielectric layers D1, D2, D3 in the contact region BOND_REG and in the dicing region SL_REG. The dielectric layers D1, D2, D3 under the opening of the mask RES4 in the contact region BOND_REG are removed until the metal contact PAD is uncovered and those under the opening of the mask RES4 in the dicing region SL_REG are removed until the substrate SUB is uncovered.
Thus, an equal thickness Ed of dielectric layers D1, D2, D3 is removed, in the same etching step, in the dicing region SL_REG and in the contact region BOND_REG while keeping the vertical portion of dielectric layers D1, D2, D3 corresponding to the vertical dielectric layer BUFF2.
The second etching step 203 can then be completed when the metal contact PAD in the contact region BOND_REG and the substrate SUB in the dicing region SL_REG are uncovered without for all that exposing the contact region BOND_REG to prolonged etching and thus not causing metal dispersion in the vacuum chambers.
Furthermore, the dimensions of the opening of the fourth temporary mask RES4 in the dicing region SL_REG (smaller and located inside the location of the opening of the third temporary mask RES3) make it possible to keep, at the end of the removal of the dielectric layers, a vertical portion of dielectric layers protecting the interconnection network INTRCX in the dicing line.
The hard mask HM thus has a pattern resulting from the second etching step 203 and defining the dicing line in the dicing region SL_REG.
In the two alternatives, the dicing method further comprises a step of plasma dicing of the semiconductor wafer WF into semiconductor chip devices singulated from one another DISP in the dicing line SL_REG defined by the pattern of the hard mask HM.
The semiconductor chip device DISP, as represented in
The interconnection network INTRCX is covered with a vertical dielectric layer CDV1, for example with a layer of silicon nitride (or a layer of silicon oxide according to the material used during step 103 described above in relation to
In an alternative illustrated in
Moreover, the vertical dielectric layer CDV1, CDV2 extends along the external edge FL of the chip from the level of the substrate SUB, preferably along the entire interconnection network INTRCX, and has an arc-shaped outer face. Advantageously, the vertical dielectric layer CDV1, CDV2 is configured to cover the interconnection network INTRCX on the external edge FL of the chip, along the entire perimeter of the semiconductor device DISP.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2302754 | Mar 2023 | FR | national |
