Patent Application
20240128308
The present invention relates to semiconductor processing and semiconductor devices, and more particularly, to structures of dielectric films on a substrate, including ferroelectric high-k films that may be used as capacitors and memory cells in semiconductor devices.
Dielectric materials that are ferroelectric (FE) and antiferroelectric (AFE) are types of dielectric materials that can, for example, be used for CMOS-related applications, including field-effect transistor (FET) devices and dynamic random-access memory (DRAM) devices. Resistive RAM (ReRAM) devices are a class of storage memory devices that have received much attention due to the potential payout toward high-density/low-cost/low-energy non-volatile memories. A requirement for film stacks containing these dielectric materials for data storage includes long retention times and high switching speeds.
Embodiments of the invention provide a method for fabricating a ferroelectric device. The ferroelectric device can include a ferroelectric material that is integrated with metal electrodes in a film stack. The disclosed method includes forming a retention enhancement layer on a surface of a lower electrode layer using a gas phase oxidation process, where the resulting ferroelectric device has improved retention performance and high reliability.
According to one embodiment, the method includes providing a lower electrode layer on a substrate, forming a retention enhancement layer by oxidizing a surface of the lower electrode layer using a gas phase oxidation process, and depositing a ferroelectric high-k metal oxide layer over the retention enhancement layer using a vapor deposition process.
According to another embodiment, the method includes providing a lower electrode layer on a substrate, forming a retention enhancement layer by oxidizing a surface of the lower electrode layer using ozone, depositing a ferroelectric hafnium zirconium oxide (HfZrOx) layer in direct physical contact with the retention enhancement layer using a vapor deposition process, and depositing an upper electrode layer above the ferroelectric hafnium zirconium oxide layer.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Embodiments of the invention provide a method for fabricating a ferroelectric device that includes a ferroelectric material integrated with a retention enhancement layer and metal electrodes in a film stack. According to one embodiment, the method includes providing a lower electrode layer on a substrate, forming a retention enhancement layer on the lower electrode layer using a gas phase oxidation process, and depositing a ferroelectric high-k metal oxide layer over the retention enhancement layer using a vapor deposition process. The formation of the retention enhancement layer on the lower electrode layer results in improved retention performance and good reliability of the resulting ferroelectric memory device.
According to one embodiment, schematically shown in
The method further includes, in 110, forming a retention enhancement layer 220 on the lower electrode layer 200 using a gas phase oxidation process. This is schematically shown in
According an embodiment, forming the retention enhancement layer 220 incorporates oxygen atoms into a surface of the lower electrode layer 200 and the oxygen incorporation does not significantly increase the thickness of the lower electrode layer 200. In other words, the combined thickness of the retention enhancement layer 220 and the lower electrode layer 200 in
According to one embodiment, forming the oxidized surface includes: a) exposing the substrate 20 to gas phase ozone, b) purging the process chamber with an inert gas, and c) repeating steps a) and b) at least once. In one example, ozone may be flowed for about 5 seconds in step a), and the inert gas may be flowed for about 10 seconds in step b).
According to one embodiment, forming the oxidized surface includes performing plasma oxidation on the lower electrode layer 200. In one example, the gas phase oxidation process includes a gas exposure time between about 30 seconds and about 30 minutes to a plasma-excited oxygen-containing gas (e.g., O2).
According to one embodiment, performing the plasma oxidation includes using a microwave excitation source to excite O2 gas, and exposing the substrate 20 to the excited O2 gas.
According to one embodiment, performing the plasma oxidation includes using a remote plasma excitation source to excite O2 gas, and exposing the substrate 20 to the plasma-excited O2 gas.
According to one embodiment, forming the oxidized surface on the lower electrode layer 200 further includes heating the substrate 20 to a temperature between about room temperature and about 500° C. According to one embodiment, forming the retention enhancement layer 220 further includes heating the substrate 20 to a temperature between about 250° C. and about 300° C.
The method further includes, in 120, depositing a ferroelectric high-k metal oxide layer 240 over the retention enhancement layer 220 using a vapor deposition process. According to one embodiment, the ferroelectric high-k metal oxide layer 240 is in direct physical contact with the retention enhancement layer. This is schematically shown in
According to some embodiments, the ferroelectric high-k metal oxide layer 240 includes a ferroelectric high dielectric constant (high-k) material with a dielectric constant greater than that of SiO2 (k˜4). In some embodiments, the vapor deposition process can include chemical vapor deposition (CVD) or atomic layer deposition (ALD). In the example of ALD, the process can include cycles of alternating saturating gaseous exposures of a metal-containing precursor and an oxidizer, where each cycle includes one exposure of the metal-containing precursor, followed by one exposure of the oxidizer. Each cycle deposits one atomic layer or less of the metal oxide, and the number of cycles may selected in order to accurately control the film thickness. Steric hindrance of ligands in the metal-containing precursor and the oxidizer, and a limited number of bonding sites, can limit the chemisorption on the substrate surface, and therefore the film growth per cycle can remain at less than one atomic layer.
In one embodiment, depositing the ferroelectric high-k metal oxide layer 240 includes, sequentially first, exposing the substrate 20 to a metal-containing precursor vapor, and, sequentially second, exposing the substrate 20 to an oxygen-containing gas.
According to some embodiments, the ferroelectric high-k metal oxide layer 240 can contain zirconium oxide (ZrO2), hafnium oxide (HfO2), or laminates or mixtures thereof. In one example, the ferroelectric high-k metal oxide layer 240 can be hafnium zirconium oxide (HfZrOx). The HfO2 or ZrO2 may be doped with aluminum (Al), gadolinium (Gd), lanthanium (La), silicon (Si), strontium (Sr), or yttrium (Y) dopants.
In one example, a ferroelectric high-k metal oxide layer 240 containing ZrO2 may be deposited by ALD using cycles of alternating gaseous exposures of a zirconium-containing precursor and an oxidizer. In another example, a ferroelectric high-k metal oxide layer 240 containing a mixture of ZrO2 and HfO2 may be deposited by ALD using cycles of alternating gaseous exposures of a zirconium-containing precursor, and oxidizer, a hafnium-containing precursor, and an oxidizer. In yet another example, a ferroelectric high-k metal oxide layer 240 containing doped HfO2 may be deposited by ALD using cycles of alternating gaseous exposures of a hafnium-containing precursor, a dopant gas, and an oxidizer. The dopant concentration can, for example, be between about 0.1 atomic % and about 20 atomic %, between about 0.1 atomic % and about 10 atomic %, or between about 0.1 atomic % and about 1 atomic %.
Embodiments of the invention may utilize a wide variety of zirconium (Zr) and hafnium (Hf) precursors for the vapor phase deposition. For example, representative examples include: Zr(OtBu)4 (zirconium tert-butoxide, ZTB), Zr(NEt2)4 (tetrakis(diethylamido)zirconium, TDEAZ), Zr(NMeEt)4 (tetrakis(ethylmethylamido)zirconium, TEMAZ), Zr(NMe2)4 (tetrakis(dimethylamido)zirconium, TDMAZ), Hf(OtBu)4 (hafnium tert-butoxide, HTB), Hf(NEt2)4 (tetrakis(diethylamido)hafnium, TDEAH), Hf(NEtMe)4 (tetrakis(ethylmethylamido)hafnium, TEMAH), and Hf(NMe2)4 (tetrakis(dimethylamido)hafnium, TDMAH). In some examples, tris(dimethylaminocyclopentadienylhafnium (HfCp(NMe2)3) available from Air Liquide as HyALD™ may be used as a hafnium precursor and tris(dimethylaminocyclopentadienylzirconinum (ZrCp(NMe2)3) available from Air Liquide as ZyALD™ may be used as a zirconium precursor. The oxidizer may include an oxygen-containing gas, including plasma-excited O2, water (H2O), or ozone (O3).
The Al, Gd, La, Si, Sr, and Y dopants may be provided using any dopant gases that have sufficient reactivity, thermal stability, and volatility.
Examples of Al precursors include Al2Me6, Al2Et6, [Al(O(sBu))3]4, Al(CH3COCHCOCH3)3, AlBr3, AlI3, Al(O(iPr))3, [Al(NMe2)3]2, Al(iBu)2Cl, Al(iBu)3, Al(iBu)2H, AlEt2Cl, Et3Al2(O(sBu))3, and Al(THD)3.
Examples of Gd precursors include Gd(N(SiMe3)2)3, ((iPr)Cp)3Gd, Cp3Gd, Gd(THD)3, GdPOCCH(C2H5)C4H9]3, Gd(O(iPr))3, and Gd(acac)3.
Examples of La precursors include La(N(SiMe3)2)3, La(N(iPr)2)3, La(N(tBu)SiMe3)3, La(TMPD)3, ((iPr)Cp)3La, Cp3La, Cp3La(NCCH3)2, La(Me2NC2H4Cp)3, La(THD)3, La[OCCH(C2H5)C4H9]3, La(C11H19O2)3CH3(OCH2CH2)3OCH3, La(C11H19O2)3·CH3(OCH2CH2)4OCH3, La(O(iPr))3, La(OEt)3, La(acac)3, La(((tBu)2N)2CMe)3, La(((iPr)2N)2CMe)3, La(((tBu)2N)2C(tBu))3, La(((iPr)2N)2C(tBu))3, and La(FOD)3.
Examples of silicon precursors include silane (SiH4), disilane (Si2H6), monochlorosilane (SiClH3), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), hexachlorodisilane (Si2Cl6), diethylsilane (Et2SiH2), and alkylaminosilane compounds. Examples of alkylaminosilane compounds include, but are not limited to, di-isopropylaminosilane (H3Si(NPr2)), bis(tert-butylamino)silane ((C4H9(H)N)2SiH2), tetrakis(dimethylamino)silane (Si(NMe2)4), tetrakis(ethylmethylamino)silane (Si(NEtMe)4), tetrakis(diethylamino)silane (Si(NEt2)4), tris(dimethylamino)silane (HSi(NMe2)3), tris(ethylmethylamino)silane (HSi(NEtMe)3), tris(diethylamino)silane (HSi(NEt2)3), and tris(dimethylhydrazino)silane (HSi(N(H)NMe2)3), bis(diethylamino)silane (H2Si(NEt2)2), bis(di-isopropylamino)silane (H2Si(NPr2)2), tris(isopropylamino)silane (HSi(NPr2)3), and (di-isopropylamino)silane (H3Si(NPr2).
Examples of Sr precursors include Bis(tert-butylacetamidinato)strontium (TBAASr), Sr-C, Sr-D, Sr(N(SiMe3)2)2, Sr(THD)2, Sr(THD)2 (tetraglyme), Sr(iPr4Cp)2, Sr(iPr3Cp)2, and Sr(Me5Cp)2.
Examples of Y precursors include Y(N(SiMe3)2)3, Y(N(iPr)2)3, ((iPr)Cp)3Y, Cp3Y, Y(THD)3, Y[OOCCH(C2H5)C4H9]3, Y(O(iPr))3, Y(acac)3, (C5Me5)2Y, Y(hfac)3, and Y(FOD)3.
In the above precursors, as well as precursors set forth below, the following common abbreviations are used: Si: silicon; Me: methyl; Et: ethyl; iPr: isopropyl; nPr: n-propyl; Bu: butyl; nBu: n-butyl; sBu: sec-butyl; iBu: iso-butyl; tBu: tert-butyl; Cp: cyclopentadienyl; THD: 2,2,6,6-tetramethyl-3,5-heptanedionate; TMPD: 2,2,6,6-tetramethylpiperidide; acac: acetylacetonate; hfac: hexafluoroacetylacetonate; and FOD: 6,6,7,7,8,8,8-heptafluoro-2,2-dimethyl-3,5-octanedionate.
Following deposition of the ferroelectric high-k metal oxide layer 240, a heat-treating process may be performed on the substrate 20 using a predetermined substrate temperature and time period. The heat-treating organizes the atomic elements in the ferroelectric high-k metal oxide layer 240, reduces the film stress, and locks in the crystallographic orientation of the ferroelectric high-k metal oxide layer 240. The heat-treating may be performed at a substrate temperature of about 500° C. or lower, between about 200° C. and about 500° C., between about 200° C. and about 300° C., between about 300° C. and about 400° C., or between about 400° C. and about 500° C. In one example, the heat-treating may be performed in the same process chamber as the deposition of the ferroelectric high-k metal oxide layer 240. In another example, the heat-treating may be formed in a different process chamber than the deposition of the ferroelectric high-k metal oxide layer 240. The heat-treating may be performed under vacuum conditions in the presence of an inert gas, for example argon(Ar) or nitrogen (N 2).
Referring back to
According to one embodiment, a method is provided for fabricating a ferroelectric device, where the method includes providing a lower electrode layer on a substrate, forming a retention enhancement layer by oxidizing a surface on the lower electrode layer using ozone, depositing a ferroelectric hafnium zirconium oxide (HfZrOx) layer in direct physical contact with the retention enhancement layer using a vapor deposition process, and depositing an upper electrode layer above the ferroelectric hafnium zirconium oxide layer. The lower electrode layer can include a titanium (Ti) metal layer, a tungsten (W) metal layer, or a laminate thereof, and the upper electrode layer can include a tungsten (W) metal layer. In one example, the film stack can include a 10 nm W upper electrode layer, a 10 nm HfZrOx layer, and a 1.0 nm Ti/50 nm W lower electrode layer.
According to one embodiment, the steps of forming the retention enhancement layer using a gas phase oxidation process, and depositing a ferroelectric high-k metal oxide layer over the retention enhancement layer using a vapor deposition process, may be performed on the same processing tool without air exposure between the steps. The steps may be performed in the same process chamber or in different process chambers.
In one example, the process chamber may be configured to perform plasma exposure of a lower electrode layer to form a retention enhancement layer by gas phase oxidation. In another example, the process chamber may be configured to also perform atomic layer deposition (ALD) of a ferroelectric material over the retention enhancement layer. In another example, a first process chamber may be configured to perform surface oxidation of a lower electrode layer to form a retention enhancement layer by gas phase oxidation. Further, following the surface oxidation, the substrate may be transferred to a second process chamber that is configured to perform atomic layer deposition (ALD) of a ferroelectric material over the retention enhancement layer.
The exemplary film stack described in
The electrical tests included the steps of writing an original complementary data state into the first and second test structures after the test structures were initialized into an initial valid data state. The first and second test structures were then subjected to time and temperature stress. The original complementary data state from the first and second test structures was then read, and same state charge (Q_SS) information collected. An opposite complementary data state was then written in the first and second test structures. After a short time interval, the Opposite complementary data state from the first and second test structures was read to gather opposite state charge (Q_OS) information. The original complementary data state was then written into the first and second test structures. The first and second test structures were then subjected to further stress cycles, after which the same state and opposite state charge values were recorded.
Plots of the same state charge (Q_SS) versus log time are shown in
A plurality of embodiments for a ferroelectric device have been described. The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms that are used for descriptive purposes only and are not to be construed as limiting. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
This application is related to and claims priority to U.S. Provisional Patent Application Ser. No. 63/379,938 filed on Oct. 18, 2022, the entire contents of which are herein incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63379938 | Oct 2022 | US |
