Claims
- 1. A method for fabricating a memory chip, comprising:providing a substrate; forming a conductive layer over said substrate, said conductive layer formed in such a manner as to include at least one raised portion characterized by a tip having a first cross-sectional area and a base having a second cross-sectional area, said second cross-sectional area of said base being larger than said first cross-sectional area of said tip; providing an insulative material over at least a portion of said conductive layer; depositing a programmable resistive material in contact with said tip of said at least one raised portion of said conductive layer.
- 2. The method of claim 1, wherein depositing said programmable resistive material comprises depositing a chalcogenide material.
- 3. The method of claim 2, further comprising selecting said chalcogenide material from a group consisting of tellurium (Te), germanium (Ge), antimony (Sb), and combinations thereof.
- 4. The method of claim 3, further comprising formulating said chalcogenide material to include Te, Ge, and Sb in a ratio TeaGebSb100−(a+b), where a, b, and 100−(a+b) are in atomic percentages which total 100% of constituent elements and a≦70% and 15%≦b≦50%.
- 5. The method of claim 4, wherein 40%≦a≦60% and 17%≦b≦44%.
- 6. The method of claim 1, wherein forming said conductive layer comprises:forming a planar conductive layer over said substrate; forming an oxide layer on said planar conductive layer; patterning said oxide layer to form at least one oxide element; and etching said planar conductive layer to form said at least one raised portion characterized by said tip having said first cross-sectional area and said base having said second cross-sectional area, said second cross-sectional area of said base being larger than said first cross-sectional area of said tip.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of application Ser. No. 09/586,144 filed Jun. 2, 2000, now U.S. Pat. No. 6,294,452, issued on Sep. 25, 2001, which is a continuation of application Ser. No. 08/956,594, filed Oct. 23, 1997, now U.S. Pat. No. 6,150,253, issued Nov. 21, 2000, which is a continuation-in-part of U.S. patent application Ser. No. 08/724,816, filed Oct. 2, 1996, now U.S. Pat. No. 6,147,395, issued Nov. 14, 2000.
US Referenced Citations (32)
Foreign Referenced Citations (2)
Number |
Date |
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07-058204 |
Aug 1993 |
JP |
WO 9641380 |
Dec 1996 |
WO |
Continuations (2)
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Parent |
09/586144 |
Jun 2000 |
US |
Child |
09/963842 |
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US |
Parent |
08/956594 |
Oct 1997 |
US |
Child |
09/586144 |
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US |
Continuation in Parts (1)
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08/724816 |
Oct 1996 |
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08/956594 |
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