1. Field of the Invention
The present invention relates to semiconductor packaging technology generally and more specifically, to bonding of flip-chip devices to a substrate using copper pillars and solder.
2. Description of the Related Art
Copper pillars are a widely used technique for electrically interconnecting a flip-chip semiconductor device or “chip” to conductors on an organic-based substrate, such as a thin (less than one millimeter thick) glass-epoxy board, because copper pillar interconnects have superior geometric control, higher density, and electrical performance relative to solder bump interconnects. The copper pillars formed on the device's die pads connect to the substrate's substrate pads by using a solder layer between each pillar and the respective substrate pad to join the copper pillars to the substrate pads.
To bond a flip-chip device to a substrate, the device and substrate are brought together and heated until the solder formed (usually by plating) on the ends of the copper pillars melts and wets the substrate pads on the substrate, each pillar and solder combination forming a lone. Then the device-substrate combination is cooled down and the solder solidifies to bond the device to the substrate, forming a bonded device-substrate structure or “package”. However, because the coefficient of thermal expansion (CTE) for the flip-chip device is significantly different from that of the substrate, changes in the package temperature causes the position of the substrate pads to laterally shift relative to die pads. This shift is referred to as offset, the amount of misalignment between a die pad and the corresponding substrate pad. During bonding, the device and the substrate are cooled down from the temperature that the solder melts to the temperature the solder solidifies and then to room temperature. As the package cools, the amount of offset each joint is subject to changes depending on where the pillars are located on the device. For example, the offset might be zero at the center of the device and tens of microns for pillars on pads at the periphery of the device. The larger the offset, the less likely the joint between a die pad and a substrate pad will occur without defects, such as voided regions and cracks, in the solder due to insufficient solder volume between the substrate pad and the pillar. The tendency to void or crack is particularly prevalent in smaller volume solder joints such as those found with copper pillar interconnect. Differences in height between the die pad and the corresponding substrate pad due to warping of the substrate or other variations can further aggravate the formation of the solder voids and cracks. Temperature cycling of the package will tend to drive solder creep that can weaken marginal joints, leading to additional cracks. Voids and cracks essentially decrease the cross sectional area of the solder joint, this combined with the small area at the tip of the void/crack enhances the propensity for crack initiation and growth in the solder when exposed to temperature cycling and or other thermal mechanical stresses that a device experiences during testing, transportation, or operation. Moreover, the temperature cycling and other stresses can cause the cracks to eventually cause separation in the copper pillar and solder joint connecting, the die to the substrate, possibly resulting in a functional failure of the packaged device. Thus, it is desirable to find a process for device-substrate bonding using copper pillars that might result in fewer interconnection defects and, concomitantly, a more reliable bonded device-substrate package.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.
Described embodiments include a package comprising a flip-chip device, a plurality of copper pillars, a substrate, and a plurality of solder layers. The flip-chip device has a centroid and a plurality of die pads thereon. Each of the copper pillars is disposed on a respective die pad of the plurality of die pads. The substrate has a plurality of substrate pads thereon and each of the solder layers is disposed between a respective copper pillar and a respective substrate pad. Each substrate pad has an offset from a respective die pad at a specific temperature, the offset for each of the substrate pads of the is substantially the same, and the offset is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, and a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate. Alternatively, the offset for each of the substrate pads is not substantially the same and instead the above-determined offset is scaled as a function of a distance the respective die pad is from the centroid of the device.
Other embodiments of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. The drawings are not to scale.
Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation”.
As used in this application, the word “exemplary” is used herein to mean serving, as an example, instance, or illustration. Any aspect or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the word exemplary is intended to present concepts in a concrete fashion.
It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary. Likewise, additional steps might be included in such methods, and certain steps might be omitted or combined, in methods consistent with various embodiments of the present invention.
Also for purposes of this description, the terms “couple”, “coupling”, “coupled”, “connect”, “connecting”, or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled”, “directly connected”, etc., imply the absence of such additional elements.
The present invention will be described herein in the context of illustrative embodiments of a process to bond a flip-chip device to a substrate by joining die pads on the flip-chip device to substrate pads on the substrate using joints of copper pillars and solder. Each substrate pad has an offset from a respective die pad at a specific temperature and the offset is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, and a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate. In one embodiment the offset for each of the substrate pads of the is substantially the same and, in another embodiment, the offset for each of the substrate pads is equal to the above-determined offset scaled as a function of a distance the respective die pad is from the centroid of the device.
In this example, the joints 106 are arranged with a higher density near the center or NPD of the device 102 than at the edges of the device. Generally, power and ground are supplied to the device 100 using the joints 106 at the center of the device 102 and high-speed signals are carried using the joints 106 at the edges of the device 102.
Referring to
The copper pillar 108 has a height of HP and the solder layer 110 has a height of HS (before melting), and both have an approximate diameter D. The height of the joint is HP÷HS. In various embodiments, the height of the joint prior to melting ranges from 5 μm to 130 μm.
During the bonding process, the substrate 104 and device 102 are brought together so that the solder layer 110 contacts the respective substrate pad 114. The device and substrate are heated sufficiently for the solder 110 to melt, wetting both the substrate pad 114 and at least along part of the sides of the pillar 108 to form a joint. Then everything is cooled sufficiently for the solder 110 to solidify, thereby electrically and mechanically bonding the device 102 to the substrate 104.
To address the above-described problem with large offsets, the combination of a copper pillar 108 and solder 110 between a die pad 112 and a substrate pad 114 has been modeled and the results are shown in
A flip-chip device 102 will have many tens to tens of thousands or more of joints 106. When considering the totality of all joints for a package 100, with the solder in the liquid state, the joints 106 are effectively captured between two rigid surfaces one being the die pads 112 and the other being the substrate pads 114. Force equilibrium requires that the sum of the forces over all of the joints equal the weight of the die, which can be approximated as zero for the case where there are many joints. Further, with each joint having a distinct force-height response curve as determined, by its degree of offset, the equilibrium requirement of zero net force implies some joints will be in tension while other will be in compression.
As shown in
Due to heat transfer dynamics in a reflow chamber where the device 102 is bonded to the substrate 104, the solder in the joints along the outer regions of the device will tend to cool faster and solidify before the joints toward the center of the device. While not wishing to be held to a particular theory, it is believed that at the start of solidification, these outer joints will be in tension due to their higher degree of offset. Because solder solidification is accompanied by volumetric shrinkage, which will tend to increase the tension in the outer joints before they fully solidify, collapse of the outer joints (i.e., the reduction in joint height in response to their tensile forces) is prevented by the opposing compressive force of the joints towards the center of the device 102 for which the solder is still in the liquid state. In this scenario, the outer joints become starved of solder as they solidify and will tend to exhibit tearing or cracking in the solder.
Any warpage of the package 100 that occurs during the cooling/solder solidification process might aggravate the solder-starved nature of the outer joints, thus increasing the potential for cracking.
In accordance with one embodiment of the invention, a method of decreasing the tendency of the outer joints to exhibit solder cracking during solidification is to reduce the tensile forces in those joints.
As shown in
Recognizing this, the substrate pads positions are designed such that all of them have a calculated offset of an amount, such as 20 μm at a specific temperature such as room temperature (e.g., 25° C.) or the expected device operating temperature (e.g., 75° C.), although other offsets and temperatures could be used instead if they are found to provide acceptable joint shape. This is shown in
The amount of offset 302, 402 might be determined from a joint force diagram similar to that shown in
Offset=DNPmax×(CTEsubstrate−CTEdevice)×(Tsolidification−T) (Eqn. 1)
In one embodiment, the temperature T is an expected operating temperature of the device (e.g., 75° C.) and in another embodiment; T is room temperature (e.g., 25° C.).
In an alternative embodiment and as shown in
Offsetpad=Offset×(1−DNPpad/DNPmax) (Eqn. 2)
As shown in
The CTE of Si is approximately 3 ppm/° C., the CTE of an organic substrate (e.g., FR-4) is approximately 13 ppm/° C. (this might range between 10 and 30 ppm/° C. for organic-base substrate and could be smaller, e.g., 5 to 10 ppm/° C. for certain low-CTE ceramic substrates). Here, assuming lead free solder with up to 50° C. undercooling, a solidification temperature (Tsolidification) of 185° C. and a specified (e.g., room) temperature T of 25° C. In this case and from Eqn. 1, the amount of offset (Offset) is (13−3 ppm/° C.)×(185° C.−25° C.) or 0.16%. Assuming a 20 mm×20 mm device, DNPmaximum (the distance from the center of device or NP to the farthest corner of the device) is 14.14 mm. Thus, from Eqn. 1, the maximum offset is 14.4 mm×0.16% or approximately 22.6 μm. In the embodiment shown in
In this embodiment, the copper pillars have a diameter of approximately 80 μm, a height HP of 20-70 μm, and the solder layers, prior to melting, have a height HS of 10-60 μm so that the total height is approximately 80 μm and might range from 5 μm to 130 μm. However, it is understood that the ratio of the height of the copper pillar to the height of the solder layer before melting can range from 1:10 to 100:1. The width of the substrate and die pads typically range from about 80% to about 120% of the diameter of the copper pillars.
In an alternative embodiment, instead of applying the solder to the ends of the copper pillars, a solder layer is formed on the substrate pads 114 by using a patterned solder mask on the substrate 104 with the solder pads exposed and the solder plated onto the exposed pads, using either conventional electroplating or electroless plating.
Although the elements in the following method claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being, implemented in that particular sequence.
It is understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention might be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims.
The subject matter of this application is related to U.S. patent application Ser. No. 14/190,582, filed concurrently herewith as attorney docket no. L13-1421US1, titled “Method for Flip-Chip Bonding Using Copper Pillars”, the teachings of which are incorporated herein by reference.