Patent Application
20060237320
The present invention relates generally to semiconductor processing technology, and more particularly to a method for forming a metal layer in multiple steps.
Semiconductor integrated circuits (ICs) have many levels of patterned metal layers. Different levels of metal layers can be connected by interconnection structures, such as vias and cross-over trenches that contain inlaid conductive materials. The process of forming the metal layers is usually referred to as metallization. Copper is usually selected as the material for forming the metal layers, because of its superior electrical conductivity.
The copper layer is usually formed by an electroplating process. A thin seed layer is deposited on an underlying material, such as a semiconductor substrate or a dielectric layer. The underlying material, on which the seed layer is disposed, is placed in a chemical electroplating solution or a chemical reaction chamber. The seed layer then grow into a thicker copper layer atop the underlying material. The copper layer is then patterned to form a desired conductive structure.
In certain applications, some very thick copper layers are needed. Those thick copper layers often cause the problem of “hillock.” During the electroplating process, each grain grows in an individual crystal orientation. As growth proceeds, grains fill the space between them and generally grow upward at similar rates. However, some grains find early nucleation and have a head start in growth. Also, some grains grow at a crystal orientation that promotes a faster growth rate. Such grains that grow substantially taller than their neighbors are identified as “hillocks.” As the thickness of the copper layer increases, the problem of “hillock” becomes more serious. When the thickness of the copper layer is under 13K angstroms, the grain size of copper is relatively small, and does not cause serious problems to the copper layer. However, when the thickness of the copper layer is above 40K angstroms, the copper grain may become a “hillock,” and cause serious problems to the copper layer.
The “hillocks” may cause certain drawbacks. One drawback is the irregular etching rates over the surface of the copper layer due to the “hillocks.” Another drawback is that the “hillocks” may increase the possibility of bumping failures when using the copper layer as a bonding pad during an IC packaging process.
Therefore, desirable in the art of semiconductor processing technology is a method for forming a metal layer without suffering from the “hillock” problems.
The present invention discloses a method for forming a metal layer having a predetermined thickness on an underlying material. In one embodiment of the invention, the underlying material is electroplated to form the metal layer having a fraction of the predetermined thickness thereon. The step of electroplating is interrupted for a predetermined period of time. The step of electroplating is then resumed to form the metal layer having the predetermined thickness on the underlying material, thereby improving planarity of the metal layer.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
In this embodiment, the metal layer 206 is made of copper. However, other conductive materials, such as aluminum, titanium, tantalum, cobalt, nickel, and an alloy thereof, can also be selected as the material for the metal layer 206. The predetermined time period of interruption can be any time period more than one second. The predetermined thickness is the thickness eventually the metal layer 206 will have after the processing steps present by
During the interruption of the electroplating process, the semiconductor structure 200 is removed from the chemical electroplating solution or the chemical reaction chamber. This interrupts the continuous growth of the grains 208.
The advantage of this invention is that the totality of the irregularity of the originally grown metal layer and the irregularity of the additional metal layer is less than that of the irregularity of a metal layer formed by the conventional one-step electroplating process. The full predetermined thickness of the metal layer may be divided into more than two metal layers of fractional thickness. The steps of interrupting and resuming the electroplating process can be repeated for many times to form a metal layer of a desirable thickness without generating “hillocks.” Thus, the present invention helps to provide the surface of metal layer with even etching rates. It also helps to reduce the possibility of bumping failure when using the metal layer as a bounding pad during an IC packaging process.
The above illustration provides many different embodiments or embodiments for implementing different features of the invention. Specific embodiments of components and processes are described to help clarify the invention. These are, of course, merely embodiments and are not intended to limit the invention from that described in the claims.
Although the invention is illustrated and described herein as embodied in one or more specific examples, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention, as set forth in the following claims.
