Claims
- 1. A method comprising the steps of:
a) producing an amorphous region on a silicon body; b) forming a metal layer in contact with the amorphous region; and c) irradiating the metal layer with light to diffuse metal into the amorphous region to form an alloy region of silicide composition,
the irradiating step proceeding at least until the metal overlying the amorphous region is consumed to expose the alloy region, the increased reflectivity of the exposed alloy region relative to the metal reflectivity being sufficient to prevent further significant melting of the alloyed region.
- 2. A method as claimed in claim 1, further comprising the step of:
d) treating the alloy region to form a low-resistivity silicide region from the alloy region.
- 3. A method as claimed in claim 2, wherein said step (d) includes a substep of subjecting at least the alloy region to rapid thermal annealing.
- 4. A method as claimed in claim 2, further comprising the step of:
e) patterning at least one insulator layer and at least one conductive layer to form a conductive lead that contacts the silicide region.
- 5. A method as claimed in claim 1, wherein said step (a) includes a substep of implanting ions in the silicon body to form the amorphous region.
- 6. A method as claimed in claim 5, wherein the ions include at least one of silicon, argon, arsenic and germanium.
- 7. A method as claimed in claim 6, wherein the ions are implanted with an energy in a range from 10 to 100 kilo-electronVolts (keV).
- 8. A method as claimed in claim 6, wherein the substep of implanting is performed with a dosage in a range from 1013 to 1015 atoms per square centimeter.
- 9. A method as claimed in claim 5, further comprising the step of:
d) selecting at least one of ion species, ion energy and ion dosage to form the amorphous region to a predetermined depth,
said implanting substep performed based on said step (d).
- 10. A method as claimed in claim 1, further comprising the step of:
d) stripping an oxide layer from the silicon body after performing said step (a) and before performing said step (b).
- 11. A method as claimed in claim 10, wherein said step (d) includes a substep of immersing the silicon body in an acidic bath.
- 12. A method as claimed in claim 1, wherein said step (b) includes a substep of sputtering metal onto the amorphous region to form the metal layer.
- 13. A method as claimed in claim 12, wherein the metal includes at least one of titanium, cobalt, and nickel.
- 14. A method as claimed in claim 1, wherein said step (b) includes a substep of evaporating metal onto the amorphous region to form the metal layer.
- 15. A method as claimed in claim 1, wherein said step (b) includes a substep of forming the metal layer on the amorphous region by chemical vapor deposition.
- 16. A method as claimed in claim 1, wherein the metal layer is formed with a thickness greater than the predetermined depth to which the amorphous region is formed in the silicon body, divided by a consumption ratio of silicon to metal.
- 17. A method as claimed in claim 1, wherein said step (c) includes a substep of irradiating the metal layer with laser light.
- 18. A method as claimed in claim 17, wherein the laser light has a fluence that causes the amorphous region to melt while the metal layer and the silicon body remain in solid states.
- 19. A method as claimed in claim 18, wherein the fluence is in a range from 0.1 to 1.0 Joules per square centimeter.
- 20. A method as claimed in claim 17, wherein the metal layer is irradiated by the laser light in a series of shots.
- 21. A method as claimed in claim 1, wherein the silicon body is situated in an ambient medium including at least one of argon, helium and nitrogen during performance of said step (c).
- 22. A method comprising the steps of:
a) forming a field isolation layer on a silicon substrate; b) forming a first insulator layer on the silicon substrate; c) forming silicon regions over the first insulator layer and the field isolation layer; d) patterning the silicon regions and the first insulator layer to produce a gate silicon region overlying a gate insulator layer and at least one runner over the field isolation layer; e) doping at least regions of the silicon substrate adjacent the gate silicon region to form source and drain regions on the silicon substrate; f) forming a second insulator layer over the gate silicon region, the runner and the silicon substrate; g) etching the second insulator layer to form side walls in contact with the side of the gate silicon region and the runner; h) producing amorphous regions in the gate, source, drain and runner regions; i) forming a metal layer in contact with the amorphous regions; j) irradiating the metal layer with light to melt underlying regions and to diffuse metal into the molten regions to form alloy regions of silicide composition from the molten regions, the irradiating step continuing at least until after the metal overlying the gate alloy region is consumed so that the increased reflectivity of the gate alloy region relative to the metal layer reduces thermal loading of the gate alloy region as the source and drain alloy regions continue to grow; k) removing an unconsumed portion of the metal layer; and l) treating the alloy regions to form silicide regions.
- 23. A method as claimed in claim 22, further comprising the steps of:
m) forming a third insulator layer over the silicon substrate; n) patterning the third insulator layer to selectively expose the gate, source, drain and runner regions; and o) forming conductive leads on the third insulator layer that contact the gate, source, drain and runner regions.
- 24. A method as claimed in claim 22, wherein said step (h) includes a substep of implanting ions to form the amorphous regions.
- 25. A method as claimed in claim 22, wherein said step (i) includes a step of sputtering the metal layer onto the amorphous regions.
- 26. A method as claimed in claim 22, wherein the light used to irradiate the substrate in step (i) is laser light.
- 27. A method as claimed in claim 22, wherein the metal layer is formed in said step (i) with a thickness that is approximately sufficient to produce a stoichiometric alloy region in at least the gate.
- 28. A method as claimed in claim 22, wherein said step (j) is continued after consumption of the metal layer overlying the gate region to continue growth of the alloy regions in the source and drain regions.
- 29. A method comprising the steps of:
a) amorphizing regions on a gate, source, and drain of an integrated device formed on a silicon substrate; b) forming a metal layer in contact with the amorphized regions; c) irradiating the amorphized regions with light of an energy fluence sufficient to melt the amorphized region, yet insufficient to melt the metal and the silicon body, so that metal diffuses into the amorphized regions to form alloy regions of silicide composition, the irradiating step continuing at least until the metal layer overlying the gate region is consumed so that the increased reflectivity of the gate alloy region relative to the metal layer reduces further thermal loading of the gate region.
- 30. A method as claimed in claim 29, wherein the irradiating step is continued after the consumption of the metal layer overlying the gate region so that diffusion of metal into the alloy regions in the source and drain continues as the increased reflectivity of the gate alloy region substantially arrests further melting of the gate region so that the gate alloy region does not significantly advance beyond its boundaries existing upon consumption of the metal layer overlying the gate alloy region.
- 31. A method as claimed in claim 29, further comprising the steps of:
d) removing the unconsumed metal from the silicon body; and e) forming silicide regions from the alloy regions.
- 32. A method as claimed in claim 31, wherein said step (e) includes a substep of rapid thermal annealing of the alloy regions to produce the silicide regions.
- 33. A method as claimed in claim 29, wherein said step (a) includes a substep of implanting ions into the silicon substrate to produce the amorphized regions.
- 34. A method as claimed in claim 29, wherein said step (b) includes a substep of sputtering the metal onto the amorphized regions.
- 35. A method as claimed in claim 29, wherein said step (b) includes a substep of evaporating the metal onto the amorphized regions.
- 36. A method as claimed in claim 29, wherein said step (b) includes a substep of forming the metal in contact with the amorphized regions using chemical vapor deposition.
- 37. A method as claimed in claim 29, wherein the metal layer is formed in said step (b) with a thickness that produces an approximately stoichiometric alloy region upon consumption of the metal layer overlying the amorphous region by irradiation in said step (c).
- 38. A method as claimed in claim 29, wherein said step (c) includes a substep of irradiating the metal with laser light having a fluence in a range from 0.1 to 1.0 Joules per square centimeter.
- 39. A method as claimed in claim 38, wherein said step (c) includes a substep of irradiating the laser light in a series of shots.
- 40. A method as claimed in claim 39, wherein a predetermined number of shots in a range from 3 to 10 are delivered to the metal with a duration of 10 to 100 nanoseconds.
- 41. A method as claimed in claim 29, wherein the thickness of the alloy region over the gate is determined by the thickness of the metal layer formed in said step (b), and wherein the thickness of the silicide in the source and drain regions is determined by the depth to which the amorphizing is performed in said step (a).
- 42. A method as claimed in claim 29, wherein the fluence is within a range necessary to consume the metal layer formed in said step (b) in areas overlying the gate region and to allow the alloy region to grow to amorphization depths in the source and drain regions resulting from said step (a).
- 43. An integrated metal insulator semiconductor field effect transistor (MISFET) device having a gate silicide region that is thicker than the silicide regions overlying the source and drain.
- 44. An integrated metal insulator semiconductor field effect transistor (MISFET) device comprising:
a semiconductor substrate; a field oxide region formed in the substrate and bounding an area of the substrate; a source region formed in the substrate in the area bounded by the field oxide region; a drain region formed in the substrate in the area bounded by the field oxide region; an insulator layer situated on the substrate between the source and drain regions; a gate region overlying the insulator layer; a silicide region situated in contact with the gate region; a silicide region situated in contact with the source region; a silicide region situated in contact with the drain region,
the thickness of the gate silicide region greater than the thicknesses of the source and drain regions.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This patent application is a continuation-in-part of application Ser. No. 08/791,775 filed Jan. 29, 1997, in which the named inventors and assignee entity are the same.
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
08791775 |
Jan 1997 |
US |
Child |
09158346 |
Sep 1998 |
US |