Claims
- 1. A method of forming a conductor layer on a substrate comprising, in sequence, the steps of:
- previously forming a metal underlayer on a surface of a substrate designated to have a conductor formed thereon, said metal underlayer comprising an upper layer of chromium and said metal underlayer being patterned to have a pattern slightly larger than and similar to a desired conductor pattern;
- forming a polyimide insulation layer over said substrate surface, said polyimide insulation layer being patterned by dry etching to form a groove and to expose a portion of said metal underlayer on which said desired conductor pattern is to be formed;
- removing the upper layer of chromium with wet etching after formation of the groove to expose a metal layer of the underlayer active to electroless plating; and
- disposing a plating layer in the groove and on the exposed portion of said metal underlayer by carrying out electroless plating while applying said polyimide insulation layer as a mask and thereby forming a conductor layer with a high aspect ratio ranging from 0.6 to 1.5.
- 2. A method for forming a conductor layer according to claim 1, wherein said insulation layer is formed on the periphery of said metal underlayer.
- 3. A method for forming a conductor layer according to claim 14, wherein said metal underlayer comprises a chromium layer, a copper layer and a chromium layer in a sandwich structure.
- 4. A method for forming a conductor layer according to claim 1, wherein a photoresist layer formed by spin-coating an organosilicon polymer material and heating it is used as a mask for said dry etching.
- 5. A method for forming a conductor layer according to claim 1, wherein an SiO.sub.2 layer and a photoresist layer on said insulation layer are applied as a mask for said dry etching.
- 6. A fabrication method of multilayer conductor patterns according to claim 5, wherein said first insulation layer is formed on the periphery of said metal underlayer.
- 7. A fabrication method of multilayered conductor patterns comprising the steps of:
- (a) forming a metal underlayer on a surface of a substrate destined to have a conductor formed thereon, said metal underlayer comprising an upper layer of chromium and said metal underlayer being patterned to form a desired conductor pattern, with a slightly larger dimension than said conductor pattern;
- (b) forming a first polyimide insulation layer over portions of said substrate and said metal underlayer;
- (c) providing a conductor pattern in said first polyimide insulation layer by dry etching to from a groove and to expose a portion of said metal underlayer;
- (d) removing the upper layer of chromium with wet etching after formation of the groove to expose a metal layer of the underlayer active to electroless plating;
- (e) disposing a plating layer in the groove and on the exposed portion of the metal underlayer by conducting electroless plating while applying the first polyimide insulation layer as a mask and thereby forming a patterned conductor having a high aspect ratio ranging from 0.6 to 1.5;
- (f) forming a chromium layer on said patterned conductor;
- (g) forming a second polyimide insulation layer on said patterned conductor to form a through-hole on said conductor;
- (h) removing the chromium layer from the patterned conductor by wet etching;
- (i) filling a plating layer in said through-hole by carrying out electroless plating using said second polyimide insulation layer as a mask; and
- (j) forming multilayered conductor patterns comprising conductors and insulation layers alternately laminated by repeating said steps (a) to (j).
- 8. A fabrication method of multilayer conductor patterns according to claim 7, wherein said metal underlayer comprises a chromium layer, a copper layer and a chromium layer.
- 9. A fabrication method of multilayer conductor patterns according to claim 7, wherein a photoresist layer formed by spin-coating an organosilicon polymer material and heating it is applied as a resist mask for said dry etching.
- 10. A fabrication method of multilayer conductor patterns according to claim 7, wherein an SiO.sub.2 layer and a photoresist layer on said first insulation layer are applied as a mask for said dry etching.
Priority Claims (2)
Number |
Date |
Country |
Kind |
61-64970 |
Mar 1986 |
JPX |
|
61-103765 |
May 1986 |
JPX |
|
Parent Case Info
This application is a continuation of application Ser. No. 029,219, filed Mar. 23, 1987, now abandoned.
US Referenced Citations (11)
Non-Patent Literature Citations (1)
Entry |
Moriya et al., IEEE Electronic Components Conf. 1984, 0569-5503/84/0000-0082, pp. 82-87. |
Continuations (1)
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Number |
Date |
Country |
Parent |
29219 |
Mar 1987 |
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