Claims
- 1. A method for producing a multilayer wiring structure comprising a plural number of conductor pattern layers and a plural number of low-thermal-expansivity polyimide insulating film layers, the low-thermal expansivity polyimide forming the insulating film layers having a coefficient of thermal expansion of 2.times.10.sup.-5 K.sup.-1 to 4.times.10.sup.-6 K.sup.-1, which method comprises the steps of:
- (A) coating a flexible polymer resin on a substrate and heat-curing the polymer coating into a half-cured state;
- (B) applying on said polymer coating a polyamic acid varnish which is a low-thermal-expansivity polyimide precursor and forming a polyimide of a half-cured state by conducting a thermal condensation reaction;
- (C) applying on said polyimide a flexible polymer resin and heating it to form a flexible polymer film into a perfectly cured state;
- (D) bonding a copper foil on said flexible polymer film and etching said copper foil layer to form a conductor pattern layer;
- (E) coating a flexible polymer varnish on said conductor pattern layer and heat curing the polymer coating into a half-cured state;
- (F) applying on said polymer coating a polyamic acid varnish which is a low-thermal-expansivity polyimide precursor and subjecting the precursor to a thermal condensation reaction to form a polyimide layer into a half-cured state;
- (G) coating a flexible polymer varnish on the low-thermal-expansivity polyimide layer and heating the coating to form a polymer film into a perfectly cured state; and
- repeating the steps (D)-(E)-(F)-(G) at least once.
- 2. A method for producing a multilayer wiring structure comprising a plural number of conductor pattern layers and a plural number of low-thermal-expansivity polyimide insulating film layers, the low-thermal expansivity polyimide forming the insulating film layers having a coefficient of thermal expansion of 2.times.10.sup.-5 K.sup.-1 to 4.times.10.sup.-6 K.sup.-1, which method comprises the steps of:
- (A) depositing a thin copper film on a substrate;
- (B) applying and hardening a resist on said thin copper film and etching it to form a pattern;
- (C) forming a conductor pattern by electroplating of a metal and removing the resist;
- (D) coating a flexible polymer varnish on said conductor pattern layer and heat curing the polymer coating to form a polymer coating film into a half-cured state;
- (E) applying on said polymer coating film a varnish of polyamic acid which is a low-thermal-expansivity polyimide precursor, and subjecting the precursor to a thermal condensation reaction to form a polyimide layer into a half-cured state;
- (F) coating a flexible polymer varnish in the low-thermal-expansivity polyimide film and heating the coating to form a polymer coating film into a perfectly cured state;
- (G) depositing a thin copper film on said polymer coating film; and
- repeating the steps (B)-(C)-(D)-(E)-(F)-(G) at least once.
- 3. A method for producing a multilayer wiring structure comprising a plural number of conductor pattern layers and a plural number of low-thermal-expansivity polyimide insulating film layers, the low-thermal expansivity polyimide forming the insulating film layers having a coefficient of thermal expansion of 2.times.10.sup.-5 K.sup.-1 to 4.times.10.sup.-6 K.sup.-1, which method comprises the steps of:
- (A) depositing a thin copper film on a substrate;
- (B) applying and hardening a resist on said thin copper film and etching it to form a thin film pattern;
- (C) coating thereon a flexible polymer varnish and heat curing it to form a polymer coating film into a half-cured state;
- (D) applying on said polymer coating film a varnish of polyamic acid which is a low-thermal-expansivity polyimide precursor and subjecting the precursor to a thermal condensation reaction to form a polyimide layer into a half-cured state;
- (E) coating a flexible polymer varnish on said polyimide layer and heating the coating to form a polymer coating film into a perfectly cured state;
- (F) forming a conductor pattern layer on said polymer coating film by chemical plating; and
- repeating the steps (B)-(C)-(D)-(E)-(F) at least once.
Priority Claims (1)
Number |
Date |
Country |
Kind |
3-023106 |
Feb 1991 |
JPX |
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Parent Case Info
This application is a Divisional application of application Ser. No. 834,837, filed Feb. 13, 1992, now abandoned.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4673773 |
Nakano et al. |
Jun 1987 |
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4939039 |
Watanabe |
Jul 1990 |
|
5072075 |
Lee et al. |
Dec 1991 |
|
Non-Patent Literature Citations (1)
Entry |
IBM Technical Disclosure Bulletin "Multilayer Circuit Board Fabrication", vol. 10, No. 4, Sep. 1967. |
Divisions (1)
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Number |
Date |
Country |
Parent |
834837 |
Feb 1992 |
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