Patent Application
20130082332
The present disclosure relates to a method of fabricating semiconductor devices with metal gates and the resulting devices. The present disclosure is particularly applicable to fabricating semiconductor devices with NMOS and PMOS gates made from two different work function materials.
The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of lightly doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage (i.e., low off-state current) to reduce power consumption. Typically, the structural and doping parameters tending to provide a desired increase in drive current adversely impact leakage current.
Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high temperature annealing to activate the source/drain implants, as at a temperature in excess of 900° C. This fabrication technique may degrade the metal gate electrode or cause interaction with the gate dielectric, thereby adversely impacting transistor performance.
Replacement gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, a polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the polysilicon is removed and replaced with a metal gate. However, additional issues arise with forming replacement metal gates.
Historically, semiconductor manufacturers have used a single process to form n-type and p-type metal-oxide-semiconductor (N/PMOS) replacement gates at the same time. Because of the different work function control requirements for NMOS gates and PMOS gates, two different work function materials, one for NMOS gates and one for PMOS gates are needed. However, these two different materials within the same gate tend to interact with each other, making work function targeting difficult. Additionally, the process of forming NMOS work function material in the PMOS gate causes fill problems.
A need therefore exists for methodology enabling the fabrication of semiconductor devices including NMOS and PMOS gates made with different work function materials, made during separate and distinct processes and the resulting devices.
An aspect of the present disclosure is an efficient method of fabricating a semiconductor device with replacement metal gate electrodes having NMOS and PMOS gates made separately with different work function materials.
Another aspect of the present disclosure is a semiconductor device including NMOS and PMOS gates made with different work function materials.
Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
According to the present disclosure, some technical effects may be achieved in part by a method of fabricating a semiconductor device, the method including: forming a first removable gate and a second removable gate on a substrate; forming a first pair of spacers and a second pair of spacers on opposite sides of the first removable gate and the second removable gate, respectively; forming a hardmask layer over the second removable gate; removing the first removable gate, forming a first cavity between the first pair of spacers; forming a first work function material between the first pair of spacers; removing the hardmask layer and the second removable gate, forming a second cavity between the second pair of spacers; and forming a second work function material, different from the first work function material, in the second cavity.
Aspects of the present disclosure include forming the hardmask layer of polysilicon, amorphous silicon or a combination thereof. Further aspects include forming a first dielectric layer in the first cavity prior to forming the first work function material, and forming a second dielectric layer in the second cavity prior to forming the second work function material. Another aspect includes forming a first metal fill layer over the first work function material, and forming a second metal fill layer over the second work function material. Additional aspects include forming the hardmask layer over the second removable gate by: forming a hardmask material over the first and second removable gates, patterning a photoresist over the hardmask material with an opening over the first removable gate, and removing the hardmask material over the first removable gate through the opening; and removing the hardmask layer over the second removable gate by: patterning, after forming the first work function material, a mask with an opening over the second removable gate and the hardmask over the second removable gate, and removing the hardmask layer through the opening.
Another aspect of the present disclosure includes a method of fabricating a semiconductor device, the method including: forming two removable gates on a substrate, each having a pair of spacers on opposite sides thereof; removing the two removable gates, to form two gate trenches; forming a hardmask layer over the two gate trenches; removing the hardmask layer over a first gate trench of the two gate trenches; forming a first work function layer over the first gate trench; removing the hardmask layer over a second gate trench of the two gate trenches; forming a second work function layer, different from the first work function layer, over the second gate trench.
Aspects include forming the hardmask layer of polysilicon, amorphous silicon, or a combination thereof. Another aspect includes conformally forming a dielectric layer in the two gate trenches prior to depositing the hardmask layer. An additional aspect includes forming a capping layer over the dielectric layer prior to depositing the hardmask layer. Additional aspects include forming a threshold modulation layer over the dielectric material of the second gate trench, and forming a capping layer over the threshold modulation layer of the second gate trench prior to forming the second work function layer. Another aspect includes forming a seal layer over the capping layer prior to forming the second work function layer. Further aspects include forming a capping layer over the dielectric layer of the second gate trench after removing the hardmask layer over the second gate trench, and forming a seal layer over the capping layer. Another aspect includes filling a remainder of the first gate trench with a first metal fill layer subsequent to forming the first work function layer, and filling a remainder of the second gate trench with a second metal fill layer subsequent to forming the second work function layer.
Another aspect of the present disclosure is a semiconductor device including: a substrate; a p-type gate on the substrate, the p-type gate including a first work function layer; an n-type gate on the substrate, the n-type gate including a second work function layer different from the first work function layer; and spacers on opposite side surfaces of each of the p-type gate and the n-type gate.
Aspects include a dielectric layer under the first work function layer and under the second work function layer, for the p-type gate and the n-type gate, respectively. Another aspect includes a capping layer between the dielectric layer and each of the first and second work function layers, for the p-type gate and the n-type gate, respectively. Further aspects include an additional dielectric layer between the dielectric layer and the second work function layer for the n-type gate. Another aspect includes wherein the dielectric layer comprises hafnium oxide and the additional dielectric layer includes lanthanum oxide. An additional aspect includes a titanium nitride capping layer on the additional dielectric for the n-type gate. Another aspect includes a seal layer between the capping layer and the second work function layer for the n-type gate. Additional aspects include a first metal fill layer on the first work function layer, and a second metal fill layer on the second work function layer.
Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
The present disclosure addresses and solves the current problem of N-type metal-oxide-semiconductor equivalent oxide thickness caused by gate leakage (Toxgl), work function tuning problems caused by interactions between work function materials and gap fill problems associated with replacement metal gate processing. In accordance with embodiments of the present disclosure, NMOS and PMOS gates are formed separately allowing for better tuning of the respective work function materials and preventing PMOS gap fill issues. In addition, NMOS gates are formed with the addition of barrier or capping layers to improve NMOS Toxgl issues.
Methodology in accordance with embodiments of the present disclosure includes forming two removable gates on a substrate, each of the two removable gates having a pair of spacers on opposite sides. The two removable gates are removed from between the spacers to form two trenches, which are filled with a hardmask layer made of polysilicon and/or amorphous silicon. The trenches may be lined with a gate dielectric layer and a capping layer before they are filled with the hardmask layer. The hardmask layer is removed over one of the two trenches, for example the one corresponding to the PMOS gate. If a gate dielectric layer was not previously formed in the trenches, a gate dielectric layer is formed to line the sides and bottom of the exposed PMOS trench. Subsequently, a PMOS work function layer including, for example, titanium nitride (TiN), an optional barrier layer (e.g., TiN), and a seal (or wetting) layer of, for example, titanium, are sequentially formed in the trench, which is then filled with a metal fill of, for example, aluminum or tungsten.
The hardmask over the other trench is then removed. If a gate dielectric layer was not previously formed in the trench, a gate dielectric layer is formed to line the sides and bottom of the trench. This gate dielectric layer may be of the same material as the gate material discussed above, or may be a different gate material. Further, an additional gate dielectric layer may be formed above the first gate dielectric layer of a different material, for example lanthanum oxide. The additional gate dielectric layer may be added, for example, to help modulate the threshold voltage of the NMOS gate. A capping layer, for example TiN, and an additional seal (or wetting) layer of, for example, titanium are formed over the gate dielectric layer(s). Subsequently, a NMOS work function layer including, for example, titanium aluminide, an optional barrier layer (e.g., TiN) and a seal (or wetting) layer of, for example, titanium are sequentially formed on the seal (or wetting) layer followed by a metal fill of, for example, aluminum or tungsten. However, depending on the size of the gates, forming the work function layers to the desired thicknesses may completely fill the gates such that the addition of other layers, such as the metal layers, are unnecessary.
Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
Adverting to
As illustrated in
Next, a gate dielectric layer 301 is conformally formed over ILD 105 and in trenches 201a and 201b, lining both sides and the bottom of each trench. The gate dielectric layer 301 can be a high-k dielectric, for example having a dielectric constant of about 25 or greater, such as hafnium oxide, hafnium silicate, zirconium silicate, zirconium dioxide, silicon dioxide, etc. After a post deposition anneal, a first, thin metal layer (not shown for illustrative convenience) (e.g., titanium nitride (TiN)) may be deposited over the gate dielectric layer 301 as a capping layer. The capping layer may be formed to a thickness of around 20 Å (for example 5 Å to 50 Å). Gate dielectric layer 301 and any capping layer are removed from above ILD 105 by any conventional removal processing, such as polishing, e.g., chemical mechanical polishing (CMP). Thus, the result is a gate dielectric layer 301 and a thin metal layer (not shown for illustrative convenience) lining both sides and the bottom of each of trenches 201a and 201b, as illustrated in
Adverting to
The partial hardmask layer 501 may remain over the trench that will correspond to either the NMOS gate or the PMOS gate. For purposes of explanation, the partial hardmask layer 501 remains over the trench 201b corresponding to the NMOS gate with the trench 201a corresponding to the PMOS gate exposed.
As illustrated in
Subsequently, as illustrated in
The metal layer 701, the PMOS work function layer 601, and any seal layer and/or barrier layer, over trench 201b, are polished down to the level of the partial hardmask layer 501, as illustrated in
If no capping layer was previously formed over gate dielectric 301, a thin metal layer (not shown for illustrative convenience) (e.g., TiN) may be deposited over the gate dielectric layer 301 in trench 201b. Prior to depositing the thin metal layer, an additional gate dielectric layer (not shown for illustrative convenience) may be deposited over gate dielectric layer 301 in trench 201b. The additional gate dielectric layer can be a high-k dielectric, for example having a dielectric constant of about 25 or greater, such as hafnium oxide, hafnium silicate, zirconium silicate, zirconium dioxide, silicon dioxide, lanthanum oxide, etc. The additional gate dielectric layer may be added, for example, to help modulate the threshold voltage of the NMOS gate. Further, a seal (or wetting) layer (not shown for illustrative convenience) of, for example, titanium may be formed over the capping layer.
Next, as illustrated in
Subsequently, as illustrated in
In accordance with another exemplary embodiment, all layers of one gate may be formed prior to forming layers of the other gate, such that the PMOS gate and the NMOS gate are formed completely independently. For example, after removal of the removable gate electrodes 109 forming the two trenches 201a and 201b, as discussed above with respect to
Subsequently, as discussed above, a photo resist material (not shown for illustrative convenience) is patterned over hardmask layer 401 to enable the removal of the hardmask layer 401 from over one of the two trenches 201a and 201b (or alternatively to enable removal the hardmask layer 401 from over one of the two removable gate electrodes 109a and 109b as well as the exposed gate electrode, if the removable gate electrodes 109a and 109b were not previously removed). Upon removal of the hardmask layer 401 over one of the two trenches 201a and 201b, a partial hardmask layer 501 remains covering the other of the two trenches 201a and 201b (or alternatively covering the other of the two removable gate electrodes 109a and 109b). By way of example, the partial hardmask layer 501 remains covering the trench 201b (or alternatively the removable gate electrode 109b), which will be the NMOS gate, and is removed from the trench 201a (or alternatively from and with removable gate electrode 109a), which will be the PMOS gate, as illustrated in
A gate dielectric layer 301a is then conformally formed over ILD 105 and lining the sides and bottom of trench 201a, as illustrated in
Adverting to
A metal layer 701 is then deposited over the PMOS work function layer 601, as illustrated in
Subsequently, the partial hardmask layer 501 (or alternatively the partial hardmask 501 and the remaining removable gate electrode 109b, if the remaining removable gate electrode 109b was not removed prior to forming the hardmask layer 401) is removed via wet chemistry and/or a combination of dry and wet chemistries, as illustrated in
After removing the partial hardmask layer 501, a gate dielectric layer 301b is formed over ILD 105 and lining the sides and bottom of the trench 201b, as illustrated in
Adverting to
Next, a metal layer 1101 is deposited over the NMOS work function layer 1001, as illustrated in
In an alternative embodiment, the metal layer 1101, any NMOS seal layer and/or barrier layer, and the NMOS work function layer 1001, as well as the gate dielectric layer 301b, metal layer 701, any PMOS seal layer and/or barrier layer, PMOS work function layer 601, and gate dielectric layer 301a over trench 201a, are removed down to the height of the gate dielectric layers 301a and 301b directly above ILD 105. The resulting device includes gate dielectric layers 301a and 301b substantially coplanar above ILD 105, as illustrated in
The embodiments of the present disclosure can achieve several technical effects, such as the ability to separately tune the work functions of the NMOS and PMOS gates, improve NMOS gate leakage and reliability, and improve the metal fill issues in the trenches during formation of the NMOS and PMOS gates. The present disclosure enjoys utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices.
In the preceding description, the present disclosure is described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.
