Patent Application
20120017826
The present invention relates to a method for manufacturing a silicon carbide substrate.
An SiC (silicon carbide) substrate has recently increasingly been adopted as a semiconductor substrate used for manufacturing a semiconductor device. SiC has a band gap wider than Si (silicon) that has been used more commonly. Therefore, a semiconductor device including an SiC substrate is advantageous in a high breakdown voltage, a low ON resistance and less lowering in characteristics in an environment at a high temperature.
In order to efficiently manufacture a semiconductor device, a substrate is required to have a size not smaller than a certain size. According to U.S. Pat. No. 7,314,520 (Patent Literature 1), an SiC substrate not smaller than 76 mm (3 inches) can be manufactured.
PTL 1: U.S. Pat. No. 7,314,520
Industrially, the size of an SiC single crystal substrate is still limited to approximately 100 mm (4 inches). Accordingly, semiconductor devices cannot be efficiently manufactured using large single crystal substrates, disadvantageously. This disadvantage becomes particularly serious in the case of using the property of a plane other than the (0001) plane in SiC of hexagonal system. Hereinafter, this will be described.
An SiC single crystal substrate small in defect is usually manufactured by slicing an SiC ingot obtained by growth in the (0001) plane, which is less likely to cause stacking fault. Hence, a single crystal substrate having a plane orientation other than the (0001) plane is obtained by slicing the ingot not in parallel with its grown surface. This makes it difficult to sufficiently ensure the size of the single crystal substrate, or many portions in the ingot cannot be used effectively. For this reason, it is particularly difficult to effectively manufacture a semiconductor device that employs a plane other than the (0001) plane of SiC.
Instead of increasing the size of such an SiC single crystal substrate with difficulty, it is considered to use a silicon carbide substrate having a supporting portion and a plurality of small single crystal substrates connected thereon. The size of the silicon carbide substrate can be made larger by increasing the number of single crystal substrates as required. However, in the case where such a supporting portion and single crystal substrate are connected, the strength of the connection may be insufficient.
The present invention was made in view of the above-described problem, and an object of the present invention is to provide a method for manufacturing a silicon carbide substrate that can have the connecting strength between a single crystal substrate and a supporting portion increased.
A method for manufacturing a silicon carbide substrate of the present invention includes the following steps.
At least one single crystal substrate, each having a backside surface and made of silicon carbide, is prepared. A supporting portion having a main surface and made of silicon carbide is prepared. At least a portion of the main surface of the supporting portion has irregularities. The supporting portion and at least one single crystal substrate are stacked such that a backside surface of each at least one single crystal substrate and the main surface of the supporting portion having irregularities formed contact each other. In order to connect the backside surface of each at least one single crystal substrate to the connecting portion, the supporting portion and at least one single crystal substrate are heated such that the temperature of the supporting portion exceeds the sublimation temperature of silicon carbide, and the temperature of each at least one single crystal substrate is below the temperature of the supporting portion.
Since a cavity is ensured between the supporting portion and single crystal substrate by the irregularities of the supporting portion in the present invention, the temperature of the single crystal substrate can be set reliably lower that the temperature of the supporting portion. This allows the mass transfer from the supporting portion to the single crystal substrate associated with the sublimation recrystallization reaction to occur more reliably. Therefore, the connecting strength between the single crystal substrate and supporting portion can be increased.
Preferably, the step of preparing a supporting portion includes the steps of forming a main surface, and forming irregularities on the main surface. Therefore, formation of a main surface and the formation of irregularities can be carried out independently.
Preferably, the step of forming irregularities includes the step of grinding the surface so as to roughen the main surface. Preferably, the step of grinding the main surface includes the step of grinding the main surface in one linear direction.
Preferably, the step of forming irregularities includes the step of applying a predetermined surface feature to the main surface. Preferably, the surface feature includes a plurality of recesses extending on the main surface along a first direction. Preferably, the surface feature includes a recess extending on the main surface along a second direction crossing the first direction. Preferably, the surface feature includes a recess extending on the main surface in the circumferential direction.
In the step of preparing a supporting portion, a surface layer having a distortion in the crystal structure may be formed on the main surface. Preferably, before the step of stacking a supporting portion and at least one single crystal substrate, at least a portion of the surface layer is removed chemically.
Preferably, at least one single crystal substrate has a hexagonal crystal structure, and an off angle greater than or equal to 50° and less than or equal to 65° relative to the {0001} plane.
Preferably, the irregularities have a random direction. Accordingly, the anisotropy of the irregularities becomes smaller.
Preferably, the step of preparing a supporting portion includes the step of forming the main surface by slicing. Irregularities are formed by the slicing. Accordingly, the steps of manufacturing a silicon carbide substrate can be simplified since it is not necessary to carry out an independent step just for forming irregularities.
Preferably, the back surface of each at least one single crystal substrate is formed by slicing.
Preferably, a heating step is carried out in an atmosphere having pressure higher than 10−1 Pa and lower than 104 Pa.
As from the description set forth above, the connecting strength between the single crystal substrate and supporting portion can be increased according to the method for manufacturing a silicon carbide substrate of the present invention.
Embodiments of the present invention will be described hereinafter based on the drawings.
Referring to
Each of single crystal substrates 11-19 preferably has a hexagonal crystal structure, and more preferably an off angle greater than or equal to 50° and less than or equal to 65°, relative to the {0001} plane, and further preferably a plane orientation of {03-38}. As the plane orientation, {0001}, {11-20} or {1-100} can also be employed. Further, a plane offset by several degrees from each of the aforementioned plane orientation may also be used. Regarding various polytypes of the hexagonal system, the 4H polytype is particularly preferable. For example, each of single crystal substrates 11-19 has a plane configuration of 20×20 mm, a thickness of 300 μm, the 4H polytype, the plane orientation of {03-38}, an n type impurity concentration of 1×1019 cm−3, a micropipe density of 0.2 cm−2, and a stacking defect density less than 1 cm−1.
Supporting portion 30 may have the crystal structure of single crystal, polycrystal, and amorphous. Preferably, supporting portion 30 has a crystal structure similar to that of single crystal substrates 11-19. In general, the amount of defect in supporting portion 30 may be greater as compared to that of single crystal substrates 11-19. Therefore, the impurity concentration of supporting portion 30 can be readily increased as compared to the impurity concentration of single crystal substrates 11-19. For example, supporting portion 30 has a plane shape of 60×60 mm, a thickness of 300 μm, the 4H polytype, a plane orientation of {03-38}, an n impurity concentration of 1×1020 cm−3, a micropipe density of 1×104 cm−2, and a stacked defect density of 1×105 cm−1.
Preferably, the shortest distance between single crystal substrates 11-19 (for example, the horizontal distance between single crystal substrates 11 and 12 in
A method for manufacturing silicon carbide substrate 81 will be described hereinafter. Although only single crystal substrates 11 and 12 among single crystal substrates 11-19 may be mentioned for the sake of simplification in the following description, single crystal substrates 11-19 follow the description of single crystal substrates 11 and 12.
Referring to
Then, irregularities are formed at main surface FO. The irregularities can be formed by the step of grinding main surface FO so as to roughen main surface FO to a desired degree. This step can be carried out by rubbing main surface FO. This rubbing can be carried out by relative motion between a pad impregnated with slurry including abrasive grains and main surface FO, pressed against each other under a predetermined pressure. The size of the abrasive grains can be determined depending upon the degree of irregularities to be formed, and is 9 μm, for example. The substance of the crystal grains preferably has a hardness equal to or greater than that of SiC, and is diamond, for example. The aforementioned pressure is, for example, 0.1 to 0.2 kg/cm2. The aforementioned relative motion is a reciprocating movement of 1000 times across a length of approximately 30 cm along one linear direction.
Referring mainly to
A surface layer 71 having a distortion in the crystal structure may be formed on main surface FO due to the step of forming irregularities. Preferably by chemically removing at least a portion of surface layer 71, the amount of surface layer 71 is reduced, as shown in
Referring to
First heat body 91, single crystal substrate group 10, supporting portion 30c, and second heat body 92 are arranged so as to be stacked in the cited order. Specifically, single crystal substrates 11-19 (
The atmosphere in heat-insulating container 40 is obtained by reducing the atmospheric pressure. The pressure of the atmosphere is preferably set higher than 10−1 Pa and lower than 104 Pa.
The aforementioned atmosphere may be inert gas atmosphere. For inert gas, noble gas such as He or Ar, nitrogen gas, or mixed gas of the noble gas and nitrogen gas can be used, for example. The pressure in heat-insulating container 40 is preferably less than or equal to 50 kPa, more preferably less than or equal to 10 kPa.
Referring to
The mass transfer indicated by arrow M2 in
By the aforementioned regrowth, supporting portion 30c changes to a supporting portion 30 (
A method for manufacturing a silicon carbide substrate of a comparative example (
In contrast, the present embodiment readily allows temperature difference between supporting portion 30c and each of single crystal substrates 11 and 12 by virtue of cavity GQ therebetween due to supporting portion 30c (
When the backside surfaces of each single crystal substrate is formed by slicing, appropriate irregularities are provided on the backside surface, which also allows the formation of a cavity, likewise with cavity GQ. Therefore, the functional effect set forth above can be enhanced.
According to the present embodiment, surface layer 71 (
Preferably, each of single crystal substrates 11-19 has a crystal structure of the 4H polytype. Thus, a silicon carbide substrate 81 suitable for manufacturing a semiconductor directed to electric power use can be obtained.
Preferably, in order to prevent silicon carbide substrate 81 from cracking, the difference between the thermal expansion coefficient of supporting portion 30 and the thermal expansion coefficient of single crystal substrates 11-19 in silicon carbide substrate 81 is made as small as possible. Accordingly, occurrence of a warpage at silicon carbide substrate 81 can be suppressed. To this end, the crystal structure of supporting portion 30 is to be identical to that of single crystal substrates 11-19. Specifically, the crystal structure of supporting portion 30 is made to match that of single crystal substrates 11-19 by sufficient mass transfer (
Preferably, the electrical resistivity of supporting portion 30c (
The impurity concentration of supporting portion 30 of silicon carbide substrate 81 is greater than or equal to 5×1018 cm−3, more preferably greater than or equal to 1×1020 cm−3. By manufacturing a vertical type semiconductor device conducting a current flow in the vertical direction such as a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) employing such silicon carbide substrate 81, the on resistance of the vertical type semiconductor device can be reduced.
Preferably, the average value of the electrical resistivity of silicon carbide substrate 81 is preferably less than or equal to 5 mΩ·cm, more preferably less than or equal to 1 mΩ·cm.
Preferably, surface F1 (
Under the first condition, the angle between the off orientation of surface F1 and the <1-100> direction of single crystal substrate 11 is less than or equal to 5°. Further preferably, the off angle of surface F1 relative to the {03-38} plane in the <1-100> direction of single crystal substrate 11 is greater than or equal to −3° and less than or equal to 5°.
Under the second condition, the angle between the off orientation of surface F1 and the <11-20> direction of single crystal substrate 11 is less than or equal to 5°.
As used herein, “the off angle of surface F1 relative to the {03-38} plane in the <1-100> direction” refers to the angle between the orthogonal projection of the normal line of surface F1 on the projecting plane defined by the <1-100> direction and <0001> direction and the normal line of the {03-38} plane. The sign is positive when the aforementioned orthogonal projection approaches the <1-100> direction in parallel, and negative when the aforementioned orthogonal projection approaches the <0001> direction in parallel.
Although the above description is based on the preferable orientation for surface F1 of single crystal substrate 11, preferably the same applies to the orientation for each surface of other single crystal substrates 12-19 (
Although supporting portion 30 (
Although a resistance heating method using an electrical resistance heater for heater 50 is taken as an example, other heating methods can be employed. For example, the high-frequency induction heating or lamp annealing method may be employed.
In the present embodiment, a relative motion was carried out between a pad and main surface FO in one linear direction for the formation of irregularities. The direction of the relative motion may be in random. Accordingly, the direction of the irregularities will be random, allowing formation of irregularities with small anisotropy.
Referring to
A method for manufacturing silicon carbide substrate 81r will be described hereinafter. First, a substrate substantially similar to substrate 30b (
Referring to
Supporting portion 31a includes a plurality of recesses Ri (
Subsequently, steps similar to those set forth in the first embodiment are carried out, whereby silicon carbide substrate 81r (
The present embodiment provides advantages substantially similar to those of the first embodiment. Since a predetermined surface feature is applied to supporting portions 31a-31c, a more controllable cavity GQ (
A modification of the present embodiment will be described with reference to
According to the present modification, cavity GQ (
Another modification of the present embodiment will be described hereinafter with reference to
The present modification is advantageous in that application of anisotropy corresponding to a specific linear direction to the silicon carbide substrate can be avoided since the surface feature is not formed in a specific linear direction.
In a method for manufacturing a silicon carbide substrate according to the present embodiment with reference to
In the present embodiment, irregularities are formed on main surface FO in association with the formation of main surface FO (
In the present embodiment, a structure corresponding to supporting portion 30c (
According to the present embodiment, supporting portion 30c can be prepared through an extremely simple method of compacting SiC powder. Therefore, the steps of manufacturing a silicon carbide substrate 81 (
Referring to
Silicon carbide substrate 81 has an n type conductivity in the present embodiment, and includes supporting portion 30 and single crystal substrate 11, as described in the first embodiment. Drain electrode 112 is provided on supporting portion 30 such that supporting portion 30 is located between single crystal substrate 11 and drain electrode 112. Buffer layer 121 is provided on single crystal substrate 11 such that single crystal substrate 11 is located between supporting portion 30 and buffer layer 121.
Buffer layer 121 has an n type conductivity, and a thickness of 0.5 μm, for example. The concentration of the n type conductivity impurities in buffer layer 121 is 5×1017 cm−3, for example.
Breakdown voltage holding layer 122 is formed on buffer layer 121, and made of silicon carbide of n type conductivity. For example, breakdown voltage holding layer 122 has a thickness of 10 μm and an n type conductivity impurity concentration of 5×1015 cm−3.
At the surface of this breakdown voltage holding layer 122, a plurality of p regions 123 of p type conductivity are formed spaced apart from each other. In p region 123, n+ region 124 is formed at the surface layer of p region 123. At a region adjacent to this n+ region 124, p+ region 125 is formed. There is also an oxide film 126 formed extending from above n+ region 124 at one of p regions 123, over p region 123, a region of breakdown voltage holding layer 122 exposed between the two p regions 123, and the other p region 123, as far as above n+ region 124 at the relevant other p region 123. Gate electrode 110 is formed on oxide film 126. Source electrode 111 is formed on n+ region 124 and p+ region 125. Upper source electrode 127 is formed on source electrode 111.
The maximum value of the nitrogen atom concentration at the region within 10 nm from the boundary between oxide film 126 and the semiconductor layer, i.e. n+ region 124, p+ region 125, p region 123 and breakdown voltage holding layer 122, is greater than or equal to 1×1021 cm−3. Accordingly, the mobility at particularly the channel region under oxide film 126 (the portion of p region 123 in contact with oxide film 126, and located between n+ region 124 and breakdown voltage holding layer 122) can be improved.
A method for manufacturing semiconductor device 100 will be described hereinafter. Although the steps in the proximity of single crystal substrate 11 among single crystal substrates 11-19 (
At a substrate preparing step (step S110:
Referring to
First, buffer layer 121 is formed on single crystal substrate 11 of silicon carbide substrate 81. Buffer layer 121 is made of silicon carbide of n type conductivity, and is an epitaxial layer having a thickness of 0.5 μm, for example. Further, the concentration of the conductivity type impurities in buffer layer 121 is 5×1017 cm−3, for example.
Then, breakdown voltage holding layer 122 is formed on buffer layer 121. Specifically, a layer of silicon carbide of n type conductivity is produced by epitaxial growth. Breakdown voltage holding layer 122 is set to have a thickness of 10 μm, for example. Further, the concentration of the n type conductivity impurities in breakdown voltage holding layer 122 is 5×1015 cm−3, for example.
Referring to
First, p type conductivity impurities are selectively implanted to a portion of breakdown voltage holding layer 122 to form p region 123. Then, n type conductivity impurities are selectively implanted into a predetermined region to form n+ region 124. By selectively implanting p type conductivity impurities into a predetermined region, p+ region 125 is formed. Selective implantation of impurities is conducted using a mask composed of an oxide film, for example.
Following the implantation step, an activation annealing process is carried out. For example, annealing is carried out for 30 minutes at the heating temperature of 1700° C. in an argon atmosphere.
Referring to
Then, a nitrogen annealing step (step S150) is carried out. Specifically, annealing is carried out in a nitric oxide (NO) atmosphere. The conditions of this process include, for example, a heating temperature of 1100° C., and a heating duration of 120 minutes. As a result, nitrogen atoms are introduced in the vicinity of the boundary between oxide film 126 and each of breakdown voltage holding layer 122, p region 123, n+ region 124 and p+ region 125.
Subsequent to this annealing step employing nitric oxide, an annealing process employing argon (Ar) gas identified as inert gas may be further carried out. The conditions of this process include, for example, a heating temperature of 1100° C. and a heating duration of 60 minutes.
Referring to
First, a resist film having a pattern is formed on oxide film 126 by photolithography. Using this resist film as a mask, the portion of oxide film 126 located above n+ region 124 and p+ region 125 is removed by etching. Accordingly, an opening is formed in oxide film 126. Then, a conductor film is formed to be brought into contact with each of n+ region 124 and p+ region 125 at this opening. By removing the resist film, the portion of the aforementioned conductor film located on the resist film is removed (lift off). This conductive film may be a metal film, made of nickel (Ni), for example. As a result of this lift off, source electrode 111 is formed.
At this stage, a heat treatment is preferably carried out for alloying. For example, a heat treatment is carried out for 2 minutes at the heating temperature of 950° C. in the atmosphere of argon (Ar) gas identified as inert gas.
Referring to
A configuration in which the conductivity type is replaced in the present embodiment, i.e. a configuration in which the p type and n type are replaced, can be employed.
The silicon carbide substrate for producing semiconductor device 100 is not limited to silicon carbide substrate 81 of the first embodiment, and a silicon carbide substrate of any of the other embodiments may be employed.
Furthermore, although a vertical type DiMOSFET is taken as an example, another type of semiconductor device may be manufactured using the semiconductor substrate of the present invention. For example, a RESURF-JFET (Reduced Surface Field-Junction Field Effect Transistor), or a Schottky diode may be manufactured.
(Appendix 1)
The silicon carbide substrate of the present invention is produced by the manufacturing method summarized as below.
At least one single crystal substrate is prepared, each substrate having a backside surface and made of silicon carbide. A supporting portion having a main surface and made of silicon carbide is prepared. At least a portion of the main surface of the supporting portion has irregularities. The supporting portion and at least one single crystal substrate are stacked such that the backside surface of each at least one single crystal substrate and the main surface of the supporting portion having irregularities form contact each other. In order to connect the backside surface of each at least one single crystal substrate to the supporting portion, the supporting portion and at least one single crystal substrate are heated such that the temperature of the supporting portion exceeds the sublimation temperature of silicon carbide, and the temperature of each at least one single crystal substrate is below the temperature of the supporting portion.
(Appendix 2)
The semiconductor device of the present invention is produced using a semiconductor substrate produced by the manufacturing method summarized as below.
At least one single crystal substrate is prepared, each substrate having a backside surface and made of silicon carbide. A supporting portion having a main surface and made of silicon carbide is prepared. At least a portion of the main surface of the supporting portion has irregularities. The supporting portion and at least one single crystal substrate are stacked such that the backside surface of each at least one single crystal substrate and the main surface of the supporting portion having irregularities formed contact each other. In order to connect the backside surface of each at least one single crystal substrate to the supporting portion, the supporting portion and at least one single crystal substrate are heated such that the temperature of the supporting portion exceeds the sublimation temperature of silicon carbide, and the temperature of each at least one single crystal substrate is below the temperature of the supporting portion.
It should be understood that the embodiments disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the scope of the claims, rather than the description set forth above, and is intended to include any modification within the scope and meaning equivalent to the terms of the claims.
11-19 single crystal substrate; 30, 30c, 31, 31a-31e supporting portion; 81, 81r silicon carbide substrate; 91 first heat body; 92 second heat body; 100 semiconductor device.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010 045623 | Mar 2010 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2010/066829 | 9/28/2010 | WO | 00 | 9/21/2011 |
