Patent Application
20240162161
The present invention relates to the field of semiconductor packaging technologies, in particular to a method for preparing a dielectric layer on a surface of a wafer, a wafer structure, and a method for shaping a bump.
In a manufacturing process of a semiconductor device, almost every step of a photolithography technique relates to an alignment or aligning process. The so-called alignment or aligning process refers to recognition of a special alignment mark on a substrate surface by a machine on photolithographic equipment or by human eyes, so that there is an overlap in position between a latter technique and a former technique. For a wafer, misplacement caused by inaccurate alignment can result in distortion of a subsequent pattern or misalignment of registration, which ultimately affects an electrical characteristic of the semiconductor device in an adverse manner.
In the field of wafer packaging testing, since a surface of a wafer is usually distributed with a large number of IC circuit layers, a wafer packaging testing technique becomes particularly critical. At present, a height difference of IC circuit layers on surfaces of some wafers is too small, only about 0.1 μm; when a dielectric layer is processed in a packaging stage (such as PI covering), a circuit layer at the bottom cannot be displayed after the surface of the wafer is coated with a photoresist; and as a result, an alignment mark on the surface of the wafer is completely invisible after being covered with the photoresist, leading to failure of an exposure machine to subsequently recognize the alignment mark, and disabling continuous production. In this case, a packaging manufacturer has to return the wafer to an upstream wafer provider to re-make the alignment mark. Obviously, this will be very cumbersome, and thus, a packaging manufacturer cannot carry out continuous production, greatly reducing the production efficiency. It can be seen that how to enable the alignment mark on the surface of the wafer to be still visible after the dielectric layer is formed is a technical problem that needs to be solved.
A technical problem solved by the present application is to provide a method for preparing a dielectric layer on a surface of a wafer, so as to improve the problem of an unclear alignment mark in the prior art.
In order to solve the above technical problem, the present application provides a method for preparing a dielectric layer on a surface of a wafer, including:
Further, the UBM layer includes a chromium layer, a chromium-copper layer and a copper layer from bottom to top.
Further, the “removing the photoresist layer other than a target position” includes:
Further, the development technique is to dissolve the photoresist in a region other than the target position by using a chemical developer, so as to enable the metal layer under the photoresist to be exposed on the surface of the wafer.
A wafer structure includes: a substrate, a bonding pad formed on the substrate and a passivation layer, wherein the bonding pad is exposed outwardly from a passivation layer opening in the passivation layer; and
Further, the metal block is a UBM layer.
A method for shaping a bump includes:
Compared with the prior art, the present application optimizes the preparation technique of the dielectric layer of the wafer, in which the alignment mark is prepared in advance on the surface of the wafer before the dielectric layer is shaped on the surface of the wafer. Since the thickness of the alignment mark is 0.3 μm or more, the alignment mark is relatively prominent and easily visible, and can be effectively recognized and used for positioning in a subsequent technique of the wafer (such as a preparation stage of the dielectric layer), which is beneficial to the proceeding of the subsequent technique, effectively avoids the problem of reworking due to the invisible alignment mark in the preparation stage of the dielectric layer, ensures the continuity of the process technique, improves the production efficiency and also saves the labor and material costs of the reworking.
Reference numerals: 10—wafer, 101—bonding pad, 20—alignment mark, 30—metal layer, 40—photoresist layer, and 401—photoresist block.
Embodiments described below in combination with the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
Referring to
In S1, as shown in
In S2, an alignment mark 20 is formed on an upper surface of the wafer 10, wherein the alignment mark 20 is a metal block with a thickness of not less than 0.3 μm, and is only arranged on the passivation layer of the wafer 10, and no alignment mark 20 is formed on the bonding pad 101 of the wafer 10.
In S3, a dielectric layer is formed on the upper surface of the wafer where the alignment mark 20 is formed.
The “forming an alignment mark 20 on an upper surface of the wafer 10” includes the following steps.
In S21, as shown in
In S22, the metal layer other than a target position is removed to form a metal block, wherein the target position is a position where the alignment mark is located.
Specifically, the metal layer 30 is an under-bump metallization (UBM) layer shaped on the upper surface of the wafer. The UBM layer is deposited on the surface of the wafer 10 by a magnetron sputtering technique, and is generally a composite layer of a multi-layer structure. In the present embodiment, the UBM layer includes a chromium layer, a chromium-copper layer and a copper layer from bottom to top. In another embodiment, the UBM layer may also be a nickel-containing metal composite layer. The metal layer 30 may be a metal such as Ti, Cu, Au and Al.
The metal layer 30 covers the whole surface of the wafer 10, and the UBM layer enables a magnification effect on a protrusion or dent on the surface of the wafer 10 during actual use. Covering the upper surface of the wafer 10 with the UBM layer can enable an original protrusion on the upper surface of the wafer 10 to be more obvious. In this way, for the wafer 10 with the above protrusion, a more obvious contrast mark 20 can be obtained, so that an alignment role of the alignment mark 20 can be better played in the subsequent technological process.
In the prior art, the alignment mark is prone to be smoothed by the dielectric layer after being covered with the dielectric layer, that is, it is difficult to find the position of the alignment mark on the dielectric layer. Thus, a chip cannot be aligned in an operation after the dielectric layer is formed. In the present embodiment, a protrusion of the metal layer 30 is formed on the upper surface of the wafer 10, and is used as a new alignment mark 20, so that the alignment mark 20 can be clearly displayed after the wafer 10 is covered with the dielectric layer. Of course, in other embodiments, the alignment mark 20 may also be a dent disposed on the surface of the wafer 10. It should be noted that the height of the alignment mark 20 when it is a protrusion cannot be less than 0.3 μm, and similarly, when it is a dent, the depth of the alignment mark 20 is not less than 0.3 μm.
Specifically, in S22, “removing the metal layer other than a target position to form a metal block” includes the following steps.
In S221, as shown in
In S222, as shown in
In S223, as shown in
Specifically, the photoresist 30 at the target position can be removed by wet etching, so that the metal layer covered by the photoresist is exposed on the surface of the wafer 10. In this case, the surface of the wafer 10 is covered with the metal layer only at the target position, and the metal layer finally forms a metal bump, which protrudes from the surface of the wafer 10 and becomes the alignment mark on the surface of the wafer 10.
In “forming a dielectric layer on the surface of the wafer 10”, the dielectric layer may be a polyimide (PI) film.
Another embodiment of the present invention further discloses a wafer structure. As shown in
Another embodiment of the present invention further discloses a method for shaping a bump, including the following steps:
In summary, the present application optimizes the processing technique of the wafer 10, in which the alignment mark is prepared in advance on the surface of the wafer 10 before the dielectric layer is shaped on the surface of the wafer 10. Since the thickness of the alignment mark is not less than 0.3 μm, the alignment mark is relatively prominent and easily visible after being covered with the dielectric layer, and can be effectively recognized for positioning in a subsequent technique of the wafer 10 (such as a preparation stage of the dielectric layer), which is beneficial to the proceeding of the subsequent technique, effectively avoids the problem of reworking due to the invisible alignment mark in the preparation stage of the dielectric layer, ensures the continuity of the process technique, improves the production efficiency and also saves the labor and material costs of the reworking.
The structure, features and effects of the present invention have been described in detail according to the embodiments shown in the drawings. The above are only preferred embodiments of the present invention, but the scope of implementations of the present invention is not limited by the drawings. Any changes made according to the concept of the present invention or equivalent embodiments modified to equivalent changes that do not go beyond the spirit covered by the Description and drawings should be within the scope of protection of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202110735094.7 | Jun 2021 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/132274 | 11/23/2021 | WO |
