The present invention relates to a method for producing a PCM memory element and to a corresponding PCM memory element.
U.S. Pat. No. 5,166,758 discloses a PCM (phase change memory) memory element in the case of which electrical energy is used for converting a PCM material, typically chalcogenide alloys (e.g. Ge2Sb2Te5), between the crystalline phase (high conductivity, logic “1”) and the amorphous phase (low conductivity, logic “0”).
The conversion from the amorphous phase into the crystalline phase requires a thermal pulse with a temperature which is higher than the glass transition temperature but lower than the melting point, whereas the conversion from the crystalline phase into the amorphous phase requires a thermal pulse with a temperature greater than the melting point followed by rapid cooling.
In the case of the above example of Ge2Sb2Te5, the melting point is 600° C. and the glass transition temperature is 300° C. The crystallization time is typically 50 ns.
A further PCM (phase change memory) memory element having a particular contact structure is disclosed in WO 00/57498 A1, a contact being formed from a sidewall spacer.
PCM memory elements of this type have a whole series of advantageous properties, for example nonvolatility, direct overwritability, nondestructive readability, rapid writing/erasing/reading, long service life (1012 to 1013 read/write cycles), high packing density, low power consumption and good integrability with standard semiconductor processes. In particular, the previously known concepts of SRAM, EEPROM and ROM can be combined in a PCM memory element.
One of the main problems with the known PCM memory elements is the relatively high heat generation during the programming and erasing operations. These problems are suitably remedied by reducing the contact-connected electrode area to increase the current density and consequently lower the energy consumption and the associated heat generation.
IEDM 200136,05, Stefan Lai and Tyler Lowrey, “OUM—A 180 nm Nonvolatile Memory Cell Element Technology For Stand Alone and Embedded Applications” provides a summary of the current state of development of PCM memory elements (also referred to there as “OUM” (Ovonic Unified Memory) memories) in 180 nm technology.
It is therefore an object of the present invention to provide a method for producing a PCM memory element and a corresponding PCM memory element which enable a further reduction of the size and hence of the heat generation during operation.
This problem is solved according to the invention by means of the production method specified in claim 1 and by means of the PCM memory element specified in claim 11.
The idea on which the present invention is based consists in the application of a sublithographic process for reducing the size of the contact area of the PCM memory element. In particular, the invention provides a liner mask technique for the configuration of the top electrode.
Advantageous developments and improvements of the respective subject matter of the invention may be found in the subclaims.
In accordance with one preferred development, the first and second conducting line devices are parallel strips.
In accordance with a further preferred development, two segments of the mask strip are provided, the two segments having an interspace in the center of the hole, so that they each lie only above one strip-type resistance element.
In accordance with a further preferred development, the strip-type resistance elements are provided at the wall of the hole by the following steps of: providing a filling made of the resistance material in the hole; etching back the filling; providing a circumferential spacer (25) in the hole above the etched-back filling; etching the filling using the spacer as a mask; removing the spacer; and photolithographically patterning the etched filling to form the strip-type resistance elements.
In accordance with a further preferred development, the strip-type resistance elements are provided at the wall of the hole by the following steps of: providing a liner layer made of the resistance material in the hole and on the surrounding surface of the insulation material; carrying out a spacer etch for the purpose of removing the liner layer from the bottom of the hole and from the surrounding surface of the insulation material; and photolithographically patterning the etched liner layer to form the strip-type resistance elements.
In accordance with a further preferred development, the strip-type resistance elements and the filling made of the insulation material are etched back in the hole, the layer made of the PCM material being provided as a cover in the hole.
In accordance with a further preferred development, the strip-type resistance elements are etched back by a first depth and the filling made of the insulation material is etched back by a second depth, which is smaller than the first depth, in the hole, the layer made of the PCM material being provided as a circumferential spacer above the strip-type resistance elements in the hole.
In accordance with a further preferred development, the sublithographic mask strips are formed by the following steps of: providing an auxiliary layer on the conductive layer; photolithographically patterning the auxiliary layer to form blocks whose edges define the mask strips; providing a liner layer made of the spacer material; carrying out a spacer etch of the liner layer for the purpose of forming the mask strips; and removing the auxiliary layer.
In accordance with a further preferred development, the top electrodes are electrically connected to the further conducting line device by the following steps of: providing a liner layer and an insulation layer above the structure; providing one or two contact plugs for making contact with the top electrodes in the liner layer and the insulation layer; and providing an interconnect on the insulation layer for making contact with the one or the two contact plugs.
In accordance with a further preferred development, a plurality of pairs of first and second conducting line devices are provided and a plurality of holes are concomitantly provided per pair in the insulation layer, which uncover the first and second conducting line devices in sections in each case.
Exemplary embodiments of the invention are illustrated in the drawings and explained in more detail in the description below.
a, b to 10a, bshow schematic illustrations of successive method stages of a method for producing a PCM memory element as first embodiment of the present invention, to be precise in each case in plan view perspective and cross section perspective;
a, b show schematic illustrations of a method for producing a PCM memory element as second embodiment of the present invention, to be precise one in plan view perspective and one in cross section perspective;
a, b to 13a, b show schematic illustrations of a method for producing a PCM memory element as third embodiment of the present invention, to be precise in each case in plan view perspective and cross section perspective; and
a, b to 18a, b show schematic illustrations of a method for producing a PCM memory element as fourth embodiment of the present invention, to be precise in each case in plan view perspective and cross section perspective.
In the figures, identical reference symbols designate identical or functionally identical component parts. The cross-sectional plane is always the same and is indicated by the letters A-A′ in
a, b to 10a, b show schematic illustrations of successive method stages of a method for producing a PCM memory element as first embodiment of the present invention, to be precise in each case in plan view perspective and cross section perspective.
In
Reference symbols 5a, 5b designate two rectangular holes which are provided alongside one another in the insulation layer 10 and partly uncover the metal interconnects Ma, Mb running parallel in each of the holes 5a, 5b, as illustrated in
In a subsequent process step, which is illustrated in
In the next process step, a spacer layer made of silicon nitride or TEOS with a thickness of typically 40 nm is deposited above the entire structure and from this spacers 25 having a width of typically 30 nm are formed in the upper region of the holes 5a, 5b by means of a spacer etching process. The spacers run along the entire inner upper circumference of the holes 5a, 5b, as is clearly discernible in
This is followed, referring to
Referring further to
After the resistance material filling 20 has been severed, which is expediently likewise realized by means of a reactive ion etching step, the bottom electrodes of in each case two PCM memory cells in the same hole 5a or 5b, respectively, have been completed.
The photoresist mask is then removed from the surface of the insulation layer 10. In the subsequent process step, TEOS insulation material is deposited above the resulting structure and polished back, with the result that an insulation material filling 30 remains in the holes 5a, 5b. During the polishing-back process, which is effected by means of a CMP step, a section of the surface of the insulation layer 10 which, in accordance with
A subsequent process step involves sinking the remaining halves of the resistance material filling 20 in the holes 5a, 5b, and likewise sinking the insulation material filling 30 by the same depth. A PCM material, here Ge2Sb2Ti5, is then deposited, for example by sputtering, above the resulting structure and is polished back in a further CMP step, which leads to the state shown in
This is followed, referring to
As illustrated in
The patterning is effected perpendicular to the direction in which the metal strips Ma, Mb run, and in such a way that approximately half of the holes 5a, 5b is covered. In a further process step, a liner layer made of TEOS is then deposited above the patterned auxiliary layer 45 and subjected to a spacer etch, so that spacer strips run above the holes 5a, 5b essentially perpendicular to the metal interconnects 5a, 5b. This process step has the significant advantage that it creates sublithographic spacer strips 50, the size of which can be made significantly smaller than the lithographic resolution. The thickness of the TEOS layer is usually 40 nm.
Referring further to
In a subsequent etching process, the spacer strips 50 are then cut open using the photoresist mask 55 and remain only beneath the photoresist mask 55. This is followed, referring to
Finally, the segments of the spacer strips 50 are removed selectively in a further etching step, which leads to the structure shown in
a, 10b illustrate the concluding process steps for making contact with the strips of the layer 40 which function as top electrode. In a customary manner, a silicon nitride liner layer 60 with a thickness of approximately 30 nm is deposited as an etching stop above the layer and a further insulation layer 75 is subsequently provided above that. Contact plugs 70 are formed in the insulation layer 75 by means of a customary contact hole 10 technique. Finally, metallic connection strips 80 are provided above the resulting structure for the purpose of connecting the contact plugs 70, which leads to the structure shown in
The small volume of the PCM layer 35 which is converted between the phases crystalline/amorphous during operation is specially highlighted by “x” in
a, b show schematic illustrations of a method for producing a PCM memory element as second embodiment of the present invention, to be precise one in plan view perspective and one in cross section perspective.
In the case of the second embodiment shown in
a, b to 13a, b show schematic illustrations of a method for producing a PCM memory element as third embodiment of the present invention, to be precise in each case in plan view perspective and cross section perspective.
In the case of the third embodiment, the halves of the resistance material filling 20 which serve as bottom electrodes are produced in a different way. In particular, this embodiment proceeds from the state in accordance with
Referring further to
a, b to 18a, b show schematic illustrations of a method for producing a PCM memory element as fourth embodiment of the present invention, to be precise in each case in plan view perspective and cross section perspective.
In the case of the fourth embodiment, the initial state is the state shown in
A subsequent process step involves firstly etching back the resistance material filling 20″ by a first depth and etching back the insulation material filling 30 by a second depth, which is smaller than the first depth. Afterward, a PCM layer 35 is deposited above the resulting structure and subjected to a spacer etch, which leads to the process state shown in
Referring further to
As already explained thoroughly in connection with
Likewise as already explained, a photoresist mask 55 is then formed on the resulting structure and the spacer strips 50 are thereby subdivided into segments. Removal of the photoresist mask 55 is followed by etching of the layer 40 and the underlying PCM layer 35 using the spacer strip segments as a mask. Removal of the spacer strip segments 50 yields the structure shown in
In the case of this fourth embodiment, too, the volume of the PCM layer 35 which contributes to the phase change is very small, so that there is only an extremely low energy requirement for the phase conversion.
The type of contact-connection of the strips 40 of the top electrodes that is shown in
Although the present invention has been described above on the basis of a preferred exemplary embodiment, it is not restricted thereto, but rather can be modified in diverse ways.
In particular, the selection of the layer materials and filling materials is only by way of example and can be varied in many different ways.
Although the PCM memory element has been provided between two adjacent metal planes in the case of the above embodiments, the present invention is not restricted thereto, and the PCM memory elements according to the invention can generally be arranged between arbitrary conductive layers, for example between the substrate and an overlying metal plane.
Moreover, the conducting line devices may be embodied not only as interconnects but e.g. also as diffusion zones or the like.
List of Reference Symbols
Number | Date | Country | Kind |
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102004015899.1 | Mar 2004 | DE | national |
This application is a continuation of PCT International Patent Application No. PCT/EP2005/003069, filed Mar. 22, 2005, which claims priority to German Patent Application No. 102004015899.1, filed Mar. 31, 2004, the disclosures of each of which are incorporated herein by reference in their entitety.
Number | Date | Country | |
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Parent | PCT/EP05/03069 | Mar 2005 | US |
Child | 11522225 | Sep 2006 | US |