Patent Application
20080099537
This invention generally relates to substrate manufacturing processes, and more particularly, to a method for hermetically sealing one or more vias in a substrate.
Electronic circuitry including one or more components may be disposed on a generally flat substrate. The substrate provides a support structure for the electronic circuitry and may include one or more electrically conductive paths for the flow of electricity from one component to another. Vias having holes may also be formed in these substrates to provide an electrical connection from an upper surface to a lower surface of the substrate. The vias may also provide structural connection of the substrate to a carrier, such as a heat sink or other device having a surface for mounting the substrate.
According to one embodiment of the invention, a method for sealing one or more vias comprises providing a first substrate having vias, forming an adhesion layer on an inner surface of the vias, sandwiching a solder layer between the first substrate and a second substrate, and elevating of the first substrate, second substrate, and solder layer to a temperature above a eutectic point and below a melting point of the solder layer. The act of elevating the solder layer to a temperature above the eutectic point and below the melting point causes the solder layer to flow into the vias in a generally consistent manner.
According to another embodiment of the present invention, a method for sealing vias comprises the acts of providing a first substrate having the vias, forming an adhesion layer on an inner surface of the vias, and sandwiching a solder layer between the first substrate and a second substrate. The first substrate, solder layer, and second substrate are then elevated to a temperature and pressure, the pressure being operable to urge the first substrate toward the second substrate such that the solder layer flows into the vias in a generally consistent manner.
Some embodiments of the present invention may provide numerous technical advantages. A technical advantage of one embodiment may include the addition of a second substrate, such as a heat sink or ground plane to the lower surface of the first substrate using a relatively inexpensive manufacturing process. Certain embodiments of the present invention may also provide a method for sealing vias that alleviates the need for relatively expensive conventional via sealing systems. One embodiment of the present invention provides a via sealing method that may use conventionally available solder materials and be processed using readily available equipment, such as an autoclave. The autoclave is a type of equipment that is adapted to provide an ambient environment having an elevated pressure and an elevated temperature. The autoclave may be utilized to provide an elevated pressure and temperature for sealing vias in a substrate in a cost effective manner.
An additional advantage is presented whereby multiple substrates may be adhered together using the method according to the present invention. In one embodiment, the method may be administered multiple times in order to adhere multiple substrates on top of one another in a stacking fashion. In another embodiment, multiple substrates may be simultaneously adhered together by stacking multiple substrates on top of one another with a solder layer sandwiched between each of the adjoining substrates.
While specific advantages have been disclosed hereinabove, it will be understood that various embodiments may include all, some, or none of the disclosed advantages. Additionally, other technical advantages not specifically cited may become apparent to one of ordinary skill in the art following review of the ensuing drawings and their associated detailed description.
A more complete understanding of embodiments of the invention will be apparent from the detailed description taken in conjunction with the accompanying drawings in which:
a through 1d are side elevation, cross-sectional views of a semiconductor structure showing the results of a sequence of acts that may be performed to implement one embodiment according to the present invention;
a through 3c are side elevation, cross-sectional views showing various fill levels of solder within a via following an act of elevating the temperature associated with
a and 5b are side elevation, cross-sectional views of an alternative embodiment showing the results of a sequence of acts in which a solder layer that is formed into a pattern may be used to fill vias and adhere the second substrate to the first substrate;
a and 6b are side elevation, cross-sectional views of another alternative embodiment showing the results of a sequence of acts in which a solder layer that is formed into a pattern may be used to fill vias and release the second substrate from the first substrate;
a through 7c are side elevation, cross-sectional views of a semiconductor substrate showing the results of a sequence of acts that may be performed to create bumps on the semiconductor substrate; and
a and 8b are a plan view and side elevation view respectively of an alternative embodiment of a semiconductor substrate having differing sized vias that that may be filled as described above with regard to
In the following description, reference is made to the accompanying drawings that illustrate several embodiments of the present invention. It is to be understood that other embodiments may be utilized and structural and operational changes may be made without departing from the spirit and scope of the present invention.
a through 1d are cross-sectional drawings shown during various phases of manufacture of a semiconductor device showing one embodiment of a sequence of actions that may be performed to hermetically seal vias 12. The method for sealing vias 12 generally comprises a number of acts, the results of which are shown in
The solder layer 14 may comprise any suitable material that exhibits a phase change at a predetermined temperature and provides adequate adhesive properties to the adhesion layer 13. In one embodiment, the solder layer 14 may comprise a solder alloy comprising two or more elements with at least one of the elements being metallic. In such a case, one of the elements may have a melting point that is lower than the other element such that the solder alloy may possess a eutectic point below the melting point of the solder alloy. Therefore, the elevated temperature may be a predetermined temperature that is above the eutectic point and below the melting point of the solder alloy. The solder alloy may be considered to be partially molten when the temperature is above the eutectic point and below the melting point of the solder alloy. In this manner, the consistency of the partially molten solder alloy may be allowed to flow into the vias 12 using the force applied to the substrates 11 and 15. In one embodiment, the solder alloy may comprise a gold-tin alloy. In another embodiment, the solder alloy may comprise other solder alloys such as gold-silicon, gold-germanium, copper-tin, or palladium-silicon.
In order to urge the partially molten solder layer 14 into the vias 12, a force may be applied to substrates 11 and 15. There are several approaches for applying this force. In one embodiment, gravity is the force. In another embodiment, the force may be applied by a mechanical structure that urges substrate 11 toward substrate 15. In another embodiment, the force may be applied by elevating the pressure of the environment surrounding the substrates 11 and 15. In one embodiment, the elevated temperature and pressure may be applied simultaneously such that the elevated pressure urges the substrate 15 toward the substrate 11. In another embodiment, the elevated temperature and pressure may be supplied by an autoclave.
The substrate 15 may be coupled to the substrate 11 or be released from the substrate 11 following elevating of the temperature. In cases where the substrate 15 is formed of a material that is adapted to adhere to the solder layer following the act of elevating the temperature, the substrate 15 may be formed of a material that exhibits good surface tension or wetting properties to the molten or partially molten solder layer 14. In such a case, the substrate 15 may have a thermal expansion coefficient that is essentially similar to the thermal expansion coefficient of substrate 11. In one embodiment, the substrate 15 may be electrically conductive in order to form a ground plane for electrical circuitry on substrate 11. In addition, the substrate 15 may be thermally conductive such that heat may be conveyed away from substrate 11, thereby functioning as a heat sink. In another embodiment, substrate 15 may have one or more electrical circuits formed thereon. In such a case, the solder layer 14 may be operable to provide electrical connection of one or more electrical nodes on substrate 11 to one or more electrical nodes on substrate 15.
The substrate 15 alternatively may be formed of a material having relatively poor surface tension or wetting properties in relation to the solder layer 14. In this manner, substrate 15 may be removed from substrate 11 following elevating the temperature. In such a case, the thermal expansion coefficient of substrate 15 relative to substrate 11 is irrelevant. In one embodiment, substrate 15 may be fashioned of a relatively flexible material in order to allow bending away from substrate 11 using a peeling type action. Certain embodiments of the present invention may exhibit advantages provided by usage of a flexible substrate 15 in conjunction with the application of an elevated pressure in that the pressure may serve to evenly distribute the compression forces between substrates 11 and 15.
As described above, the adhesion layer 13 may be deposited within the vias 12 for providing adequate surface tension of the vias 12 to the solder layer 14. In this manner, the partially molten solder alloy 14 may be further urged into the vias 12 using the surface tension force of the adhesion layer 13 to the solder layer 14. If substrate 11 is conductive in nature, the vias 12 may be coated with an insulating or dielectric material using conventional thermal oxidation or chemical vapor deposition (CVD) techniques prior to application of the adhesion layer 13. However, deposition of a dielectric material may not be needed if substrate 11 is inherently insulative in nature. In one embodiment, the adhesion layer 13 may be formed of a Titanium-Tungsten alloy and the solder layer 14 may be made of a gold-tin alloy. In another embodiment, adhesion layer 13 may be formed from other metals or metallic alloys, such as Tin, Chromium, Tin-Nitrate alloy, or Tantalum-Nitrate alloy.
In another embodiment, the method 10 of the present invention may be performed an additional number of times as described above with regard to
a through 3c shows several vias 212 having varied fill levels such as a fully filled, an overfilled, or an under filled via that may be filled as described above with regard to
In some instances, it may be desirable to create a hermetically sealed via 212 having a particular fill level. The teachings of the present invention provide several methods of modifying the effective fill level of the vias 212. In one embodiment, the fill level of the via 212 may be modified by various physical abrasion techniques, such as lapping, polishing, wet etching, dry etching, or sanding. For example, a via 212 that is overfilled may have the overfilled portion of the solder material removed by conventional polishing, wet etching, or dry etching of the protruding solder portion. In another example, if the solder material is relatively difficult to remove, the method for sealing vias 10 may be administered on a relatively thick substrate 211. Then following completion of elevating the temperature, the upper surface 222 may be lapped down until the via 212 has a fully filled fill level. In another embodiment, the fill level of the via 212 may be further manipulated by application of a surface tension modifying agent to the adhesion layer 213. The surface tension modifying agent may comprise a relatively thin dielectric coating that serves to retard or enhance the surface tension of the solder layer 214 to the adhesion layer 213. The dielectric coating may be evenly applied over the substrate 211 or may be applied to selective regions of the substrate 211. The dielectric coating may be deposited using conventional approaches, such as, for example chemical vapor deposition (CVD) or atomic layer deposition (ALD). In another embodiment, the via 212 may have a pad 223 (
The previously described method 10 for hermetically sealing vias in a substrate may have numerous useful applications. For example, vias formed in a micro electro-mechanical system (MEMS) 300 circuit may be hermetically sealed using the above described method 10.
Certain embodiments of the present invention may provide the ability to selectively modify the thickness of substrate 311 using known thinning processes, such as lapping or polishing. That is, the method of hermetically sealing vias 10 may provide sufficient structural integrity in order to provide for lapping or polishing of substrate 311 to a relatively thin layer. In one embodiment, substrate 311 may be thinned to any desired thickness. In another embodiment, substrate 311 may be thinned to an overall thickness of approximately 50 microns.
Other useful embodiments may employ the method for hermetically sealing vias 10 of the present invention.
In another embodiment, the method for hermetically sealing vias 10 in a substrate may be used to facilitate the forming of projections or bumps on the substrate.
a and 8b show how the teachings of the present invention may be used to fill vias 712 of differing size. The substrate 711 as shown has several vias 712a and 712b that are disposed in spaced relation to one another. Vias 712a and 712b are structured in such a manner to form what is commonly known as a “faraday cage”. It should be understood however, that any suitable combination of vias 712 having differing sizes may be hermetically sealed using the teachings of the present invention.
As shown in this particular example, via 712a has a size that is larger than the size of the other vias 712b. Via 712a has been sealed in a manner similar to that described above in conjunction with
While specific advantages have been disclosed hereinabove, it will be understood that various embodiments may include all, some, or none of the disclosed advantages. Additionally, other technical advantages not specifically cited may become apparent to one of ordinary skill in the art following review of the ensuing drawings and their associated detailed description.
