Claims
- 1. The method of forming gaps within metal lines in the fabrication of an integrated circuit wherein current density of said integrated circuit is lower than the current density of an integrated circuit having no gaps within said lines comprising:
- etching openings to form gaps within said metal lines where said metal lines bend wherein said gaps act to split the flow of said high current so that said flow is uniform through the width of said metal lines thereby reducing said current density at the critical region where said metal lines bend; and
- filling said gaps formed at the region where said metal lines bend with silicon dioxide wherein voids are formed within said silicon dioxide and wherein said voids act to reduce system stress.
- 2. The method of forming gaps metal lines in the fabrication of an integrated circuit comprising:
- etching openings to form gaps within said metal lines where said metal lines bend wherein said gaps act to split the flow of said current, thereby reducing said current density at the region where said metal lines bend; and
- filling said gaps formed at the region where said metal lines bend with an insulating material wherein voids are formed within said insulating material and wherein said voids act to reduce stress.
- 3. The method of claim 2, wherein the insulating material is an oxide of silicon.
- 4. The method of claim 3, wherein the insulating material is silicon dioxide.
- 5. The method of claim 3, wherein the metal lines are wider than the metal lines are tall.
Parent Case Info
This application is a division of application Ser. No. 08/241,005 filed on May 11, 1994, now U.S Pat. No. 5,464,794.
US Referenced Citations (4)
Foreign Referenced Citations (2)
Number |
Date |
Country |
223968 |
May 1987 |
EPX |
63-232447 |
Sep 1988 |
JPX |
Non-Patent Literature Citations (1)
Entry |
S. Wolf "Silicon Processing for the VLSI Era, vol. 2.", Lattice Press, 1990, pp. 273-275. |
Divisions (1)
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Number |
Date |
Country |
Parent |
241005 |
May 1994 |
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