1. Field
This disclosure relates generally to non-volatile memory (NVM) manufacturing, and more specifically, to the making split gate NVM cells.
2. Related Art
Non-volatile memories (NVMs) have become very significant in the semiconductor industry and thus the manner of making them has also become very significant. The cost of making the NVM is accordingly kept as low as possible while achieving the needed performance. Ways of achieving this normally includes using techniques that can be implemented with commonly available equipment and using materials that are well characterized. An effective approach for achieving the desired performance has been found to be the use of split gate NVM cells which utilize a select gate and a control gate over a continuous channel.
Accordingly there is a need to provide further improvement in achieving both low cost and high performance for split gate NVM cells.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
In one aspect, a split gate NVM cell is formed using replacement gate for both the select gate and the control gate. The material of the dummy select gate is chosen so that the dummy control gate and other exposed materials are not appreciably etched during the etch, which is performed without requiring photolithographic mask, of the dummy select gate. The dummy select gate is then replaced with a metal select gate. The material of the dummy control gate is chosen so that the metal select gate and the other exposed materials are not appreciably etched during the etch, which is performed without requiring photolithographic mask, of the dummy control gate. The dummy control gate is then replaced with a material that results in the control gate used in the final split gate NVM cell. This is better understood by the drawings and the following written description.
The semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.
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As shown, an effective use of existing materials and corresponding equipment and reduced requirement for masking steps results in an efficient manufacturing process for split gate NVMs.
By now it is apparent there has been disclosed a method of making a semiconductor structure using a substrate, wherein the semiconductor structure comprises a split gate non-volatile memory (NVM) structure in an NVM region of the semiconductor structure. The method includes forming a dummy select gate structure including a first material on the substrate. The method further includes forming a dummy control gate structure including a second material on the substrate, wherein the first material is different from the second material. The method further includes replacing the dummy select gate structure with a metal select gate structure, wherein the replacing the dummy select gate structure includes removing the dummy select gate structure without removing the dummy control gate structure and replacing the dummy control gate structure with a polysilicon control gate structure and the replacing the dummy control gate structure includes removing the dummy control gate structure without removing the metal select gate structure. The method may have a further characterization by which the replacing the dummy select gate structure includes etching the first material included in the dummy select gate structure using an etchant to leave an opening, wherein the etchant substantially removes the first material and the etchant does not substantially remove the second material included in the dummy control gate structure. The method may have a further characterization by which the replacing the dummy select gate structure further includes forming a metal gate stack in the opening to form the metal select gate structure. The method may have a further characterization by which the replacing the dummy control gate structure includes etching the second material included in the dummy control gate structure using an etchant to leave an opening, wherein the etchant substantially removes the second material and the etchant does not substantially remove the third material included in the metal select gate structure. The method may have a further characterization by which the third material forms a capping layer on the metal select gate structure. The method may have a further characterization by which the replacing the dummy control gate structure further includes forming a polysilicon gate stack in the opening to form the polysilicon control gate structure. The method may have a further characterization by which the forming the dummy select gate structure and the forming the dummy control gate structure includes forming a charge storage layer over the substrate including over a first portion of the first material and along a side of the first portion, forming a second layer of the second material over the charge storage layer, and etching the second layer and the charge storage layer to form the dummy select gate structure and the dummy control gate structure. The method may further include, prior to the replacing the dummy select gate structure and the replacing the dummy control gate structure, forming an interlayer dielectric (ILD) layer over the substrate including over the dummy select gate structure and the dummy control gate structure and performing chemical mechanical polishing on the NVM region to reveal a top first surface of the first material and a second top surface of the second material. The method may have a further characterization by which an etchant utilized in one of the replacing the dummy select gate structure and the replacing the dummy control gate structure does not substantially remove oxide and an interlayer dielectric (ILD) material. The method may have a further characterization by which the dummy control gate structure is a spacer structure.
Disclosed also is a method of making a split gate non-volatile memory (NVM) structure using a semiconductor substrate. The method includes etching a first dummy material included in a dummy select gate stack formed on the semiconductor substrate to form a first opening, wherein the etching the first dummy material does not substantially remove a second dummy material included in a dummy control gate stack formed on the semiconductor substrate and the first dummy material is different from the second dummy material. The method further includes forming a metal select gate stack in the first op. The method further includes etching the second dummy material to form a second opening, wherein the etching the second dummy material does not substantially remove a third material included in the metal select gate stack. The method further includes forming a polysilicon control gate stack in the second opening. The method may further include forming the dummy select gate stack and the dummy control gate stack including etching a first layer of the first dummy material formed over the semiconductor substrate to form at least a first side of the dummy select gate stack, forming a charge storage layer over the semiconductor substrate including along the first side of the dummy select gate stack, forming a second layer of the second dummy material over the charge storage layer, and etching the second layer and the charge storage layer to form the dummy control gate stack and a second side of the dummy select gate stack. The method may have a further characterization by which the etching the second layer and the charge storage layer further includes etching the first layer to form the second side of the dummy select gate stack. The method may further include, prior to the etching the first layer and the etching the second layer and the charge storage layer, forming an interlayer dielectric (ILD) layer over the semiconductor substrate including over the dummy select gate stack and the dummy control gate stack. The method may further include, prior to the etching the first layer and the etching the second layer and the charge storage layer, performing chemical mechanical polishing on the semiconductor substrate to reveal a first top surface of the first dummy material included in the dummy select gate stack and a second top surface of the second dummy material included in the dummy control gate stack. The method may have a further characterization by which the chemical mechanical polishing removes an upper portion of the dummy select gate stack and of the dummy control gate stack. The method may further include forming sidewall spacers along the second side of the dummy select gate stack and a third side of the dummy control gate stack. The method may have a further characterization by which the etching the second layer and the charge storage layer includes performing a spacer etch on the second layer to form the dummy control gate stack, wherein, the dummy control gate stack is a spacer structure. The method may have a further characterization by which the third material forms a capping layer on the metal select gate stack.
Also disclosed is a method for making a non-volatile memory (NVM) structure using a semiconductor substrate. The method includes forming a select gate structure including a first dummy material on the semiconductor substrate. The method further includes forming a control gate structure including a second dummy material on the semiconductor substrate, wherein the first dummy material is different from the second dummy material. The method further includes replacing the first dummy material with metal. The method further includes replacing the second dummy material with polysilicon.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, materials used for dummy select gates, dummy control gates, and for the select gates can be varied with the corresponding effect that different etchants may be used. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
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