Patent Application
20180040531
The present invention relates to a method of making an interconnect substrate and, more particularly, to a method of making an interconnect substrate having a routing circuitry connected to posts and terminals.
Semiconductor chip is susceptible to performance degradation at high operating temperatures. Hence, encapsulating a chip in a molding compound without proper heat dissipation can worsen thermal environment and cause immediate failure during operation. QFN (“Quad Flat No-Lead”) packages that allow a chip disposed on a metal paddle of a lead frame aims to resolve this thermal-related deficiency. U.S. Pat. Nos. 7,102,214, 7,723,163, and 7,790,512 and U.S. Patent Application No. 20080174981 disclosed various QFN packages for such purposes. However, as lead frames are typically formed by etching of a metal sheet, they are unable to provide ultra-fine line routing circuitry needed by many high performance devices.
Further, many power module or light emitting diode (LED) applications require a highly thermally conductive, electrically insulative and low CTE (Coefficient of Thermal Expansion) board for signal transmission. U.S. Pat. Nos. 8,895,998 and 7,670,872 disclosed various interconnect structures using ceramics for such purposes. However, as the ceramic material is brittle and tends to crack during handling, making this type of circuit board prohibitively unreliable for practical usage.
A primary objective of the present invention is to provide an interconnect substrate having a routing circuitry disposed on a dielectric compound and electrically coupled to a plurality of post/terminal connecting elements. The routing circuitry disposed on the dielectric compound provides horizontal routing to improve electrical characteristics of the semiconductor assembly, whereas the post/terminal connecting elements offer vertical interconnections between two opposite sides of the interconnect substrate.
Another objective of the present invention is to provide an interconnect substrate optionally having a low-CTE and high thermal conductivity isolator incorporated therein so as to resolve the chip/board CTE mismatch problem, thereby improving the mechanical reliability and thermal characteristics of the semiconductor assembly.
In accordance with the foregoing and other objectives, the present invention provides a method of making an interconnect substrate having routing circuitry connected to posts and terminals, the method comprising steps of: providing a metal plate having a base and a plurality of posts, wherein the posts contact and project from a top side of the base; providing a dielectric compound on the top side of the base, wherein the dielectric compound covers sidewalls of the posts and has a top surface substantially coplanar with top sides of the posts; forming a top routing circuitry on the top surface of the dielectric compound and electrically coupled to the posts; and selectively removing portions of the base to form a paddle and a plurality of terminals in contact with the posts, wherein the paddle and the terminals extend laterally from the posts in lateral directions and each have a larger lateral dimension than that of the posts.
In another aspect, the present invention provides a method of making an interconnect substrate having an isolator, the method comprising steps of: providing a metal plate having a base and a plurality of posts, wherein the posts contact and project from a top side of the base, and the base has a through opening that extends from the top side to a bottom side of the base; inserting an isolator into the through opening of the base, with a top surface of the isolator substantially coplanar with top sides of the posts, wherein the isolator includes a thermally conductive and electrically insulating slug; providing a dielectric compound on the top side of the base, wherein the dielectric compound covers sidewalls of the isolator and the posts and has a top surface substantially coplanar with the top sides of the posts and the top surface of the isolator; forming a top routing circuitry on the top surface of the dielectric compound and electrically coupled to the posts; and selectively removing portions of the base to form a plurality of terminals in contact with the posts, wherein the terminals extend laterally from the posts in lateral directions and each have a larger lateral dimension than that of the posts.
Unless specifically indicated or using the term “then” between steps, or steps necessarily occurring in a certain order, the sequence of the above-mentioned steps is not limited to that set forth above and may be changed or reordered according to desired design.
The method of making the interconnect substrate according to the present invention have numerous advantages. For instance, depositing the dielectric compound to the post/base metal plate can provide a platform for high resolution circuitries disposed thereon, thereby enhancing routing capability of the interconnect substrate. Binding the isolator to the post/terminal connecting elements provides a CTE-compensated platform for the attachment of a semiconductor device and also establishes a heat dissipation pathway for spreading out the heat generated by the semiconductor device.
These and other features and advantages of the present invention will be further described and more readily apparent from the detailed description of the preferred embodiments which follows.
The following detailed description of the preferred embodiments of the present invention can best be understood when read in conjunction with the following drawings, in which:
Hereafter, examples will be provided to illustrate the embodiments of the present invention. Advantages and effects of the invention will become more apparent from the following description of the present invention. It should be noted that these accompanying figures are simplified and illustrative. The quantity, shape and size of components shown in the figures may be modified according to practical conditions, and the arrangement of components may be more complex. Other various aspects also may be practiced or applied in the invention, and various modifications and variations can be made without departing from the spirit of the invention based on various concepts and applications.
The dielectric compound 30 mainly includes an organic resin binder and particulate inorganic fillers. In this embodiment, the organic resin binder has a coefficient of thermal expansion more than 20 ppm/° C., whereas the particulate inorganic fillers have a coefficient of thermal expansion less than 10 ppm/° C. Further, the content of the particulate inorganic fillers in the dielectric compound 30 preferably ranges from 30 to 90 weight percent based on the total weight of the dielectric compound 30. As a result, the dielectric compound 30 has a coefficient of thermal expansion which is compatible to that of the metal plate 10 so as to prevent cracking or delamination caused by CTE mismatch.
Following the deposition of the seeding layer, an electrically conductive layer (typically a copper layer) is deposited on the seeding layer. The electrically conductive layer can be made of Cu, Ni, Ti, Au, Ag, Al, their combinations, or other suitable electrically conductive material. Once the desired thickness is achieved, the electrically conductive layer as well as the seeding layer can be patterned to form the top routing circuitry 40 by numerous techniques such as wet etching, electro-chemical etching, laser-assist etching, or their combinations, with an etch masks (not shown) thereon that define the top routing circuitry 40. In this embodiment, the top routing circuitry 40 includes a top thermal pad 41 in contact with the first posts 12 to provide a thermal platform for device attachment and top conductive traces 43 electrically coupled to the second posts 13.
Accordingly, as shown in
For purposes of brevity, any description in Embodiment 1 above is incorporated herein insofar as the same is applicable, and the same description need not be repeated.
The interconnect substrate 500 is similar to that illustrated in
The interconnect substrate 600 is similar to that illustrated in
The interconnect substrate 700 is similar to that illustrated in
As illustrated in the aforementioned embodiments, a distinctive interconnect substrate is configured to exhibit improved reliability and have a dielectric compound bonded with a plurality of post/terminal connecting elements and a top routing circuitry. The interconnect substrate mainly includes a plurality of posts, a plurality of terminals, a dielectric compound, and a top routing circuitry. In a preferred embodiment, the terminals are located below the posts and the dielectric compound and patterned from a base that is integral with the posts and extends laterally from the posts in lateral directions to peripheral edges of the dielectric compound; the posts are embedded in the dielectric compound and serve as vertical connecting channels; the dielectric compound provides a planar dielectric platform surrounding the posts for the top routing circuitry deposited thereon; and the top routing circuitry provides electrical contacts on the top surface of the dielectric compound for device connection.
Additionally, the interconnect substrate may further include an isolator incorporated with the post/terminal connecting elements by the dielectric compound. The isolator can provide a platform for device attachment and preferably has top and bottom surfaces not covered by the dielectric compound and substantially coplanar with the top sides of the posts and the bottom sides of the terminals, respectively. Specifically, the isolator includes a thermally conductive and electrically insulating slug that may be made of ceramic, silicon, glass or others and typically has high elastic modulus and low coefficient of thermal expansion (for example, 2×10−6 K−1 to 10×10−6 K−1). As a result, the isolator, having CTE matching a semiconductor device to be assembled thereon, provides a CTE-compensated platform for the semiconductor device, and thus internal stresses caused by CTE mismatch can be largely compensated or reduced. Further, the isolator also provides primary heat conduction for the semiconductor device so that the heat generated by the semiconductor device can be conducted away.
The post/terminal connecting elements can be formed by selectively removing portions of a post/base metal plate after bonding the dielectric compound to the post/base metal plate. The post/base metal plate can be a selectively etched single-piece metal or a stamped single-piece metal. Alternatively, the post/base metal plate may be formed by depositing the posts on the top side of the base using metal deposition techniques. Further, the post/base metal plate may be formed with a through opening in the base for isolator disposition. Preferably, the thickness of the isolator is substantially equal to the combined thickness of the posts and the terminals. Additionally, by selective removal of the base, a paddle may be formed on the bottom surface of the dielectric compound and in contact with at least one of the posts to provide a larger thermal dissipation surface area than the post. For instance, in a preferred embodiment, the base is patterned to form a paddle in contact with at least one first post as a heat pipe and terminals in contact with second posts as vertical routing. Accordingly, the posts can provide electrical connection or heat conduction pathway between two opposite sides of the dielectric compound, whereas the terminals can serve as electrical contacts on the bottom surface of the dielectric compound.
The dielectric compound can be a resin-based layer and bonded to the top side of the base and sidewalls of the posts and the optional isolator by paste printing, compressive molding, transfer molding, liquid injection molding, spin coating, or other suitable methods. In the interconnect substrate having no isolator incorporated therein, the dielectric compound preferably has a uniform thickness substantially equal to that of the posts. As for the alternative interconnect substrate having the isolator incorporated therein, the dielectric compound preferably further fills in a gap between the isolator and interior sidewalls of the through opening and has a larger thickness where it contacts the isolator than where it contacts the posts. In any case, the dielectric compound preferably has a planar top surface substantially coplanar with the top sides of all the posts and the top surface of the optional isolator. In a preferred embodiment, for CTE match between the dielectric compound and the post/terminal connecting elements, the dielectric compound preferably includes particulate inorganic fillers of CTE less than 10 ppm/C blended therein. The content of the particulate inorganic fillers in the dielectric compound may range from 30 to 90 weight percent based on the total weight of the dielectric compound. As a result, cracking or delamination due to CTE mismatch can be suppressed. Further, the top surface of the dielectric compound preferably has an arithmetic mean roughness (Ra) in a range of 0.1 to 2 micrometer to improve adhesion of the top routing circuitry on the dielectric compound and prevent peeling of the top routing circuitry from the dielectric compound.
The top routing circuitry can be deposited before or after selective removal of the base, and provides electrical contacts on the top surface of the dielectric compound for device connection. Typically, the top routing circuitry is thinner than the paddle and the terminals, and contacts and is electrically coupled to the top sides of the posts without metallized vias in contact with the posts. Optionally, the top routing circuitry may include a top thermal pad for device attachment. The top thermal pad preferably is aligned with and thermally conductible to the paddle by at least one of the posts. Additionally, for the interconnect substrate having the isolator incorporated therein, the top routing circuitry may further extend onto the top surface of the isolator. As a result, the top routing circuitry can provide electrical contacts on the top surface of the isolator to allow a semiconductor device to be flip-chip attached on the isolator, or provide a top thermal pad on the top surface of the isolator for a semiconductor device face-up mounted thereon. The top routing circuitry can be formed by metal deposition using photolithographic process. Preferably, the top routing circuitry is deposited by a sputtering process and then an electrolytic plating process. In order to promote adhesion between the top routing circuitry and the dielectric compound, the top routing circuitry preferably includes a seeding layer that contains a titanium film, a titanium tungsten film or the like in contact with the top surface of the dielectric compound.
Optionally, a balance layer may be further provided on the bottom surface of the dielectric compound to cover sidewalls of the terminals and the paddle and laterally extend to peripheral edges of the interconnect substrate. In a preferred embodiment, the balance layer has a uniform thickness substantially equal to that of the terminals and an exterior surface substantially coplanar with bottom sides of the terminals. The balance layer can be a resin-based layer and bonded to the bottom surface of the dielectric compound as well as sidewalls of the terminals and the paddle by paste printing, compressive molding, transfer molding, liquid injection molding, spin coating, or other suitable methods. The material of the balance layer may be the same as or different from the dielectric compound. For instance, the balance layer may include particulate inorganic fillers of CTE less than 10 ppm/C blended therein. The content of the particulate inorganic fillers in the balance layer preferably ranges from 30 to 90 weight percent based on the total weight of the balance layer. Further, the exterior surface of the balance layer may have an arithmetic mean roughness (Ra) in a range of 0.1 to 2 micrometer to improve adhesion of an optional bottom routing circuitry on the exterior surface of the balance layer and prevent peeling of the optional bottom routing circuitry from the balance layer. After provision of the balance layer, a cavity can be optionally formed by selectively or entirely removing the paddle and aligned with at least one of the posts.
Further, a bottom routing circuitry can be optionally deposited on the exterior surface of the balance layer and electrically connected to the top routing circuitry on the top surface of the dielectric compound by the posts in the dielectric compound and the terminals in the balance layer. Accordingly, the double routing circuitries can enhance routing flexibility of the interconnect substrate. Typically, the bottom routing circuitry is thinner than the paddle and the terminals, and contacts and is electrically coupled to the bottom sides of the terminals without metallized vias in contact with the terminals. Optionally, the bottom routing circuitry may include a bottom thermal pad in contact with the paddle. Additionally, for the interconnect substrate having the isolator incorporated therein, the bottom routing circuitry may further extend onto the bottom surface of the isolator. As a result, the bottom routing circuitry can provide electrical contacts on the bottom surface of the isolator, or provide a bottom thermal pad on the bottom surface of the isolator. The bottom routing circuitry can be formed by metal deposition using photolithographic process. Preferably, the bottom routing circuitry is deposited by a sputtering process and then an electrolytic plating process. In order to promote adhesion between the bottom routing circuitry and the balance layer, the bottom routing circuitry may include a seeding layer that contains a titanium film, a titanium tungsten film or the like in contact with the exterior surface of the balance layer.
The term “cover” refers to incomplete or complete coverage in a vertical and/or lateral direction. For instance, in a preferred embodiment, the balance layer covers sidewalls of the isolator regardless of whether another element such as the dielectric compound is between the isolator and the balance layer.
The phrases “mounted on” and “attached on” include contact and non-contact with a single or multiple support element(s). For instance, in a preferred embodiment, the semiconductor device is attached on the isolator regardless of whether the semiconductor device is separated from the isolator by the top routing circuitry and conductive bumps.
The phrase “aligned with” refers to relative position between elements regardless of whether elements are spaced from or adjacent to one another or one element is inserted into and extends into the other element. For instance, in a preferred embodiment, the interior sidewalls of the base are laterally aligned with the peripheral edges of the isolator since an imaginary horizontal line intersects the interior sidewalls of the base and the peripheral edges of the isolator, regardless of whether another element is between the interior sidewalls of the base and the peripheral edges of the isolator and is intersected by the line, and regardless of whether another imaginary horizontal line intersects the peripheral edges of the isolator but not the interior sidewalls of the base or intersects the interior sidewalls of the base but not the peripheral edges of the isolator. Likewise, in a preferred embodiment, at least one of the posts is aligned with the bottom of the cavity formed by selectively or completely removing the paddle.
The phrase “in close proximity to” refers to a gap between elements not being wider than the maximum acceptable limit. As known in the art, when the gap between the peripheral edges of the isolator and the interior sidewalls of the base is not narrow enough, the isolator may not be accurately confined at a predetermined location. The maximum acceptable limit for a gap between the peripheral edges of the isolator and the interior sidewalls of the base can be determined depending on how accurately it is desired to dispose the isolator at the predetermined location. Thereby, the description “ the peripheral edges of the isolator in close proximity to the interior sidewalls of the through opening” means that the gap between the peripheral edges of the isolator and the interior sidewalls of the through opening is narrow enough to prevent the location error of the isolator from exceeding the maximum acceptable error limit. For instance, the gaps in between the peripheral edges of the isolator and the interior sidewalls of the through opening may be in a range of about 25 to 100 microns.
The phrases “electrical connection”, “electrically connected” and “electrically coupled” refer to direct and indirect electrical connection. For instance, in a preferred embodiment, the terminals are electrically connected to the top routing circuitry by the posts but are spaced from and do not contact the top routing circuitry.
The interconnect substrate according to the present invention has numerous advantages. The post/terminal connecting elements provide primary horizontal and vertical routing, and the top routing circuitry offers further routing to increase routing flexibility of the interconnect substrate.
The interconnect substrate made by this method is reliable, inexpensive and well-suited for high volume manufacture. The manufacturing process is highly versatile and permits a wide variety of mature electrical and mechanical connection technologies to be used in a unique and improved manner. The manufacturing process can also be performed without expensive tooling. As a result, the manufacturing process significantly enhances throughput, yield, performance and cost effectiveness compared to conventional techniques.
The embodiments described herein are exemplary and may simplify or omit elements or steps well-known to those skilled in the art to prevent obscuring the present invention. Likewise, the drawings may omit duplicative or unnecessary elements and reference labels to improve clarity.
This application is a continuation-in-part of U.S. application Ser. No. 15/642,253 filed Jul. 5, 2017, a continuation-in-part of U.S. application Ser. No. 15/642,256 filed Jul. 5, 2017. The U.S. application Ser. No. 15/642,253 is a continuation-in-part of U.S. application Ser. No. 14/621,332 filed Feb. 12, 2015 and continuation-in-part of U.S. application Ser. No. 14/846,987 filed Sep. 7, 2015. The U.S. application Ser. No. 14/846,987 is a continuation-in-part of U.S. application Ser. No. 14/621,332 filed Feb. 12, 2015. The U.S. application Ser. No. 14/621,332 claims benefit of U.S. Provisional Application Ser. No. 61/949,652 filed Mar. 7, 2014. The entirety of each of said Applications is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61949652 | Mar 2014 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15642253 | Jul 2017 | US |
| Child | 15785426 | US | |
| Parent | 15642256 | Jul 2017 | US |
| Child | 15642253 | US | |
| Parent | 14621332 | Feb 2015 | US |
| Child | 15642253 | US | |
| Parent | 14846987 | Sep 2015 | US |
| Child | 14621332 | US | |
| Parent | 14621332 | Feb 2015 | US |
| Child | 14846987 | US |
