This application is the U.S. national phase of PCT Application No. PCT/CN2013/089646 filed on Dec. 17, 2013, which claims priority to Chinese Patent Application No. 201310275057.8 filed on Jul. 2, 2013, the disclosures of which are incorporated in their entirety by reference herein.
The present invention relates to the field of a display technique, in particular to a 3D barrier substrate, the method of manufacturing the same, and a display device.
In the prior art, the method of manufacturing a 3D barrier substrate comprises the steps as follows.
Referred to
Referred to
Referred to
The above-described method of manufacturing a 3D barrier substrate may ensure that the ring shape signal line metal electrode 11 charges the stripe shape ITO transparent electrode 31 respectively, and the design requirements for a 3D barrier substrate are met
To sum up, in the prior art, the method of manufacturing a 3D barrier substrate need to perform a photo etching process for three times and adopts a three-layer structure comprising a signal line metal layer, a passivation layer, and an ITO transparent conducting layer, and each of which need to design a mask respectively, so many procedures decreases the production efficiency and increases the cost of production.
An embodiment according to the present invention provides a 3D barrier substrate, a method of manufacturing the same, and a display device to improve the utilization of facilities, increase the production efficiency, and decrease the cost of production.
An embodiment according to the present invention provides a method of manufacturing a 3D barrier substrate comprising:
forming a transparent electrode thin film on a substrate, and forming a passivation layer on the transparent electrode thin film;
forming an transparent electrode and a passivation layer via hole by a patterning process, wherein the via hole is used for coupling the transparent electrode to a signal line; and
forming the signal line, wherein the signal line is coupled to the transparent electrode through the via hole.
An embodiment according to the present invention provides a 3D barrier substrate comprising: a substrate, a transparent electrode on the substrate, a passivation layer on the transparent electrode layer, and a signal line on the passivation layer, wherein the signal line is coupled to the transparent electrode through a via hole on the passivation layer.
An embodiment according to the present invention provides a display device comprising the above-described 3D barrier substrate.
To sum up, among the technical solutions provided by the embodiments of the present invention, the method of manufacturing a 3D barrier substrate comprises: forming a transparent electrode thin film on a substrate, and forming a passivation layer on the transparent electrode thin film; forming an transparent electrode and a passivation layer via hole by a patterning process, wherein the via hole is used for coupling the transparent electrode to the signal line; and forming a signal line, wherein the signal line couples to the transparent electrode through the via hole. The method provided by the embodiment of the present invention adopts two times patterning process, decreases the cost of producing the mask, reduces one time exposure process, shortens the process procedure, improves the utilization of facilities, increases the production efficiency, and decreases the cost of production
An embodiment of the present invention provides a 3D barrier substrate and a method of manufacturing the same, and a display device to improve the utilization of facilities, increases the production efficiency, and decrease the cost of production
The details of the technical solutions provided by the embodiments of present invention are described as follows.
Referred to
S101: forming a transparent electrode thin film on a substrate, and forming a passivation layer on the transparent electrode thin film;
S102: forming a transparent electrode and a passivation layer via hole by a patterning process, and the via hole being used to couple the transparent electrode to a signal line;
It is appreciated that the patterning process may comprise a part or all processes of masking, exposing, developing, photo-etching, etching and so on which are required to form a pattern, and may also comprise ashing and annealing and so on.
For example, forming a pattern of a gate electrode on the substrate by a patterning process comprises: firstly, depositing a gate electrode layer on the substrate; then coating the photo-resist, and exposing and developing the photo-resist using a mask so as to form a photo-resist pattern; then, removing a corresponding electrode layer by etching process and so on by using the photo-resist pattern as an etching mask, and removing the residual photo-resist; and finally forming the gate electrode pattern on the substrate.
S103: forming the signal line which is coupled to the transparent electrode through a via hole.
Preferably, the patterning process comprises: a part or all processes of a photo etching process of coating a photo-resist on the passivation layer and then exposing and developing, a etching process after photo-etching, and a process of removing the photo-resist after etching.
Preferably, when a transparent electrode and a passivation layer via hole are formed by the patterning process, after exposing and developing the photo-resist coated on the passivation layer by a halftone technique, the photo-resist layer coated on the passivation layer comprises: a first photo-resist layer which coats a region where the transparent electrode is to be formed, a second photo-resist layer which coats a region where the via hole is to be formed, the via hole is used to couple the transparent electrode to the signal line, and the thickness of the first photo-resist layer is larger than that of the second photo-resist layer.
Preferably, the process of forming the via hole comprises: etching the passivation layer which is not coated by the photo-resist, removing the second photo-resist layer, forming the transparent electrode by etching the revealed transparent electrode layer, and forming the via hole by etching the passivation layer that is formerly coated by the second photo-resist layer.
Preferably, the thickness of the first photo-resist layer is in the range of 1.5-3 μm, and the thickness of the second photo-resist layer is in the range of 0.5-1 μm.
Preferably, when removing the second photo-resist layer, the photo-resist having the thickness of 0.5-1 μm is removed from the first photo-resist layer.
Preferably, the second photo-resist layer is removed by an ashing process.
Preferably, the process of forming the transparent electrode by etching the revealed transparent electrode layer comprises: performing over-etching when the revealed transparent electrode layer is etched, and the transparent electrode formed after over-etching has an indentation with a size of 0.5-2 μm relative to the passivation layer coating the transparent electrode so that the signal line may be only coupled to the transparent electrode through the via hole.
Preferably, the process of forming the signal line comprises: depositing a signal line metal layer, coating a third photo-resist layer on the signal line metal layer, and forming a pattern which is required by the signal line on the third photo-resist layer by exposing and developing, etching the signal line metal layer which is not coated by the third photo-resist layer, and forming the signal line by removing the third photo-resist layer.
The embodiments will be described in detail.
As shown in
The detail of forming the transparent electrode and the passivation layer via hole by a patterning process is described as follows.
As shown in
As shown in
As shown in
As shown in
Preferably, over-etching is required during the etching process. After over-etching, the ITO layer 31 has an indentation region 80 with a size of 0.5-2 μm relative to the passivation layer 21 coating the ITO layer 31 so that the ITO layer 31 and the metal layer are not electrically connected when depositing the metal layer subsequently.
As shown in
As shown in
Then, the signal line metal layer 11 which has a thickness about 2000-5000 Å is deposited by sputtering, wherein the signal line metal layer 11 may also be deposited by other methods such as electron beam evaporation and so on.
The signal line is formed by the second patterning process, and the signal line may be only coupled to the transparent electrode through the via hole. Certainly, the second patterning process may be not exactly the same as the preceding pattering process. For example, the detail of the second patterning process may be described as following.
As shown in
As shown in
An embodiment of the present invention provides a 3D barrier substrate comprising: a substrate, a transparent electrode on the substrate, a passivation layer on the transparent electrode layer, and a signal line on the passivation layer, wherein the signal line is coupled to the transparent electrode through the via hole on the passivation layer.
Preferably, the transparent electrode, which is revealed at the position of the via hole on the passivation layer, is in the display area of the substrate.
Preferably, the transparent electrodes are alternately arranged transparent electrodes.
Preferably, the signal line is a ring shape signal line, and the transparent electrode is a strip shape transparent electrode.
Preferably, the transparent electrode is an Indium Tin Oxide transparent electrode.
An embodiment of the present invention provides a display device comprising the 3D barrier substrate, wherein the display device may be a liquid crystal display (LCD) or a naked-eye 3D display.
To sum up, among the technical solutions provided by the embodiments of the present invention, the method of manufacturing a 3D barrier substrate comprises: forming a transparent electrode thin film on a substrate, and forming a passivation layer on the transparent electrode thin film; forming an transparent electrode and a passivation layer via hole by a patterning process, wherein the via hole is used for coupling the transparent electrode to the signal line; and forming a signal line, wherein the signal line couples to the transparent electrode through the via hole. The method provided by the embodiment of the present invention adopts two times patterning process, decreases the cost of producing the mask, reduces one time exposure process, shortens the process procedure, improves the utilization of facilities, increases the production efficiency, and decreases the cost of production.
It should be noted that, those of ordinary skills in the art may further make improvements and modifications without departing from the principle of the present invention, and these improvements and modifications shall also be considered as the scope of the present invention.
Number | Date | Country | Kind |
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2013 1 0275057 | Jul 2013 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN2013/089646 | 12/17/2013 | WO | 00 |
Publishing Document | Publishing Date | Country | Kind |
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WO2015/000272 | 1/8/2015 | WO | A |
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Second Office Action for corresponding Chinese Application No. CN 201310275057.8; dated Mar. 25, 2015; 6 pages. |
Second Office Action for corresponding Chinese Application No. CN 201310275057.8; dated Mar. 25, 2015; 3 pages—[English Translation]. |
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Chinese First Office Action Dated Oct. 16, 2014, Application No. 201310275057.8, Applicant BOE Technology Group Co., Ltd; Beijing BOE Display Technology Co., Ltd., 6 Pages. |
Number | Date | Country | |
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20150194660 A1 | Jul 2015 | US |