This application priority to French Patent Application No. 1873209, flied on Dec. 18, 2018, the entire contents of which are incorporated herein by reference.
The invention relates to field effect transistors, and in particular to methods for fabricating such transistors that are compatible with three-dimensional integration methods.
To decrease the cost of integrated circuits and to increase their performance, manufacturers are constantly decreasing the size of transistors, increasing the number thereof per chip, and increasing the number of circuits produced in parallel. To allow this increase in the performance of integrated circuits, technologists are consequently geometrically decreasing the size of the transistors in the active portion, along with the size of the interconnections. However, decreasing the technology node below 10 nm is problematic.
With a view to increasing integration density and/or decreasing the distance between electronic components, it is known practice to carry out 3D integration by superposing a second active layer of electronic components over the interconnect layer of a first active layer produced beforehand.
In three-dimensional integration methods, any heating step in the formation of a second active layer over the intermediate interconnect layer comes with a high risk of damaging the first active layer.
Doped source and drain formation generally requires dopant activation and the diffusion of these dopants at temperatures exceeding 1000° C. Such temperatures cannot be applied in the formation of the second active layer without damaging the first active layer.
A fabrication method has been proposed for decreasing the temperatures applied to activate dopants in a source or drain. According to such a method, a layer of crystalline silicon that is not intentionally doped is provided beforehand and arranged on top of a buried dielectric layer. A gate stack is formed on top of the layer of crystalline silicon. Spacers made of dielectric material are formed on either side of the gate stack. The upper portion of the silicon layer on either side of the assembly including the gate stack and the spacers is then amorphized. The amorphization method is carried out by means of ion bombardment. Next, dopants are introduced by ion implantation into the amorphous silicon. A step of solid-phase recrystallization is then carried out at a temperature below 600° C. for the purpose of recrystallizing the silicon layer and incorporating activated dopants into the crystalline structure formed.
It is desirable to be able to dope the silicon layer as close as possible up to the channel of the transistor to be formed, in particular to decrease access resistance. Thus, the silicon layer should advantageously be doped beneath the spacers. Doping beneath the spacers in this way is relatively difficult to achieve and to control. To promote greater proximity between the doped layer and the channel zone, one known method proposes producing very thin spacers beforehand on either side of the gate stack. Ion implantation is then carried out as described above on either side of the assembly including the gate stack and these thin spacers, then thicker spacers are formed over the thin spacers.
However, such a method has drawbacks. First, the zone beneath the very thin spacers cannot always be doped as desired. Second, the silicon layer on top of the buried dielectric is generally very thin, generally less than 9 nm thick. To be able to carry out the step of recrystallizing the silicon layer, it is necessary to retain crystalline silicon at the interface with the buried dielectric after the amorphization step. With the thinness of the silicon layer, retaining crystalline silicon in this way is difficult.
Additionally, the amorphization step results in the presence of residual defects after recrystallization. Such residual defects may affect the characteristics of the transistor formed.
The invention aims to overcome one or more of these drawbacks. Thus, the invention relates to a method for fabricating a field-effect transistor such as defined in the appended claims.
The invention also relates to the variants of the dependent claims. A person skilled in the art will understand that each of the features in the description or in the dependent claims may be independently combined with the features of an independent claim without, however, constituting an intermediate generalization.
Other features and advantages of the invention will become clearly apparent from the description thereof that is given hereinafter, by way of indication and without any limitation, with reference to the appended drawings, in which:
In step 300, a substrate provided with a layer 102 of semiconductor material, for example a silicon alloy, for example silicon that is not intentionally doped, is provided (the layer 102 described below will be made of silicon that is not intentionally doped or of SiGe that is not intentionally doped). The thickness of the layer of silicon 102 is between 6 and 20 nm, for example 6 nm. The layer of silicon 102 is here formed on top of a buried insulating layer 101, for example made of SiO2 (the layer 101 described below will be made of SiO2). The thickness of the layer 101 is typically between 10 and 50 nm, for example 20 nm. The buried insulating layer 101 is formed on top of a substrate 100, which is typically made of silicon that is not intentionally doped (the layer 100 described below will be made of silicon that is not intentionally doped). The invention may however also be applied with a layer 102 belonging to a bulk substrate.
In step 301, a layer 103 made of doped semiconductor material alloy is formed on top of the layer 102, as illustrated in
The layer 103 is typically made of SiGe or silicon alloy. To form an nMOS transistor, the doping of the layer 103 could be n-doping in a layer of silicon alloy. The n-type dopant is phosphorus, for example. To form a pMOS transistor, the doping of the layer 103 could be p-doping in a layer of SiGe alloy. The p-type dopant is boron, for example. The germanium concentration of the layer 103 is for example between 15% and 60% (in terms of number of atoms). The operation of deposition by epitaxial growth is for example carried out using SiGe with 30% germanium at a temperature of 630° C., using H2 as the carrier gas, and germane (GeH4) and dichlorosilane (DCS, SiH2Cl2) as precursors. The operation of deposition by epitaxial growth may also be carried out using SiGe with 10% germanium at a temperature of 700° C., using H2 as the carrier gas, and germane (GeH4) and silane (SiH4) as precursors. Advantageously, the layer 103 is pseudomorphic, i.e. its thickness is less than its critical thickness for relaxation, from which critical thickness it begins to undergo plastic relaxation.
In steps 302 to 305, steps of fabricating a sacrificial gate are implemented.
In step 302, a protective layer 104 is formed on top of the layer 103, as illustrated in
In step 303, a layer 105 made of amorphous silicon is formed on top of the protective layer 104, as illustrated in
In step 304, a hardmask layer 106 is formed on top of the layer of amorphous silicon 105, as illustrated in
In step 305, a lithography step is carried out to form a hardmask in the layer 106. Next, a step of anisotropically etching the layer 105 and the layer 104 following the etch mask is carried out in order to form the sacrificial gate stack 110. The stack is etched down to the layer 103 in order to obtain the configuration illustrated in
In step 306, spacers 120 are formed on top of the layer 103, on either side of the sacrificial gate stack 110, in order to obtain the configuration illustrated in
In step 307, a raised source 131 and drain 132 are formed on top of the layer 103, on either side of the assembly including the spacers 120 and the sacrificial gate stack 110, in order to obtain the configuration illustrated in
In step 308, a protective layer 107 is formed on top of the source 131 and the drain 132, on either side of the assembly including the spacers 120 and the sacrificial gate stack 110, in order to obtain the configuration illustrated in
In step 309, the hardmask and the sacrificial gate stack 110 are removed to form a groove 140 between the spacers 120. The width of the groove 140 thus obtained is advantageously at most equal to 40 nm. The configuration illustrated in
In step 310 (which step may be carried out as a continuation of step 309), the layer 103 is etched at the bottom of the groove 140 down to the layer 102, stopping at this layer 102. The layer 102 may also be etched slightly. The configuration illustrated in
The flanks of the groove 140 are partly delimited by lateral faces of the etched layer 103, these lateral faces being aligned with inner lateral faces of the spacers 120. The doped portion of the accesses to the channel zone, beneath the spacers 120, runsprecisely up to this channel zone without encroaching onto this channel zone. The transistor 1 thus formed exhibits decreased channel access resistance. Such results may be obtained without requiring the prior formation of thinner spacers surmounted by a new layer of spacers. To achieve the best possible alignment between the lateral faces of the zone 103 and the lateral faces of the spacers 120, the layer 103 is advantageously anisotropically etched.
In steps 311 and 312, the gate stacks 150 are formed. The stack may include a gate insulator 108 over the lateral faces and over the bottom of the groove 140 (for example composed of a 0.5 to 2 nm stack of SiO2 surmounted by 3 to 5 nm of HfO2) in order to obtain the configuration illustrated in
In step 312, the method moves on to forming a gate electrode 151 in the groove 140 and over the gate insulator 108 in order to obtain the configuration illustrated in
The steps of the method for fabricating the transistor 1 carried out according to the invention may have a thermal budget that is significantly smaller than a step in which dopants are thermally activated. The steps in a method for fabricating a transistor 1 according to the invention may thus be carried out without requiring a dopant diffusion step to be carried out.
The layer of semiconductor material 160 may be designed to exhibit mechanical strain in a plane parallel to the layer 102. Thus, for a pMOS transistor, the layer 160 will advantageously be configured to exhibit compressive strain (for example a layer 160 made of SiGe for a layer 102 made of Si), while, for an nMOS transistor, this layer 160 could be configured to exhibit tensile strain (for example a layer 160 made of Si for a layer 102 made of SiGe). Such mechanical strain allows the mobility of carriers in the channel zone of the transistor 1 formed to be increased.
To obtain the configuration illustrated in
To obtain the configuration illustrated in
To obtain the configuration illustrated in
To obtain the configuration illustrated in
A structure provided with a substrate (not illustrated) surmounted by a dielectric layer 201 is first provided. A nanowire 202 is formed on top of the layer 201.
The composition of the nanowire 202 is for example the same as that of the layer 102 described above. This nanowire 202 is encapsulated in a layer 203, the composition of which is for example the same as that of the layer 103 described above.
The layer 203 is typically deposited by epitaxial growth from the nanowire 202. The thickness of the layer 203 is typically between 2 and 10 nm. Advantageously, the layer 203 is pseudomorphic, i.e. its thickness is less than its critical thickness for relaxation, from which critical thickness it begins to undergo plastic relaxation.
The following steps in the method for fabricating the transistor 2 will be illustrated by sectional views through the nanowire 202 along a plane parallel to the substrate of the structure.
In the configuration illustrated in
In the configuration illustrated in
In the configuration illustrated in
In the configuration illustrated in
In the configuration illustrated in
In the configuration illustrated in
In the configuration illustrated in
In the configuration illustrated in
In the configuration illustrated in
Number | Date | Country | Kind |
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18 73209 | Dec 2018 | FR | national |
Number | Name | Date | Kind |
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20110303951 | Zhu | Dec 2011 | A1 |
20130001706 | Haran | Jan 2013 | A1 |
20140027818 | Asenov | Jan 2014 | A1 |
20140027854 | Asenov | Jan 2014 | A1 |
20150011056 | Kapoor et al. | Jan 2015 | A1 |
Entry |
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French Preliminary Search Report dated Oct. 14, 2019 in French Application 18 73209 filed on Dec. 18, 2018 (with English Translation of Categories of Cited Documents & Written Opinion), 9 pages. |
Number | Date | Country | |
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20200235226 A1 | Jul 2020 | US |