1. Field of the Invention
The present invention relates to a semiconductor manufacturing process, and particularly to a method of manufacturing a MOS transistor.
2. Description of the Prior Art
The performance of MOS transistors has increased year after year with the diminution of critical dimensions and the advance of large-scale integrated circuits (LSI). The process of semiconductor has evolved to 65 nm (0.065 μm) in 2005 and is approaching 45 nm. In order to meet the demand of miniaturization of the semiconductor industry, the current channel length under the gate must meet the standard of 45 nm. To meet the 45 nm channel length requirement, it is crucial to control the critical dimension (CD) during the process of exposure of the gate so as to control the line width of the conductive layer (polysilicon layer for example) after the etching process. Because the current lithographic tool techniques are incapable of obtaining the ideal CD, trimming methods are employed to reduce the size of gate line width.
On the other hand, the improvement of carrier mobility so as to increase the speed performance of MOS transistors has become a major topic for study in the semiconductor field. For the known arts, attempts have been made to use a strained silicon layer, which has been grown epitaxially on a silicon substrate with a silicon germanium (SiGe) layer disposed therebetween. In this type of MOS transistor, a biaxial tensile strain occurs in the epitaxy silicon layer due to the silicon germanium which has a larger lattice constant than silicon, and, as a result, the band structure alters, and the carrier mobility increases. This enhances the speed performance of the MOS transistors.
For the known arts, an oxide hard mask layer is usually used for making a gate during a SiGe process. However, as shown in
To solve the problems mentioned above, a silicon-rich nitride material instead of oxide has been used as a hard mask layer; however, a poly bump issue occurs in the SiGe process. As shown in
Therefore, there is still a need for a novel SiGe process to solve the issues of oxide loss or poly bump as described above.
The objective of the present invention is to provide a method of manufacturing a MOS transistor to avoid STI oxide loss or poly bump problems typically encountered in conventional SiGe processes.
The method of manufacturing a MOS transistor according to the present invention comprises steps as follows. A substrate is provided. A gate dielectric layer is formed on the substrate and a conductive layer is formed on the gate dielectric layer, a hard mask layer is formed on the conductive layer, and a photo resist layer is formed on the hard mask layer, sequentially. The photo resist layer comprises a tri-layer structure of a top photo resist layer, a silicon-containing photo resist layer, and a bottom anti-reflective coating (BARC). The etching selectivity ratio of the hard mask layer to silicon oxide is more than 2:1. Each layer of the photo resist layer is sequentially patterned until the BARC is patterned. The hard mask layer is patterned by using the BARC as a mask. A first etching process is performed on the conductive layer by using the patterned hard mask layer as a mask to form a gate. A first spacer is formed on sidewalls of the gate. A cap layer is conformally formed to cover the substrate. The cap layer is defined through a patterned photo resist layer, such that the cap layer has an opening at each of two sides of the gate. A second etching process is performed using the cap layer as a mask to form a recess on the substrate corresponding to each opening, wherein the patterned hard mask layer and the spacer-shaped cap layer protect the gate therebeneath from being bared due to the second etching process. An epitaxial growth process is performed for forming an epitaxial layer in each of the recesses. After forming the epitaxial layer, the patterned hard mask layer and the spacer-shaped cap layer are removed. A second spacer is formed on the first spacer.
In another aspect of the present invention, a method of manufacturing a MOS transistor is provided. The method comprises steps as follows. A substrate is provided. A gate dielectric layer is formed on the substrate, a conductive layer is formed on the gate dielectric layer, and a hard mask layer is formed on the conductive layer, sequentially. The etching selectivity ratio of the hard mask layer to silicon oxide is more than 2:1. A photo resist layer is formed on the hard mask layer. The photo resist layer comprises a tri-layer structure a top photo resist layer, a silicon-containing photo resist layer, and a bottom anti-reflective coating (BARC). Each layer of the photo resist layer is sequentially patterned until the BARC of the photo resist layer is patterned. The hard mask layer is patterned using the BARC of the photo resist layer as a mask. A first etching process is performed on the conductive layer by using the patterned hard mask layer as a mask to form a gate. A first spacer is formed on sidewalls of the gate. A cap layer is conformally formed to cover the substrate. An anisotropic etching process is performed on the cap layer, thereby to partially remove the cap layer and form a spacer-shaped cap layer on the first spacer and expose the substrate beside the spacer-shaped cap layer. A second etching process is performed using the spacer-shaped cap layer and the patterned hard mask layer as a mask to form a recess on the substrate exposed at each of two sides of he gate, wherein the patterned hard mask layer and the spacer-shaped cap layer protect the gate therebeneath from being bared due to the second etching process. An epitaxial growth process is performed for forming an epitaxial layer in each of the recesses. After forming the epitaxial layer, the patterned hard mask layer and the spacer-shaped cap layer are removed. A second spacer is formed on the first spacer.
In another aspect of the present invention, a method of manufacturing a MOS transistor is provided. The method comprises steps as follows. A substrate is provided. The substrate comprises a first active region for fabricating a first transistor and a second active region for fabricating a second transistor. A gate dielectric layer is formed on the substrate, a conductive layer is formed on the gate dielectric layer, and a hard mask layer is formed on the conductive layer, sequentially. The etching selectivity ratio of the hard mask layer to silicon oxide is more than 2:1. A first photo resist layer is formed on the hard mask layer, wherein the first photo resist layer comprises a tri-layer structure of a top photo resist layer, a silicon-containing photo resist layer, and a bottom anti-reflective coating (BARC). Each layer of the first photo resist layer is patterned until the BARC of the photo resist layer is patterned. The hard mask layer is patterned using the BARC of the first photo resist layer as a mask. A first etching process is performed on the conductive layer by using the patterned hard mask layer as a mask to form a first gate on the first active region and a second gate on the second active region. A first spacer and a second spacer are formed on sidewalls of the first gate and the second gate. A cap layer is conformally formed to cover the first active region and the second active region. The cap layer covering the second active region is partially removed to form a spacer-shaped cap layer on the second spacer and expose the substrate beside the spacer-shaped cap layer. A second etching process is performed using the spacer-shaped cap layer and the patterned hard mask layer as a mask to form a recess on the substrate exposed at each of two sides of the second gate, wherein the patterned hard mask layer and the spacer-shaped cap layer protect the second gate therebeneath from being bared due to the second etching process. An epitaxial growth process is performed for forming an epitaxial layer in each of the recesses. A second photo resist layer is formed to cover the second active region. The cap layer covering the first active region is partially removed to form a third spacer on the first spacer. The second photo resist layer is removed. A dielectric layer is formed to cover the first active region and the second active region. A third etching process is performed to partially remove the dielectric layer for forming a fourth spacer and a fifth spacer respectively on the third spacer and the spacer-shaped cap layer, and the patterned hard mask layer is exposed. The patterned hard mask layer is removed.
In another aspect of the present invention, a method of manufacturing a MOS transistor is provided. The method comprises steps as follows. A substrate is provided. The substrate comprises a first active region for fabricating a first transistor and a second active region for fabricating a second transistor. A gate dielectric layer is formed on the substrate, a conductive layer is formed on the gate dielectric layer, and a hard mask layer is formed on the conductive layer, sequentially. The etching selectivity ratio of the hard mask layer to silicon oxide is more than 2:1. A first photo resist layer is formed on the hard mask layer, wherein the first photo resist layer comprises a tri-layer structure of a top photo resist layer, a silicon-containing photo resist layer, and a bottom anti-reflective coating (BARC). Each layer of the first photo resist layer is patterned until the BARC of the photo resist layer is patterned. The hard mask layer is patterned using the BARC of the first photo resist layer as a mask. A first etching process is performed on the conductive layer by using the patterned hard mask layer as a mask to form a first gate on the first active region and a second gate on the second active region. A first spacer and a second spacer are formed on sidewalls of the first gate and the second gate. A cap layer is conformally formed to cover the first active region and the second active region. The cap layer covering the second active region is partially removed to form a spacer-shaped cap layer on the second spacer and expose the substrate beside the spacer-shaped cap layer. A second etching process is performed using the spacer-shaped cap layer and the patterned hard mask layer as a mask to form a recess on the substrate exposed at each of two sides of the second gate, wherein the patterned hard mask layer and the spacer-shaped cap layer protect the second gate therebeneath from being bared due to the second etching process. An epitaxial growth process is performed for forming an epitaxial layer in each of the recesses. A dielectric layer is formed to cover the first active region and the second active region. A third etching process is performed to partially remove the dielectric layer for simultaneously forming a third spacer and a fourth spacer on the first spacer and forming the fifth spacer on the spacer-shaped cap layer, and the patterned hard mask layer is exposed. The patterned hard mask layer is removed.
In the method of the present invention, a tri-layer photo resist layer is used to form a patterned hard mask layer having a sound shape and a small size, and the hard mask layer is used to form a gate. After the gate is formed, the hard mask layer is not removed until the epitaxial layers are formed. As such, the spacer-shaped cap layer formed on the sidewall of the gate also has a good configure due to the good-shaped hard mask layer. Both provide a good protection to the gate during the etching and the cleaning for the recesses such that the gate is not exposed and the poly bump issue is avoided. Additionally, since the etching selectivity ratio of the hard mask layer to silicon oxide is more than 2:1, STI oxide loss is insignificant when the hard mask layer is removed, and accordingly an STI oxide loss issue leading to contact bridge can be avoided.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In the method of forming an epitaxial layer in a MOS transistor manufacturing process according to the present invention, a tri-layer photo resist layer is utilized to pattern a hard mask layer having a sound shape substantially without a round corner and a small line width. Such hard mask layer is utilized to make a gate, and after the gate is formed, the hard mask layer is not subsequently removed as that usually done in conventional technologies, but the hard mask layer is removed after recesses are formed and epitaxial layers are formed in the recesses in an epitaxial process. The method of the present invention is easily integrated with current processes and has a low cost, and accordingly can be well applied to MOS transistor manufacturing processes. Some embodiments of the present invention are described hereinafter.
The conductive layer 42 may be formed by deposition, such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). The conductive layer 42 may comprise polysilicon or other conductive material. The hard mask layer 44 may comprise a material having an etching selectivity over silicon oxide of more than 2:1, with respect to a phosphoric acid etching solution. There is not an upper limit for the etching selectivity ratio. In view of common materials easily available, the etching selectivity ratio may be preferably between 2:1 and 5:1. Suitable materials may be, for example, silicon nitride, silicon-rich nitride, SiON, APF film (trade name, available from Applied Materials, Inc. of Santa Clara, Calif.), or SiC, but not limited thereto. The top photo resist layer 48 may be a 193 nm photo resist layer, which may be relatively thin, and accordingly, the resolution may be improved. The silicon-containing photo resist layer 50, serving as a medial layer, may contain 10-30% of silicon and has a function of anti-erosion. The BARC 52 may be a 365 nm (I-line) photo resist layer, which may improve adhesion and provide a function of anti-reflection. Such tri-layer photo resist layers and the patterning processes are taught in co-pending and co-assigned U.S. patent application Ser. No. 11/620,028, the contents of which are incorporated herein by reference.
After the tri-layer photo resist layer 46 is formed on the hard mask layer 44, a photolithographic process is performed to pattern the top photo resist layer 48, as shown in
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Alternatively, an anisotropic etching process may be performed directly on the cap layer 66, such that a spacer-shaped cap layer 69 as shown in
The method for forming the recesses 70 may be dry etching and/or wet etching. The cap layer 66 may comprise silicon nitride for convenient removal by wet etching in the subsequent process. Thereafter, a wet cleaning process is optionally performed to remove impure residue on the surface of the recess 70.
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According to the method of the present invention described above, the present invention may be applied to the manufacturing process to simultaneously form a PMOS and a NMOS on a same substrate. Please refer to
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According to the method of the present invention described above, the present invention may be modified in various ways.
In this embodiment, the cap layer 125 covering the first active region 101 and the spacer-shaped cap layer 126 on the sidewall of the second gate 112 are not removed, but directly covered with a dielectric layer 140, and then they are anisotropically dry etched together to form spacers. Accordingly there are other advantages in addition to the advantage of avoiding STI oxide loss and gate bump. In conventional techniques, since the cap layer and the spacer-shaped cap layer are removed by wet etching immediately after the epitaxial layers are formed, a specific material suitable for wet etching, such as Singen SiN, is needed, and the wet etching is slow. In the embodiment of the present invention, the choice for the material of the cap layer 125 is wider, for example, BTBAS SiN (BTBAS stands for bis-(t-butylamino)silane) may be utilized, without being limited to the wet etching selectivity ratio as the conventional techniques, and thus the process is faster and without the disadvantages of using Singen SiN.
All combinations and sub-combinations of the above-described features also belong to the present invention. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.