Claims
- 1. A method of mounting chip components on a substrate having electrically conductive lands formed on a top surface thereof which method comprises the steps of covering said lands with a printing screen having a printing pattern,
- forming a plurality of mutually separated bonding agent layers on said lands by applying said bonding agent to the lands through the printing pattern such that less than the full surface area of each of said lands is covered by said bonding agent layers;
- placing at least one of said chip components on said bonding agent layers; and
- pressing said chip components that have been placed on said bonding agent layers toward said land to spread said bonding agent layers on said lands prior to applying heat to said bonding agent layers.
- 2. A method according to claim 1, wherein said bonding agent, employed for forming said bonding agent layers, is solder.
- 3. A method according to claim 1, wherein a first bonding agent layer and a second bonding agent layer are formed spatially separated from each other during the formation of said bonding agent layers.
- 4. A method according to claim 3, wherein said first and second bonding agent layers have identical shapes.
- 5. A method according to claim 3, wherein said first and second bonding layers have different shapes.
- 6. A method according to claim 1, wherein said printing screen employed for forming said bonding agent layers has a plurality of openings which are similar to said bonding agent layers to be formed on said lands, and wherein said bonding agent is supplied to the lands through said openings.
- 7. A method of mounting chip components on a substrate having electrically conductive lands formed on a top surface thereof which method comprises the steps of covering said lands with a printing screen having a printing pattern;
- forming a plurality of mutually separated solder layers on said lands by employing said printing screen with a printing pattern which has a plurality of openings similar to the desired solder layers, and applying paste solder to said lands through said openings;
- placing said chip components on said solder layers; and
- pressing said chip components toward said lands to spread said solder layers on said lands prior to melting said solder layers.
Priority Claims (1)
Number |
Date |
Country |
Kind |
4-329677 |
Sep 1992 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 08/162,487, filed Dec. 3, 1993, now abandoned.
US Referenced Citations (5)
Foreign Referenced Citations (3)
Number |
Date |
Country |
1-224160 |
Sep 1989 |
JPX |
2-172293 |
Jul 1990 |
JPX |
3-284895 |
Dec 1991 |
JPX |
Continuations (1)
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Number |
Date |
Country |
Parent |
162487 |
Dec 1993 |
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