Patent Application
20250079357
The present technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to processes and semiconductor devices for hybrid bonding.
Hybrid bonding (which can also be referred to as heterogeneous integration) is a semiconductor fabrication technique that allows for increased miniaturization of three-dimensional semiconductor device fabrication processes related to advanced node technologies requiring heterogenous integration. Hybrid bonding involves the creation of strong bonds between dies, wafers, and/or substrates without the need for adhesives or interconnect materials.
However, heterogenous integration techniques can be limited by the scaling-down of pitch. As desired pitch shrinks, the dielectric surface area available for the contact bonding part of hybrid bonding also shrinks. As such, hybrid bonding systems may require a large percentage of bonding surface between dies to be dielectric. As desired pitch decreases, standard hybrid bonding techniques and systems may be incapable of adequately providing sufficient bond strength.
Thus, there is a need for improved systems and methods that can be used to improve systems for hybrid bonding as pitch shrinks. These and other needs are addressed by the present technology.
In some embodiments, a semiconductor device for hybrid bonding may include a first structure, which may include a first metal layer overlaying a first substrate; a first dielectric layer overlaying the first metal layer and defining a set of one or more features recessed in the first dielectric layer; a dielectric film overlaying the first dielectric layer, wherein the dielectric film is comprised of a first dielectric; and a first copper-containing material deposited within the set of one or more features; and a second structure, which may include a second metal layer overlaying a second substrate; a second dielectric layer overlaying the second metal layer and defining a second set of one or more features recessed in the second dielectric layer, wherein the second dielectric layer is comprised of a second dielectric, wherein the second dielectric is a different material than the first dielectric; and a second copper-containing material deposited within the second set of one or more features; and wherein the dielectric film of the first structure is hybrid bonded to the second dielectric layer of the second structure, wherein the first copper-containing material of the first structure contacts the second copper-containing material of the second structure.
In some embodiments, a method of forming a semiconductor device may include forming a first structure, which may include forming a first metal layer over a first substrate; forming a first dielectric layer over the first metal layer; forming a dielectric film over the first dielectric layer, wherein the dielectric film is comprised of a first dielectric; etching a trench in the dielectric film and first dielectric layer, wherein the trench extends from a top surface of the dielectric film down to at least a top surface of the first metal layer; and filling the trench with a first copper-containing material; contacting the first structure with a second structure, the second structure may include a second metal layer overlaying a second substrate; a second dielectric layer overlaying the second metal layer and defining a second set of one or more features in the second dielectric layer, wherein the second dielectric layer is comprised of a second dielectric, wherein the second dielectric is a different material than the first dielectric; and a second copper-containing material deposited within the second set of one or more features; and bonding the first structure to the second structure, wherein the dielectric film of the first structure is hybrid bonded to the second dielectric layer of the second structure, wherein the first copper-containing material of the first structure contacts the second copper-containing material of the second structure.
In some embodiments, a method of forming a semiconductor device may include forming a first structure, which may include forming a first metal layer over a first substrate; forming a first dielectric layer over the first metal layer; etching a trench in the first dielectric layer, wherein the trench extends from a top surface of the first dielectric layer down to at least a top surface of the first metal layer; filling the trench with a first copper-containing material; and selectively depositing a dielectric film on the first structure, the dielectric film overlaying the first dielectric layer and not overlaying the first copper-containing material, wherein the dielectric film is comprised of a first dielectric; contacting the first structure a second structure, which may include a second metal layer overlaying a second substrate; a second dielectric layer overlaying the second metal layer and defining a second set of one or more features in the second dielectric layer, wherein the second dielectric layer is comprised of a second dielectric, wherein the second dielectric is a different material than the first dielectric; and a second copper-containing material deposited within the second set of one or more features; and bonding the first structure to the second structure, wherein the dielectric film of the first structure is hybrid bonded to the second dielectric layer of the second structure, wherein the first copper-containing material of the first structure contacts the second copper-containing material of the second structure.
In any embodiments, any and all of the following features may be implemented in any combination and without limitation. The first dielectric layer may be or include the second dielectric. The first dielectric may include silicon carbon nitride and the second dielectric may include silicon oxide. The first dielectric may include silicon oxynitride and the second dielectric may include silicon oxide. The dielectric film may have a thickness of 5 nm. The first copper-containing material may be characterized by a dish profile having a dish depth of less than or about 1 nm. The method of forming a semiconductor device can also include contacting the first structure with one or more slurries and one or more platens, wherein the one or more slurries and one or more platens removes a portion of the first copper-containing material and a second portion of the dielectric film. The method of forming a semiconductor device can also include forming a liner in the trench, and wherein filling the trench with the first copper-containing material comprises overlaying the liner with the first copper-containing material. The method of forming a semiconductor device can also include contacting the first structure with one or more slurries and one or more platens, wherein the one or more slurries and one or more patterns remove a portion of the first copper-containing material and a second portion of the first dielectric layer, wherein contacting the first structure with the one or more slurries recesses the first dielectric layer a distance of greater than or about 5 nm from a top surface of the first copper-containing material. Etching the trench in the dielectric film and first dielectric layer can include etching the trench in the dielectric film with a chlorine-based etch. Etching the trench in the dielectric film and first dielectric layer may include etching the trench in the dielectric film and first dielectric layer with a multi-material etch, wherein the multi-material etch may include two or more of: a chlorine-based etch, a fluorine-based etch, an oxygen-plasma etch, and a fluorine-and-oxygen-based etch. Forming the first metal layer and forming the first dielectric layer may be performed in a first chamber, wherein etching the trench in the dielectric film and the first dielectric layer may be performed in a second chamber, wherein the first structure may be moved from the first chamber to the second chamber without exposing the first substrate to an external atmosphere. Contacting the first structure with the one or more slurries and one or more platens may recess the first copper-containing material a distance of less than or about 1 nm within the trench below a top surface of the dielectric film. The first dielectric may include silicon oxide and the second dielectric may include silicon oxynitride. The first dielectric may include silicon oxide and the second dielectric may include silicon carbon nitride. The first dielectric layer may be or include a third dielectric, wherein the third dielectric is a different material than the first dielectric and the second dielectric. Depositing the polymer may include depositing a long-chain polymer via vapor deposition.
A further understanding of the nature and advantages of various embodiments may be realized by reference to the remaining portions of the specification and the drawings, wherein like reference numerals are used throughout the several drawings to refer to similar components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specification to an existing sub-label, it is intended to refer to all such multiple similar components.
which material layers are included and processed according to some embodiments.
A first structure for semiconductor devices having a dielectric film on the top surface of the structure can be used to form semiconductor devices that are composed of hybrid bonded structures with reduced dielectric surface area and reduced pitch for metal studs. A semiconductor device can be formed by hybrid bonding the dielectric film of the first structure to a top surface dielectric of a second structure, where the dielectric film and the top surface dielectric are different dielectrics. In this way, the first structure and the second structure have asymmetric dielectrics on their respective top surfaces. The hybrid bonding between the asymmetric dielectrics can have increased bond strength over the hybrid bonding of symmetric dielectrics.
While conventional hybrid bonding systems may provide sufficient bond strength to bond two wafers under certain conditions, conventional systems may be limited to a pitch of a certain minimum size and/or a minimum percentage surface area of the dielectric on the surface of the wafers. Thus, the wafers are limited to a certain percentage of metal pads on the surface of the wafers and thus a limited metal density. For example, the pitch may have a minimum size of 1 micron and the dielectric bonding surface may be roughly 80% or more of the bonding surface between the wafers. The present technology overcomes these issues associated with conventional hybrid bonding systems by increasing bond strength between the dielectrics of dies. By hybrid bonding asymmetric dielectrics, the increased bond strength during the hybrid-bonding process can enable a reduced pitch and a higher density of metal pads between the wafers.
As an overview, hybrid bonding is a semiconductor fabrication technique that combines the advantages of both direct bonding and traditional bonding methods. It enables the integration of dissimilar materials at a molecular level, facilitating the development of advanced semiconductor devices with improved performance, functionality, and miniaturization that may not require the use of metal interconnects. Hybrid bonding is particularly helpful for three-dimensional semiconductor device fabrication.
When a system consisting of two wafers (dies, substrates, and the like can also be used) are being bonded together via hybrid bonding, the top surface dielectrics of the wafers are first treated to create a reactive layer via surface activation. Then the top surface dielectrics can be contacted to each other to bond, for example by spontaneous hydrophilic oxide-oxide bonding. Once the top surface dielectric have been bonded, the metal pads of each wafer will be separated by a dishing gap. The system can then be annealed such that the metal pads of each wafer will thermally expand and connect while the top surface dielectrics will remain approximately the same size by comparison to the metal. Once the annealing is complete, the wafers have been bonded via hybrid bonding.
Although the remaining disclosure will routinely identify specific hybrid bonding processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other processes as may occur in the described chambers. Accordingly, the technology should not be considered to be so limited as for use with the described etching or deposition processes alone. The disclosure will discuss one possible system that can be used with the present technology before describing systems and methods or operations of exemplary process sequences according to some embodiments of the present technology. It is to be understood that the technology is not limited to the equipment described, and processes discussed may be performed in any number of processing chambers and systems.
The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing and/or etching a material film on the substrate or wafer. In one configuration, two pairs of the processing chambers, for example 108c-d and 108e-f, may be used to deposit material on the substrate, and the third pair of processing chambers, for example 108a-b, may be used to cure, anneal, or treat the deposited films. In another configuration, all three pairs of chambers, for example 108a-f, may be configured to both deposit and cure a film on the substrate. Any one or more of the processes described may be carried out in additional chambers separated from the fabrication system shown in different embodiments. It will be appreciated that additional configurations of deposition, etching, annealing, and curing chambers for material films are contemplated by system 100. Additionally, any number of other processing systems may be utilized with the present technology, which may incorporate chambers for performing any of the specific operations. In some embodiments, chamber systems which may provide access to multiple processing chambers while maintaining a vacuum environment in various sections, such as the noted holding and transfer areas, may allow operations to be performed in multiple chambers while maintaining a particular vacuum environment between discrete processes.
System 100, or more specifically chambers incorporated into system 100 or other processing systems, may be used to produce structures according to some embodiments of the present technology.
It should be appreciated that the specific steps illustrated in
At operation 202, the method of flowchart 200 of forming a first structure 301 may include forming a metal layer 304 over a substrate 302. As illustrated in
As illustrated in
In some examples, the layers (for example, the substrate 302, the metal layer 304, and other layers described herein such as the barrier film 306, the dielectric layer 308, and the dielectric film 310) described herein can be directly overlaying each other such that the first layer is overlaying the second layer. For example, the metal layer 304 can directly overlay the substrate 302 such that there are no intervening layers. In some examples, the layers described herein can have layers between them. For example, the metal layer 304 can be overlaying an intervening layer which overlays the substrate 302. Furthermore, when forming a layer, any process for forming or depositing material can be used. For example, chemical vapor deposition (CVD) can be used in some examples while atomic layer deposition (ALD) can be used in other examples. Specifics regarding specific layers and/or materials are also described herein.
At operation 204, the method of flowchart 200 of forming the first structure 301 may include forming a dielectric layer 308 over the metal layer 304. As illustrated in
In some examples, the first structure 301 can include a barrier film 306 between the dielectric layer 308 and the metal layer 304. A barrier film 306 can have a low dielectric constant in order to reduce the dielectric constant of copper damascene structures in order to achieve faster and more powerful devices. Some barrier films can have a dielectric constant of less than 5 or even lower. Example barrier films include silicon nitride films, and low-k barrier films such as BLOK (a Si—C—H compound) or N-BLOK (a Si—C—H—N compound) developed by Applied Materials. The barrier film 306 can also be referred to as a capping layer for the metal layer 304.
At operation 206, the method of flowchart 200 of forming the first structure 301 may include forming a dielectric film 310 over the dielectric layer 308. As illustrated in
In some examples, forming the dielectric film 310 can be done in a different chamber of the system 100 than forming the dielectric layer 308. In some examples, the formation of each layer can be done in different chambers. In some examples, the formation of the dielectric layer 308, metal layer 304, and/or substrate 302 can be done in a single chamber.
In some examples, forming the dielectric film 310 can include depositing the dielectric material via atomic layer deposition. Depositing the dielectric material may include contacting the first structure 301 with a hydrogen-containing precursor. The first structure 301 can be contacted by a hydrogen-containing precursor in order to hydroxylate the surface of the dielectric layer 308. Hydroxylating the surface of the dielectric layer 308 can form a surface activation layer on the dielectric layer 308 such that hydrogen atoms form off the lattice of the dielectric layer 308. The hydrogen-containing precursor can be contacted with the first structure via any suitable means, for example CVD plasma-enhanced CVD, ALD, and the like.
Once the surface of the dielectric layer 308 has been activated to form a surface activation layer, precursors can be applied to the first structure 301 to form the dielectric film 310. In some examples, the structure 301 can be contacted by one or more precursors. The precursors can react with the surface of the surface activation layer of the dielectric layer 308 depositing an atomic layer of a material, for example, a dielectric. As in a conventional ALD process, the first structure 301 can be contacted by first precursor and then a second precursor (or any number of precursors), alternating contact between the first precursor and the second precursor (or any number of precursors), to deposit atomic layers of a dielectric material to form a dielectric film 310. The one or more precursors 718 can be selected to produce a specific dielectric film 310 on the surface of the dielectric layer 308. For example, the ALD process for depositing aluminum oxide can alternate precursors of trimethylaluminium and water. Any suitable combinations of precursors can be used.
In embodiments, there may be a determination of whether a target thickness of the dielectric film 310 has been achieved following operation 206. If a target thickness of the dielectric film 310 has not been achieved, another cycle of ALD can be performed. Exemplary ranges of target thickness to discontinue further cycles of forming dielectric film 710 include less than or about 10 nm. Additional exemplary thickness ranges may include less than or about 9.5 nm, less than or about 9.0 nm, less than or about 8.5 nm, less than or about 8.0 nm, less than or about 7.5 nm, less than or about 7.0 nm, less than or about 6.5 nm, less than or about 6.0 nm, less than or about 5.5 nm, less than or about 5.0 nm, less than or about 4.5 nm, less than or about 4.0 nm, less than or about 3.5 nm, less than or about 3.0 nm, less than or about 2.5 nm, less than or about 2.0 nm, less than or about 1.5 nm, less than or about 1.0 nm, less than or about 0.5 nm, or less, including any fraction of any of the stated numbers.
At operation 208, the method of flowchart 200 of forming the first structure 301 may include etching a feature in the dielectric layer 308, the dielectric film 310, and the barrier film 306 if applicable. Features etched into the dielectric layer 308 and dielectric film 310 can include trenches, apertures or vias, or any other structure useful in semiconductor processing. As illustrated in
The etchant used to etch the features into the dielectric layer 308, dielectric film 310, and if applicable the barrier film 306 can include a variety of semiconductor processing etches that are either solutions or plasmas, such as chlorine, fluorine, oxygen plasma, or fluorine-and-oxygen. In some examples, the etchants can be applied one at a time. In some examples, multiple etchants can be combined to form a multi-material etch. An etchant for the dielectric film 310 can be different than an etchant for the dielectric layer 308 or the barrier film 306. In some examples, a chlorine etch can be used on a dielectric film 310 of the material aluminum oxide. In some examples, a fluorine etch can be used on a TEOS layer of the dielectric layer 308. In some examples, an ashing etch such as an oxygen plasma can be used to remove organics. In some examples, a fluorine-and-oxygen etch can be used on a BLOK or n-BLOK layer of the barrier film 306. In some examples, one or more etches can be dry reactive ion etches. In some examples, one or more etches can be wet etches. Different etchants can have selectivity for different layers such that when an etchant is used it will primarily etch a targeted layer rather than other layers exposed to the etch. For example, a fluorine etch used on a TEOS layer of the dielectric layer 308 may selectively etch the TEOS layer rather than the dielectric film 310. The selectivity of the etch can make the etching of the targeted layer at a rate that is greater than or about 1.5:1 compared to one or more other layers, and may be greater than or about 1.6:1, greater than or about 1.7:1, greater than or about 1.8:1, greater than or about 1.9:1, greater than or about 2.0:1, greater than or about 2.1:1, greater than or about 2.2:1, greater than or about 2.3:1, greater than or about 2.4:1, greater than or about 2.5:1, greater than or about 2.6:1, greater than or about 2.7:1, greater than or about 2.8:1, greater than or about 2.9:1, greater than or about 3.0:1, or more.
At operation 210, the method of flowchart 200 of forming the first structure 301 may include filling the feature with a metal-containing material. As illustrated in
Metals used to fill the feature can include copper or any other high conductivity metal. Although this application will regularly discuss copper, it is to be understood that any number of conductive metal materials may be used in embodiments of the present technology, and the present technology should not be limited to any particular conductive metal material.
In some examples, a liner is formed in the trench prior to filling the trench with the metal-containing material. As illustrated in
In some examples, after the feature has been filled with a metal-containing material 322, the first structure 301 can be polished via a chemical-mechanical polishing (CMP) process as described herein with greater detail in relation to
In some examples, the liner 324 can be polished via the CMP process such that the top surface of the liner 324 aligns with the top surface of the dielectric layer 308. In some examples, the liner 324 can be polished via the CMP process such that the top surface of the liner 324 aligns with the top surface of the metal-containing material 322 as seen in
At operation 212, the method of flowchart 200 can also include forming the semiconductor device by hybrid bonding the first structure with the dielectric film to a second structure without the dielectric film. In some examples, the method of flowchart 200 may include bonding the first structure 301 to a second structure 331 via hybrid bonding as shown in
The second structure 331 does not include a dielectric film. As such, when the first structure 301 and the second structure 331 are hybrid bonded together, the top surface of the dielectric film 310 of the first structure is hybrid bonded to the top surface of the second dielectric layer 338 of the second structure 331. In some examples, the dielectric film 310 and the second dielectric layer 338 are not the same material. For example, the dielectric film 310 can be silicon oxynitride and the second dielectric layer 338 can be silicon oxide. As such, the hybrid bonding of the first structure 301 and the second structure 331 can be considered hybrid bonding of asymmetric dielectrics as the dielectric film 310 and the second dielectric layer 338 are not equivalent or the same dielectric materials. In some examples, the second dielectric layer 338 of the second structure 331 can be the same material as the dielectric layer 308 of the first structure 301. For example, the second dielectric layer 338 and the dielectric layer 308 can both be silicon oxide and the dielectric film 310 can be silicon oxynitride. In another example, the second dielectric layer 338 and the dielectric layer 308 can both be silicon carbon nitride and the dielectric film 310 can be tetraethyl orthosilicate. In some examples, the second dielectric layer 338 of the second structure 331 can be a different material from the dielectric layer 308 of the first structure 301.
In some examples, bonding the first structure 301 to the second structure 331 can include using a surface activation process on the first structure 301 and/or the second structure 331. The surface activation process can include contacting the first structure 301 and/or the second structure 331 with a hydrogen-containing precursor. The surface activation process can activate the top surface of the dielectric film 310 of the first structure 301 and/or the top surface of the second dielectric layer 338 of the second structure 331 such that either one or both surfaces have been hydroxylated to have dangling hydroxylation groups. In some examples, water is then applied to the top surface of the dielectric film 310 of the first structure 301 and/or the second dielectric layer 338 of the second structure 331.
The top surface of the dielectric film 310 of the first structure 301 and the top surface of the second dielectric layer 338 of the second structure 331 can then be aligned and contacted. When the top surface of the dielectric film 310 contacts the top surface of the second dielectric layer 338, a spontaneous bonding occurs primarily via Van der Waals bonds to set an initial bond between the top surface of the dielectric film 310 and the top surface of the second dielectric layer 380. This causes the first structure 301 and the second structure 331 to be bonded together via the top surface of the dielectric film 310 contacting the top surface of the second dielectric layer. The initial bond between the first structure 301 and the second structure 331 may not be the finalized bond but can be used to keep the first structure 301 and the second structure 331 aligned as additional processes are run to finalize the hybrid bond.
The combination structure of the first structure 301 and the second structure 331 can then annealed. During the annealing operation, the dielectric film 310 and the second dielectric layer 338 may further form covalent bonds increasing the bond strength between the dielectric film 310 and the second dielectric layer 338. In some examples, the water and/or the dangling hydroxylation groups assist in forming the covalent bonds between the dielectric film 310 and the second dielectric layer 338. Because the dielectric material of the dielectric film 310 and the dielectric material of the second dielectric layer 338 are different the covalent bonds between the top surface of the dielectric film 310 and the top surface of the second dielectric layer 338 are quite strong. The strength of the covalent bonds enables the surface area of the dielectric film 310 and the second dielectric layer 338 to be a lower ratio than traditional hybrid bonding techniques. Because the dielectric film 310 and the second dielectric layer 338 are different materials, the bond strength between the dielectric film 310 and the second dielectric layer 338 can be about 15-75% stronger when compared to bond strength between conventional dielectric layers being hybrid bonded together. For example, the bond strength between a dielectric film 310 of silicon oxynitride and a second dielectric layer 338 of tetraethyl orthosilicate can be about 40-55% stronger when compared to bond strength between conventional dielectric layers (such as silicon oxide) being hybrid bonded together. In another example, the bond strength between a dielectric film 310 of silicon carbon nitride and a second dielectric layer 338 of tetraethyl orthosilicate can be about 60-75% stronger when compared to bond strength between conventional dielectric layers (such as silicon oxide) being hybrid bonded together.
The annealing of the combination structure can also cause the metal-containing material 322 to extrude towards the second metal-containing material 354. As previously described, the combined depth of the metal-containing material 322 (and the second metal-containing material 354 by extension) is important for the bonding of the metal-containing materials. When the combined depth is less than 5 nm or lower, subsequent annealing to bond the metal-containing material 322 and the second metal-containing material 354 may be effective as the metal-containing material 322 and the second metal-containing material 354 may be close enough to bond to each other during the annealing step of hybrid bonding. During the annealing step, the metal-containing materials from the two structures may extrude towards one another, may contact each other, and may bond. At reduced annealing temperatures according to some embodiments of the present technology, unless the dishing is sufficiently reduced, the amount of expansion may be insufficient to allow adequate coupling between the copper. By performing polishing operations according to the present technology, reduce dishing may be provided, which may improve coupling capability between substrates at reduced annealing temperatures.
Once the annealing process is completed, the first structure 301 and the second structure 331 are hybrid bonded to form a single semiconductor device or a single structure. The use of hybrid bonding enables the fabrication of complex semiconductor devices from multiple structures and form the interconnects between the structures.
It should be appreciated that the specific steps illustrated in
At operation 402, the method of flowchart 400 of forming a first structure 501 may include forming a metal layer 504 over a substrate 502. As illustrated in
As illustrated in
In some examples, the layers (for example, the substrate 502, the metal layer 504, and other layers described herein such as the barrier film 506, the dielectric layer 508, and the dielectric film 510) described herein can be directly overlaying each other such that the first layer is overlaying the second layer. For example, the metal layer 504 can directly overlay the substrate 502 such that there are no intervening layers. In some examples, the layers described herein can have layers between them. For example, the metal layer 504 can be overlaying an intervening layer which overlays the substrate 502. Furthermore, when forming a layer, any process for forming or depositing material can be used. For example, chemical vapor deposition can be used in some examples while atomic layer deposition can be used in other examples. Specifics regarding specific layers and/or materials are also described herein.
At operation 404, the method of flowchart 400 of forming the first structure 501 may include forming a dielectric layer 508 over the metal layer 504. As illustrated in
In some examples, the first structure 501 can include a barrier film 506 between the dielectric layer 508 and the metal layer 504. A barrier film 506 can have a low dielectric constant in order to reduce the dielectric constant of copper damascene structures in order to achieve faster and more powerful devices. Some barrier films can have a dielectric constant of less than 5 or even lower. Example barrier films include silicon nitride films, and low-k barrier films such as BLOK (a Si—C—H compound) or N-BLOK (a Si—C—H—N compound) developed by Applied Materials. The barrier film 506 can also be referred to as a capping layer for the metal layer 504.
At operation 406, the method of flowchart 400 of forming the first structure 501 may include etching a feature in the dielectric layer 508 and the barrier film 506. In some examples, one or more features can be etched into the dielectric layer 508. Features etched into the dielectric layer 508 can include trenches, apertures or vias, or any other structure useful in semiconductor processing. As illustrated in
At operation 408, the method of flowchart 400 of forming the first structure 501 may include filling the feature with a metal-containing material. As illustrated in
In some examples, a liner is formed in the trench prior to filling the trench with the metal-containing material. As illustrated in
In some examples, after the feature has been filled with a metal-containing material 522, the first structure 501 can be polished via a chemical-mechanical polishing (CMP) process as described herein with greater detail in relation to
In some examples, the liner 524 can be polished via the CMP process such that the top surface of the liner 524 aligns with the top surface of the dielectric layer 508. In some examples, the liner 524 can be polished via the CMP process such that the top surface of the liner 524 aligns with the top surface of the metal-containing material 522 as seen in
At operation 410, the method of flowchart 400 of forming the first structure 501 may include selectively depositing a dielectric film. As illustrated in
In some examples, selectively depositing the dielectric film 510 includes a selective atomic layer deposition (ALD) process as described herein with greater detail in relation to
As previously explained, the CMP process may cause the top surface of the metal-containing material 522 to form a concave shape or dish shape that may feature a nadir or dish depth. If the nadir or dish depth combined with a recession depth of the top surface of the metal-containing material 522 to the top surface of the dielectric film 510 (the combination being referred to as combined depth) is too great, the material may not be useful for certain end products. For example, copper-to-copper hybrid bonding is one such application that may be sensitive to an imprecise combined depth. In some applications of copper-to-copper hybrid bonding, if the combined depth is too great, the copper-to-copper bond may not be sufficiently strong due to limited contact with studs from mating features, or the coupling may not occur at all. A combined depth of less than 5 nm may be small enough for copper-to-copper hybrid bonding, for example. As such, the selective deposition of the dielectric film 510 needs to be precise enough to ensure that the combined depth is within an adequate range as described herein in greater detail in relation to
At operation 412, the method of flowchart 400 can also include forming the semiconductor device by hybrid bonding the first structure with the dielectric film to a second structure without the dielectric film. In some examples, the method of flowchart 400 may include bonding the first structure 501 to a second structure 531 via hybrid bonding as shown in
The second structure 531 does not include a dielectric film. As such, when the first structure 501 and the second structure 531 are hybrid bonded together, the top surface of the dielectric film 510 of the first structure is hybrid bonded to the top surface of the second dielectric layer 538 of the second structure 531. In some examples, the dielectric film 510 and the second dielectric layer 538 are not the same material. For example, the dielectric film 510 can be silicon oxynitride and the second dielectric layer 538 can be silicon oxide. As such, the hybrid bonding of the first structure 501 and the second structure 531 can be considered hybrid bonding of asymmetric dielectrics as the dielectric film 510 and the second dielectric layer 538 are not equivalent or the same dielectric materials. In some examples, the second dielectric layer 538 of the second structure 531 can be the same material as the dielectric layer 508 of the first structure 501. For example, the second dielectric layer 538 and the dielectric layer 508 can both be silicon oxide and the dielectric film 510 can be silicon oxynitride. In another example, the second dielectric layer 538 and the dielectric layer 508 can both be silicon carbon nitride and the dielectric film 510 can be tetraethyl orthosilicate. In some examples, the second dielectric layer 538 of the second structure 531 can be a different material from the dielectric layer 508 of the first structure 501.
In some examples, bonding the first structure 501 to the second structure 531 can include using a surface activation process on the first structure 501 and/or the second structure 531. The surface activation process can include contacting the first structure 501 and/or the second structure 531 with a hydrogen-containing precursor. The surface activation process can activate the top surface of the dielectric film 510 of the first structure 501 and/or the top surface of the second dielectric layer 538 of the second structure 531 such that either one or both surfaces have been hydroxylated to have dangling hydroxylation groups. In some examples, water is then applied to the top surface of the dielectric film 510 of the first structure 501 and/or the top surface of the second dielectric layer 538 of the second structure 531.
The top surface of the dielectric film 510 of the first structure 501 and the top surface of the second dielectric layer 538 of the second structure 531 can then be aligned and contacted. When the top surface of the dielectric film 510 contacts the top surface of the second dielectric layer 438, a spontaneous bonding occurs primarily via Van der Waals bonds to set an initial bond between the top surface of the dielectric film 510 and the top surface of the second dielectric layer 538. This causes the first structure 501 and the second structure 531 to be bonded together via the top surface of the dielectric film 510 contacting the top surface of the second dielectric layer 538. The initial bond between the first structure 501 and the second structure 531 may not be the finalized bond but can be used to keep the first structure 501 and the second structure 531 aligned as additional processes are run to finalize the hybrid bond.
The combination structure of the first structure 501 and the second structure 531 can then annealed. During the annealing operation, the dielectric film 510 and the second dielectric layer 538 may further form covalent bonds increasing the bond strength between the dielectric film 510 and the second dielectric layer 538. In some examples, the water and/or the dangling hydroxylation groups assist in forming the covalent bonds between the dielectric film 510 and the second dielectric layer 538. Because the dielectric material of the dielectric film 510 and the dielectric material of the second dielectric layer 538 are different, the covalent bonds between the top surface of the dielectric film 510 and the top surface of the second dielectric layer 538 are quite strong. The strength of the covalent bonds enables the surface area of the dielectric film 510 and the second dielectric layer 538 to be a lower ratio than traditional hybrid bonding techniques. Because the dielectric film 510 and the second dielectric layer 538 are different materials, the bond strength between the dielectric film 510 and the second dielectric layer 538 can be stronger when compared to bond strength between conventional dielectric layers being hybrid bonded together. For example, the bond strength between a dielectric film 310 of silicon oxynitride and a second dielectric layer 338 of tetraethyl orthosilicate can be about 40-55% stronger when compared to bond strength between conventional dielectric layers (such as silicon oxide) being hybrid bonded together. In another example, the bond strength between a dielectric film 310 of silicon carbon nitride and a second dielectric layer 338 of tetraethyl orthosilicate can be about 60-75% stronger when compared to bond strength between conventional dielectric layers (such as silicon oxide) being hybrid bonded together.
The annealing of the combination structure can also cause the metal-containing material 522 to extrude towards the second metal-containing material 554. As previously described, the combined depth of the metal-containing material 522 (and the second metal-containing material 554 by extension) is important for the bonding of the metal-containing materials. When the combined depth is less than 5 nm or lower, subsequent annealing to bond the metal-containing material 522 and the second metal-containing material 554 may be effective as the metal-containing material 522 and the second metal-containing material 554 may be close enough to bond to each other during the annealing step of hybrid bonding. During the annealing step, the metal-containing materials from the two structures may extrude towards one another, may contact each other, and may bond. At reduced annealing temperatures according to some embodiments of the present technology, unless the dishing is sufficiently reduced, the amount of expansion may be insufficient to allow adequate coupling between the copper. By performing polishing operations according to the present technology, reduce dishing may be provided, which may improve coupling capability between substrates at reduced annealing temperatures.
Once the annealing process is completed, the first structure 501 and the second structure 531 are hybrid bonded to form a single semiconductor device or a single structure. The use of hybrid bonding enables the fabrication of complex semiconductor devices from multiple structures and form the interconnects between the structures.
It should be appreciated that the specific steps illustrated in
Here, we will describe a CMP process related to the methods, processes, and techniques related to
In some embodiments, method 600 may include providing a substrate 705 at optional operation 602 to a polishing assembly, such as the substrate 705 depicted in
As will be described in greater detail below, during the polishing in method 600, the overall removal rate of metal, such as the copper-containing layer 720, may be greater than the removal rate of dielectric material, such as the dielectric layer 710 (for example, the dielectric film 310 of
The concave shape or dish shape may feature a nadir or dish depth, respectively, that is the difference in height between the lowest point in the metal and the surface from which the feature is formed in the dielectric material, or a difference in edge height of the metal within the feature. If the nadir or dish depth is too great, the material may not be useful for certain end products. For example, copper-to-copper hybrid bonding is one such application that may be sensitive to an imprecise nadir or dish depth. In some applications of copper-to-copper hybrid bonding, if the nadir or dish depth is too great, the copper-to-copper bond may not be sufficiently strong due to limited contact with studs from mating features, or the coupling may not occur at all. In these applications substrate 705 having copper-containing layers 720 may be contacted by a secondary substrate for mating during back end of line process, and prior to an annealing operation. The dielectric material of each substrate 705, such as the dielectric layer 710, may contact the dielectric material of the other substrate such that the two separate substrates may bond into one structure. During the annealing operation, the dielectric materials may form oxide-to-oxide covalent bonds. The copper-containing layer 720 of the mating substrate may also extrude to contact the copper-containing layer 720 of the substrate 705. If the nadir or dish depth is too great, the copper-containing layer 720 may be too far recessed to connect with the copper stud during the annealing operation to contact the other copper-containing layer.
After providing the substrate 705 to the polishing assembly, the substrate 705 may be contacted with a first slurry at operation 604. As used throughout the disclosure, contact may be used interchangeably with polish, as contacting the substrate 705 with a slurry may result in a chemical operation that polishes the substrate 705. In some embodiments, at operation 604, the method 600 may include contacting the substrate 705 with a first platen in addition to the first slurry. Contacting the substrate 705 with the first slurry, and the first platen in some embodiments, may remove a first portion of the copper-containing layer 720. Operation 604 may remove the first portion of the copper-containing layer 720 such that the copper-containing layer 720 may be recessed below the liner 715, which may fully separate the regions of copper across the substrate 705 and ensure the metal does not connect discrete regions of copper across the substrate. Removing the first portion of the copper-containing layer 720 may isolate individual copper plugs within the copper-containing layer 720. The copper plugs may refer to the portions of the copper-containing layer 720 that extend into the one or more features. The first slurry may be selective to copper and removing the copper-containing layer 720 may not remove a substantial amount of the liner 715. Therefore, operation 604 may remove the copper-containing layer 720 such that the liner 715 may be at least partially exposed and that the copper-containing layer 720 may be recessed to expose the liner 715 across a surface of the substrate and/or in the one or more features of the dielectric layer 710, as shown in
At operation 606, the substrate 705 may be contacted with a second slurry. In some embodiments, at operation 606, the method 600 may include contacting the substrate 705 with a second platen in addition to the second slurry. The second slurry, and the second platen in some embodiments, may remove at least a portion of the liner 715 and/or a first portion of the dielectric layer 710. The second slurry may be selective to removing the liner 715 and may not remove a substantial amount of the copper-containing layer 720. The second slurry may be selective to oxide and nitride materials, and may remove the liner and/or the oxide material at a rate that is greater than or about 1.5:1 compared to copper, and may be greater than or about 1.6:1, greater than or about 1.7:1, greater than or about 1.8:1, greater than or about 1.9:1, greater than or about 2.0:1, greater than or about 2.1:1, greater than or about 2.2:1, greater than or about 2.3:1, greater than or about 2.4:1, greater than or about 2.5:1, greater than or about 2.6:1, greater than or about 2.7:1, greater than or about 2.8:1, greater than or about 2.9:1, greater than or about 3.0:1, or more. The second slurry may remove the portion of the liner 715 that may be exposed after operation 604. That is, the portion of the liner 715 between the dielectric layer 710 and the first portion of the copper-containing layer 720, such as the portion of the copper-containing layer 720 that was removed in operation 604, may be removed during operation 606. As the portion of the liner 715 may be removed, the copper-containing layer 720 may protrude above the dielectric layer 710 based on the selectivity of removal, as shown in
After the substrate 705 is contacted with the second slurry, the substrate 705 may be contacted with a third slurry at operation 608. In some embodiments, at operation 608, the method 600 may include contacting the substrate 705 with a third platen in addition to the third slurry. The third slurry, and the third platen in some embodiments, may remove at least a second portion of the copper-containing layer 720. The third slurry may be selective to removing the copper-containing layer 720 and may not remove a substantial amount of the dielectric layer 710. In some examples, the third slurry may remove the second portion of the copper-containing layer 720 that may be exposed after operation 604 and operation 606. That is, the copper-containing layer 720 protruding above dielectric layer 710 may be removed during operation 608 such that the copper-containing layer 720 may be recessed below the dielectric layer 710, as shown in
During contacting of the substrate 705 with the third slurry, the copper-containing material 720 may be purposefully recessed below the dielectric layer 710. Purposefully recessing, or dishing, the copper-containing material 720 below suitable levels for copper-to-copper hybrid bonding may allow for a longer duration of operation 610, which may be preferred such that greater control may be exerted over the duration of operation 610. For example, if the copper-containing material 720 is only slightly recessed below the dielectric layer 710, the duration of operation 610 may be so short that greater dishing of the copper-containing material 720 than desirable may inadvertently occur, which may cause uniformity issues, or over etching of the materials. If the copper containing material 720 is over-recessed below the dielectric layer 710, operation 610 may take longer and may be a slower process, which may allow the final nadir or dish depth to be controlled to a finer degree.
After operation 608, the copper-containing layer 720 may be characterized by a concave profile within the one or more features in the dielectric layer 710. The copper-containing layer 720 may additionally or alternatively be characterized by a dish profile having a dish depth. A nadir of the concave profile, or a dish depth of the dish profile, after operation 608 may be greater than or about 5 nm within a surface of the dielectric layer 710, and may be greater than or about 6 nm, greater than or about 7 nm, greater than or about 8 nm, greater than or about 9 nm, greater than or about 10 nm, greater than or about 6 nm, greater than or about 11 nm, greater than or about 12 nm, greater than or about 13 nm, greater than or about 14 nm, greater than or about 15 nm, or higher.
A nadir or dish depth of greater than 5 nm may be too large for copper-to-copper hybrid bonding, for example. When the nadir or dish depth is greater than or about 5 nm or higher, subsequent annealing to bond the separate copper elements may not be effective as the copper may be too far apart. During annealing, the separate copper elements may extrude towards each other, but if the nadir or dish depth is too greater, the copper elements will not bond to each other. If the nadir or dish depth is too little, such that the copper protrudes from one or both of the substrates 705, the dielectric materials of the substrates 705 will not be able to bond to one another sufficiently. Further, temperature during annealing may be limited by other components on the substrate 705, such as gallium nitride, which may have a thermal limit of about 400° C. This thermal limit may prevent the annealing from occurring at a much higher temperature than of about 400° C. By performing the coupling at lower temperatures, the amount of thermal expansion may also be reduced, which may further limit copper expansion and coupling between the copper materials. Therefore, additional processing to fine-tune the nadir or dish depth of the copper-containing layer 720 may be necessary such that a copper-to-copper bond may form when separate copper elements of two substrates 705 are contacted.
At operation 610, the substrate 705 may be contacted with a fourth slurry. In some embodiments, at operation 610, the method 600 may include contacting the substrate 705 with a fourth platen in addition to the fourth slurry. The fourth slurry, and the fourth platen in some embodiments, may remove at least a second portion of the dielectric layer 710. In some embodiments, the fourth slurry may be selective to removing the dielectric layer 710 and may not remove a substantial amount of the copper-containing layer 720. Contacting the substrate 705 with the fourth slurry and the fourth platen may further remove a third portion of the copper-containing layer 720. At operation 610, the copper-containing material 720 may be recessed such that the fourth slurry and the fourth platen may not immediately remove the copper-containing material 720. Instead, the fourth slurry and the fourth platen may remove only the dielectric layer 710 until the dielectric layer 710 is removed to a level near the copper-containing material 720. Once the dielectric layer 710 is removed to a level near the copper-containing material 720, the fourth slurry and the fourth platen may also remove the copper-containing material 720. The fourth slurry and the fourth platen may begin removing the copper-containing material 720 when the dielectric layer 710 is less than or about 2 nm higher than the copper-containing material 720, such as less than or about 1 nm. The fourth slurry may remove the dielectric layer 710 that may be extending above the copper-containing layer 720 after operation 608. That is, the dielectric layer 710 above copper-containing layer 720 may be removed during operation 610 such that the copper-containing layer 720 may be recessed below the dielectric layer 710 in a lesser amount than in operation 608, as shown in
Contacting the substrate 705 with the fourth slurry, and in some embodiments the fourth platen, may continue for a period of time of greater than or about 10 seconds. When the period of time is greater than or about 10 seconds, this may allow processing to be finely tuned to remove a desirable amount of dielectric layer 710 such that the remaining nadir of the concave profile or dish depth of the dish profile of the copper-containing layer 720 may be precise. A precise nadir of the concave profile or dish depth of the dish profile, as further described below, may be necessary for further processing and applications of the semiconductor substrate.
In some embodiments, the method 600 may include diluting the second slurry to form the fourth slurry. Diluting the second slurry to form the fourth slurry may control the rate at which dielectric layer 710 is removed when the substrate 705 is contacted with the fourth slurry. The fourth slurry may be diluted previous to operation 610 or, alternatively, on-platen during operation 610. The fourth slurry may be characterized by a slurry concentration of less than or about 50% of the second slurry, and may be characterized by a slurry concentration of less than or about 47% of the second slurry, less than or about 45% of the second slurry, less than or about 43% of the second slurry, less than or about 40% of the second slurry, less than or about 37% of the second slurry, less than or about 35% of the second slurry, less than or about 33% of the second slurry, or lower. Similar to the removal selectivity between dielectric layer 710 and copper discussed above, the fourth slurry being a dilute version of the second slurry may provide that the fourth slurry removes dielectric layer 710 and copper-containing layer 720 at a rate such that the nadir of the concave profile or dish depth of the dish profile of the copper-containing layer 720 may be precise enough for subsequent copper-to-copper hybrid bonding.
Diluting the fourth slurry may reduce a removal selectivity between dielectric layer 710 and copper. Diluting the fourth slurry may reduce a removal selectivity between dielectric layer 710 and copper of less than or about 2:1, and may produce a removal selectivity between dielectric layer 710 and copper of less than or about 1.9:1, less than or about 1.8:1, less than or about 1.7:1, less than or about 1.6:1, less than or about 1.5:1, less than or about 1.4:1, less than or about 1.3:1, less than or about 1.2:1, less than or about 1.1:1, less than or about 1.1:1, or lower. A removal selectivity between dielectric layer 710 and copper of less than or about 2:1 may provide that the fourth slurry removes dielectric layer 710 and copper-containing layer 720 at a sufficiently slow rate such that the removal operation may reduce the dishing of the copper by slowly removing the oxide and edge metal material. As shown in
Referring again to
After operation 610, the copper-containing layer 720 may again be characterized by a concave profile or a dish profile within the one or more features in the dielectric layer 710. A nadir of the concave profile, or a dish depth of the dish profile, after operation 610 may be less than or about 5 nm within a surface of the dielectric layer 710, and may be less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, less than or about 0.5 nm, or lower.
A nadir or dish depth of less than 5 nm may be small enough for copper-to-copper hybrid bonding, for example. When the nadir or dish depth is less than 5 nm or lower, subsequent annealing to bond the separate copper elements may be effective as the copper may be close enough to bond to each other during the annealing step. During the annealing step, the copper elements from separate substrates may extrude towards one another, may contact each other, and may bond. At reduced annealing temperatures according to some embodiments of the present technology, unless the dishing is sufficiently reduced, the amount of expansion may be insufficient to allow adequate coupling between the copper. By performing polishing operations according to the present technology, reduce dishing may be provided, which may improve coupling capability between substrates at reduced annealing temperatures.
Of note, the above description of the CMP process relates both to the first structure 301 and the second structure 331 of
As noted above, the CMP process described above relates to the methods, processes, and techniques related to
Here, we will describe a CMP process related to the methods, processes, and techniques related to
It should be appreciated that the specific steps illustrated in
Method 600 may or may not involve optional operations to develop the semiconductor structure to a particular polishing operation, such as one or more semiconductor processing operations to develop one or more layers of material on a substrate and clamping a substrate to a carrier head of a polishing system. It is to be understood that method 600 may be performed on any number of semiconductor structures or substrates 705 (for example, the substrate 502, metal layer 504, and/or the dielectric layer 508 of
In some embodiments, method 600 may include providing a substrate 705 at optional operation 602 to a polishing assembly, such as the substrate 705 depicted in
As will be described in greater detail below, the rate of removal in the copper-containing layer 720 may be greater towards the center of the copper in the one or more features as this copper may be a softer, bulk material. This greater rate of removal may result in a concave shape or dish shape forming in the copper during polishing. As previously explained, too much dishing may be considered a defect in polishing processing for copper-to-copper hybrid bonding applications. The concave shape or dish shape may feature a nadir or dish depth, respectively, or a difference in edge height of the metal within the feature. If the nadir or dish depth is too great, the material may not be useful for certain end products. For example, copper-to-copper hybrid bonding is one such application that may be sensitive to an imprecise nadir or dish depth. In some applications of copper-to-copper hybrid bonding, if the nadir or dish depth is too great, the copper-to-copper bond may not be sufficiently strong due to limited contact with studs from mating features, or the coupling may not occur at all. In these applications substrate 705 having copper-containing layers 720 may be contacted by a secondary substrate for mating during back end of line process, and prior to an annealing operation. The dielectric material of each substrate 705, such as the dielectric film 510 of
After providing the substrate 705 to the polishing assembly, the substrate 705 may be contacted with a first slurry at operation 604. As used throughout the disclosure, contact may be used interchangeably with polish, as contacting the substrate 705 with a slurry may result in a chemical operation that polishes the substrate 705. In some embodiments, at operation 604, the method 600 may include contacting the substrate 705 with a first platen in addition to the first slurry. Contacting the substrate 705 with the first slurry, and the first platen in some embodiments, may remove a first portion of the copper-containing layer 720. Operation 604 may remove the first portion of the copper-containing layer 720 such that the copper-containing layer 720 may be recessed below the liner 715, which may fully separate the regions of copper across the substrate 705 and ensure the metal does not connect discrete regions of copper across the substrate. Removing the first portion of the copper-containing layer 720 may isolate individual copper plugs within the copper-containing layer 720. The copper plugs may refer to the portions of the copper-containing layer 720 that extend into the one or more features. The first slurry may be selective to copper and removing the copper-containing layer 720 may not remove a substantial amount of the liner 715. Therefore, operation 604 may remove the copper-containing layer 720 such that the liner 715 may be at least partially exposed and that the copper-containing layer 720 may be recessed to expose the liner 715 across a surface of the substrate and/or in the one or more features of the dielectric layer 710, as shown in
At operation 606, the substrate 705 may be contacted with a second slurry. In some embodiments, at operation 606, the method 600 may include contacting the substrate 705 with a second platen in addition to the second slurry. The second slurry, and the second platen in some embodiments, may remove at least a portion of the liner 715 and/or a first portion of the dielectric layer 710. The second slurry may be selective to removing the liner 715 and/or the dielectric layer 710 and may not remove a substantial amount of the copper-containing layer 720. The second slurry may be selective to oxide and nitride materials, and may remove the liner and/or the oxide material at a rate that is greater than or about 1.5:1 compared to copper, and may be greater than or about 1.6:1, greater than or about 1.7:1, greater than or about 1.8:1, greater than or about 1.9:1, greater than or about 2.0:1, greater than or about 2.1:1, greater than or about 2.2:1, greater than or about 2.3:1, greater than or about 2.4:1, greater than or about 2.5:1, greater than or about 2.6:1, greater than or about 2.7:1, greater than or about 2.8:1, greater than or about 2.9:1, greater than or about 3.0:1, or more. The second slurry may remove the portion of the liner 715 that may be exposed after operation 604. That is, the portion of the liner 715 between the dielectric layer 710 and the first portion of the copper-containing layer 720, such as the portion of the copper-containing layer 720 that was removed in operation 604, may be removed during operation 606. As the portion of the liner 715 may be removed, the copper-containing layer 720 may protrude above the dielectric layer 710 based on the selectivity of removal, as shown in
After the substrate 705 is contacted with the second slurry, the substrate 705 may be contacted with a third slurry at operation 608. In some embodiments, at operation 608, the method 600 may include contacting the substrate 705 with a third platen in addition to the third slurry. The third slurry, and the third platen in some embodiments, may remove at least a second portion of the copper-containing layer 720. The third slurry may be selective to removing the copper-containing layer 720 and may not remove a substantial amount of the dielectric layer 710.
In some examples, the third slurry may remove the second portion of the copper-containing layer 720 that may be exposed after operation 604 and operation 606. That is, the copper-containing layer 720 protruding above the dielectric layer 710 may be removed during operation 608 such that the copper-containing layer 720 may be recessed below the dielectric layer 710, as shown in
During contacting of the substrate 705 with the third slurry, the copper-containing material 720 may be purposefully recessed below the dielectric layer 710. Purposefully recessing, or dishing, the copper-containing material 720 below suitable levels for copper-to-copper hybrid bonding may allow for a longer duration of operation 610, which may be preferred such that greater control may be exerted over the duration of operation 610. For example, if the copper-containing material 720 is only slightly recessed below the dielectric layer 710, the duration of operation 610 may be so short that greater dishing of the copper-containing material 720 than desirable may inadvertently occur, which may cause uniformity issues, or over etching of the materials. If the copper containing material 720 is over-recessed below the dielectric layer 710, operation 610 may take longer and may be a slower process, which may allow the final nadir or dish depth to be controlled to a finer degree.
After operation 608, the copper-containing layer 720 may be characterized by a concave profile within the one or more features in the dielectric layer 710. The copper-containing layer 720 may additionally or alternatively be characterized by a dish profile having a dish depth. A nadir of the concave profile, or a dish depth of the dish profile, after operation 608 may be greater than or about 5 nm within a surface of the dielectric layer 710, and may be greater than or about 6 nm, greater than or about 7 nm, greater than or about 8 nm, greater than or about 9 nm, greater than or about 10 nm, greater than or about 6 nm, greater than or about 11 nm, greater than or about 12 nm, greater than or about 13 nm, greater than or about 14 nm, greater than or about 15 nm, or higher.
A nadir or dish depth of greater than 5 nm may be too large for copper-to-copper hybrid bonding, for example. When the nadir or dish depth is greater than or about 5 nm or higher, subsequent annealing to bond the separate copper elements may not be effective as the copper may be too far apart. During annealing, the separate copper elements may extrude towards each other, but if the nadir or dish depth is too greater, the copper elements will not bond to each other. If the nadir or dish depth is too little, such that the copper protrudes from one or both of the substrates 705, the dielectric materials of the substrates 705 will not be able to bond to one another sufficiently. Further, temperature during annealing may be limited by other components on the substrate 705, such as gallium nitride, which may have a thermal limit of about 400° C. This thermal limit may prevent the annealing from occurring at a much higher temperature than of about 400° C. By performing the coupling at lower temperatures, the amount of thermal expansion may also be reduced, which may further limit copper expansion and coupling between the copper materials. Therefore, additional processing to fine-tune the nadir or dish depth of the copper-containing layer 720 may be necessary such that a copper-to-copper bond may form when separate copper elements of two substrates 705 are contacted.
Alternatively, after operation 608, the copper-containing layer 720 may be characterized by a concave profile, and also protrude from the one or more features in the dielectric layer 710 as seen in
At operation 610, the substrate 705 may be contacted with a fourth slurry. In some embodiments, at operation 610, the method 600 may include contacting the substrate 705 with a fourth platen in addition to the fourth slurry. The fourth slurry, and the fourth platen in some embodiments, may remove at least a second portion of the dielectric layer 710. In some embodiments, the fourth slurry may be selective to removing the dielectric layer 710 and may not remove a substantial amount of the copper-containing layer 720. Contacting the substrate 705 with the fourth slurry and the fourth platen may further remove a third portion of the copper-containing layer 720. At operation 610, the copper-containing material 720 may be recessed such that the fourth slurry and the fourth platen may not immediately remove the copper-containing material 720. Instead, the fourth slurry and the fourth platen may remove only the dielectric layer 710 until the dielectric layer 710 is removed to a level near the copper-containing material 720. Once the dielectric layer 710 is removed to a level near the copper-containing material 720, the fourth slurry and the fourth platen may also remove the copper-containing material 720. The fourth slurry and the fourth platen may begin removing the copper-containing material 720 when the dielectric layer 710 is less than or about 2 nm higher than the copper-containing material 720, such as less than or about 1 nm. The fourth slurry may remove the dielectric layer 710 that may be extending above the copper-containing layer 720 after operation 608. That is, the dielectric layer 710 above copper-containing layer 720 may be removed during operation 610 such that the copper-containing layer 720 may be recessed below the dielectric layer 710 in a lesser amount than in operation 608, as shown in
In some examples, the fourth slurry may be selective to removing the liner 715 and/or the dielectric layer 710 and may not remove a substantial amount of the copper-containing layer 720. The fourth slurry may be selective to oxide and nitride materials, and may remove the liner and/or the oxide material at a rate that is greater than or about 1.5:1 compared to copper, and may be greater than or about 1.6:1, greater than or about 1.7:1, greater than or about 1.8:1, greater than or about 1.9:1, greater than or about 2.0:1, greater than or about 2.1:1, greater than or about 2.2:1, greater than or about 2.3:1, greater than or about 2.4:1, greater than or about 2.5:1, greater than or about 2.6:1, greater than or about 2.7:1, greater than or about 2.8:1, greater than or about 2.9:1, greater than or about 3.0:1, or more.
As such, after operation 610, the dielectric layer 710 above copper-containing layer 720 and the dielectric layer 710 at around the level of the copper-containing layer may be removed during operation 610 such that the copper-containing layer 720 may protrude from the dielectric layer 710, as shown in
Contacting the substrate 705 with the fourth slurry, and in some embodiments the fourth platen, may continue for a period of time of greater than or about 10 seconds. When the period of time is greater than or about 10 seconds, this may allow processing to be finely tuned to remove a desirable amount of the dielectric layer 710 such that the remaining nadir of the concave profile or dish depth of the dish profile of the copper-containing layer 720 may be precise. A precise nadir of the concave profile or dish depth of the dish profile, as further described below, may be necessary for further processing and applications of the semiconductor substrate.
In some embodiments, the method 600 may include diluting the second slurry to form the fourth slurry. Diluting the second slurry to form the fourth slurry may control the rate at which the dielectric layer 710 is removed when the substrate 705 is contacted with the fourth slurry. The fourth slurry may be diluted previous to operation 610 or, alternatively, on-platen during operation 610. The fourth slurry may be characterized by a slurry concentration of less than or about 50% of the second slurry, and may be characterized by a slurry concentration of less than or about 47% of the second slurry, less than or about 45% of the second slurry, less than or about 43% of the second slurry, less than or about 40% of the second slurry, less than or about 37% of the second slurry, less than or about 35% of the second slurry, less than or about 33% of the second slurry, or lower. Similar to the removal selectivity between the dielectric layer 710 and copper discussed above, the fourth slurry being a dilute version of the second slurry may provide that the fourth slurry removes the dielectric layer 710 and copper-containing layer 720 at a rate such that the nadir of the concave profile or dish depth of the dish profile of the copper-containing layer 720 may be precise enough for subsequent copper-to-copper hybrid bonding.
Diluting the fourth slurry may reduce a removal selectivity between the dielectric layer 710 and copper. Diluting the fourth slurry may reduce a removal selectivity between the dielectric layer 710 and copper of less than or about 2:1, and may produce a removal selectivity between the dielectric layer 710 and copper of less than or about 1.9:1, less than or about 1.8:1, less than or about 1.7:1, less than or about 1.6:1, less than or about 1.5:1, less than or about 1.4:1, less than or about 1.3:1, less than or about 1.2:1, less than or about 1.1:1, less than or about 1.1:1, or lower. A removal selectivity between the dielectric layer 710 and copper of less than or about 2:1 may provide that the fourth slurry removes the dielectric layer 710 and copper-containing layer 720 at a sufficiently slow rate such that the removal operation may reduce the dishing of the copper by slowly removing the oxide and edge metal material. As shown in
Referring again to
It should be appreciated that the specific steps illustrated in
At operation 802, the method of flowchart 800 may include depositing a polymer on a first structure to form a polymer layer on a metal-containing material. In some examples, the polymer layer is a monolayer. As illustrated in
At operation 804, the method of flowchart 800 may include contacting the first structure with a hydrogen-containing precursor. As illustrated in
At operation 806, the method of flowchart 800 may include depositing a dielectric material via atomic layer deposition to form a dielectric film 910 on a dielectric layer 908. Depositing a dielectric material via atomic layer deposition to form a dielectric film 910 on the dielectric layer 908 can also be referred to as selectively depositing a dielectric material via atomic layer deposition to form a dielectric film 910 on the dielectric layer 908 as the deposition of the dielectric material will not likely extend to depositing the dielectric material on the polymer layer. As illustrated in
In embodiments, there may be a determination of whether a target thickness of the dielectric film 910 has been achieved following operation 806. If a target thickness of the dielectric film 910 has not been achieved, another cycle of ALD can be performed. Exemplary ranges of target thickness to discontinue further cycles of forming dielectric film 910 include less than or about 10 nm. Additional exemplary thickness ranges may include less than or about 9.5 nm, less than or about 9.0 nm, less than or about 8.5 nm, less than or about 8.0 nm, less than or about 7.5 nm, less than or about 7.0 nm, less than or about 6.5 nm, less than or about 6.0 nm, less than or about 5.5 nm, less than or about 5.0 nm, less than or about 4.5 nm, less than or about 4.0 nm, less than or about 3.5 nm, less than or about 3.0 nm, less than or about 2.5 nm, less than or about 2.0 nm, less than or about 1.5 nm, less than or about 1.0 nm, less than or about 0.5 nm, or less, including any fraction of any of the stated numbers.
As previously discussed, a nadir or dish depth of less than 5 nm may be small enough for copper-to-copper hybrid bonding, for example. When the nadir or dish depth is less than 5 nm or lower, subsequent annealing to bond the separate copper elements may be effective as the copper may be close enough to bond to each other during the annealing step. During the annealing step, the copper elements from separate substrates may extrude towards one another, may contact each other, and may bond. At reduced annealing temperatures according to some embodiments of the present technology, unless the dishing is sufficiently reduced, the amount of expansion may be insufficient to allow adequate coupling between the copper. By performing polishing operations according to the present technology, reduce dishing may be provided, which may improve coupling capability between substrates at reduced annealing temperatures.
After operation 806, the metal-containing material 922 may be recessed in the dielectric film 910, as shown in
In some examples, operations 804 and 806 are performed at a temperature less than or about 200° C. In some examples, operations 804 and 806 are performed at a temperature less than or about 250° C. In these examples, performing the operations below the temperature at which the polymer layer 928 burns off (for example, 200° C. or 250° C.) inhibits or prevents the polymer layer 928 from burning off such that the precursors do not interact or minimally interact with the metal-containing material 922.
At operation 808, the method of flowchart 800 may include removing the polymer layer. As illustrated in
In some examples, the polymer layer 928 can be burned off at a temperature greater than or about 250° C. In some examples, the polymer layer 928 can be burned off at a temperature greater than or about 300° C. Exemplary temperatures for the substrate, processing chamber, and/or precursors during burning off of the polymer layer 928 described herein may be greater than or about 250° C., greater than or about 255° C., greater than or about 260° C., greater than or about 265° C., greater than or about 270° C., greater than or about 275° C., greater than or about 280° C., greater than or about 285° C., greater than or about 290° C., greater than or about 295° C., greater than or about 300° C., or higher. In some embodiments, exemplary temperatures can range from 250° C.-300° C.
In some examples, the different operations (for example, operations 202, 204, 206, 208, 210, 212, 402, 404, 406, 408, 410, 412, 602, 604, 606, 608, 610, 802, 804, 806, 808) and subparts of different operations can be done in different chambers of system 100. When a substrate is moved from a first chamber to a second chamber, the substrate is moved without exposing the substrate to an external atmosphere. For example, operation 206 for forming a dielectric film over the dielectric layer can be done in a different chamber than operations 202 and 204 for forming the substrate, metal layer, and dielectric layer. The use of different chambers may be related to different conditions needed for different operations. For example, the chamber for etching the dielectric layer and dielectric film may require special setup due to the special nature of the dielectric material being used for the dielectric film. Similarly, the CMP processes described in relation to operations 602, 604, 606, 608, and 610 may be done in a different chamber than operations 202, 204, and 206. In another example, operation 410 for selectively depositing a dielectric film can be done in a different chamber than operations 402 and 404 for forming the substrate, metal layer, and dielectric layer. The use of different chambers may be related to different conditions needed for different operations. For example, the chamber for selectively depositing a dielectric film may require special setup due to the special nature of the dielectric material being used for the dielectric film as opposed to the materials related to the deposition of the metal layer and/or dielectric layer. Similarly, the CMP processes described in relation to operations 602, 604, 606, 608, and 610 may be done in a different chamber than operations 402, 404, and 406.
As used herein, the terms “about” or “approximately” or “substantially” may be interpreted as being within a range that would be expected by one having ordinary skill in the art in light of the specification.
In the foregoing description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of various embodiments. It will be apparent, however, that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.
The foregoing description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the foregoing description of various embodiments will provide an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of some embodiments as set forth in the appended claims.
Specific details are given in the foregoing description to provide a thorough understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary detail in order to avoid obscuring the embodiments.
Also, it is noted that individual embodiments may have been described as a process which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may have described the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed, but could have additional steps not included in a figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.
The term “computer-readable medium” includes, but is not limited to portable or fixed storage devices, optical storage devices, wireless channels and various other mediums capable of storing, containing, or carrying instruction(s) and/or data. A code segment or machine-executable instructions may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.
Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine readable medium. A processor(s) may perform the necessary tasks.
In the foregoing specification, features are described with reference to specific embodiments thereof, but it should be recognized that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used individually or jointly. Further, embodiments can be utilized in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the specification. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive.
Additionally, for the purposes of illustration, methods were described in a particular order. It should be appreciated that in alternate embodiments, the methods may be performed in a different order than that described. It should also be appreciated that the methods described above may be performed by hardware components or may be embodied in sequences of machine-executable instructions, which may be used to cause a machine, such as a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the methods. These machine-executable instructions may be stored on one or more machine readable mediums, such as CD-ROMs or other type of optical disks, floppy diskettes, ROMs, RAMS, EPROMs, EEPROMs, magnetic or optical cards, flash memory, or other types of machine-readable mediums suitable for storing electronic instructions. Alternatively, the methods may be performed by a combination of hardware and software.
