Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communication

Abstract

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.

Description

BACKGROUND

In communication systems, information may be transmitted from one physical location to another. Furthermore, it is typically desirable that the transport of this information is reliable, is fast and consumes a minimal amount of resources. One of the most common information transfer mediums is the serial communications link, which may be based on a single wire circuit relative to ground or other common reference, multiple such circuits relative to ground or other common reference, or multiple circuits used in relation to each other. An example of the latter utilizes differential signaling (DS). Differential signaling operates by sending a signal on one wire and the opposite of that signal on a paired wire; the signal information is represented by the difference between the wires rather than their absolute values relative to ground or other fixed reference.

Differential signaling enhances the recoverability of the original signal at the receiver, over single ended signaling (SES), by cancelling crosstalk and other common-mode noise, but a side benefit of the technique is that the Simultaneous Switching Noise (SSN) transients generated by the two signals together is nearly zero; if both outputs are presented with an identical load, the transmit demand on its power supply will be constant, regardless of the data being sent. Any induced currents produced by terminating the differential lines in the receiver will similarly cancel out, minimizing noise induction into the receiving system.

There are a number of signaling methods that maintain the desirable properties of DS while increasing pin-efficiency over DS. Many of these attempts operate on more than two wires simultaneously, using binary signals on each wire, but mapping information in groups of bits.

Vector signaling is a method of signaling. With vector signaling, pluralities of signals on a plurality of wires are considered collectively although each of the plurality of signals may be independent. Each of the collective signals is referred to as a component and the number of plurality of wires is referred to as the “dimension” of the vector. In some embodiments, the signal on one wire is entirely dependent on the signal on another wire, as is the case with DS pairs, so in some cases the dimension of the vector may refer to the number of degrees of freedom of signals on the plurality of wires instead of the number of wires in the plurality of wires.

With binary vector signaling, each component takes on a coordinate value (or “coordinate”, for short) that is one of two possible values. As an example, eight SES wires may be considered collectively, with each component/wire taking on one of two values each signal period. A “code word” of this binary vector signaling is one of the possible states of that collective set of components/wires. A “vector signaling code” or “vector signaling vector set” is the collection of valid possible code words for a given vector signaling encoding scheme. A “binary vector signaling code” refers to a mapping and/or set of rules to map information bits to binary vectors.

With non-binary vector signaling, each component has a coordinate value that is a selection from a set of more than two possible values. A “non-binary vector signaling code” refers to a mapping and/or set of rules to map information bits to non-binary vectors.

Examples of vector signaling methods are described in Cronie I, Cronie II, Cronie III, and Cronie IV.

BRIEF SUMMARY

In accordance with at least one embodiment of the invention, processes and apparatuses provide for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices, requiring low pin count and providing low power utilization. Controller-side and memory-side embodiments of such channel interfaces are disclosed. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a ternary vector signaling code wherein each wire signal has one of three values.

This Brief Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Brief Summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. Other objects and/or advantages of the present invention will be apparent to one of ordinary skill in the art upon review of the Detailed Description and the included drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments in accordance with the present disclosure will be described with reference to the drawings. Same numbers are used throughout the disclosure and figures to reference like components and features.

FIG. 1 is a block diagram of an example system comprised of a controller, host interface, memory interface, and memory, in accordance with at least one embodiment of the invention.

FIG. 2 is a block diagram detailing the controller side of the controller-to-memory interface, in accordance with at least one embodiment of the invention.

FIG. 3 is a timing diagram for the controller-to-memory interface packet start timing from the aspect of the memory controller, in accordance with at least one embodiment of the invention.

FIG. 4 is a block diagram detailing the memory side of the controller-to-memory interface, in accordance with at least one embodiment of the invention.

FIG. 5 is a timing diagram for the controller-to-memory packet start timing from the aspect of the memory device, in accordance with at least one embodiment of the invention.

FIG. 6 describes a use of the Kandou H4 Line Code as part of a communications protocol in accordance with at least one embodiment of the invention.

FIG. 7 illustrates a block diagram of a Gearbox, in accordance with some embodiments.

DETAILED DESCRIPTION

Specialized memory subsystems of modern computer systems utilize dedicated memory controllers to manage access, optimize performance, and improve utilization and reliability. Interconnections between these memory controllers and memory devices must operate at high speeds, delivering reliable and low latency data transfers, while under significant constraints in terms of available pin count and power utilization. Moreover, the design for interfaces to such interconnections is further constrained by implementation requirements, as controller devices are typically implemented using high speed logic processes, while memory devices such as DRAM rely on specialized processes optimized for high storage density and low leakage, but possibly not for fast logic speed. Thus, a successful memory-to-controller interconnection architecture must support implementation in multiple semiconductor processes.

In accordance with at least one embodiment of the invention, this disclosure describes a PHY (Physical Layer interface) and a Link Layer interface for both the controller and memory sides of such an interconnection, without presumption of limitation to the single embodiment provided as a descriptive example. Similarly, a packet format for communication of addressing, data transfer, and control operations using such an interconnection and interfaces is described, as one descriptive use example of a low-latency, pin- and power-efficient embodiment of the invention.

For purposes of description, this document uses the name “Bee” to describe this controller-to-memory interconnection system and/or a device embodying an interface for such interconnection. Without loss of generality, the physical interface between memory controller and memory device is herein described as utilizing point-to-point wire connections between integrated circuit devices, optionally including multidrop bussed interconnection of multiple memory devices and a single controller. Other embodiments of the invention may utilize other physical interfaces, including optical, inductive, capacitive, or electrical interconnection, and/or having more complex connection topologies.

FIG. 2 is a block diagram detailing the controller side of the controller-to-memory interface, in accordance with at least one embodiment of the invention.

The Bee Controller side is composed of the Bee_C_Link link layer interface and the Bee_C_PHY physical layer interface. FIG. 2 is a block diagram detailing the controller side of the controller-to-memory interface, in accordance with at least one embodiment of the invention.

The Bee_C_PHY Hard IP packet physical layer interface is implemented in a 60 nm (or so) process and is a low power ensemble coded interface that can deliver 1.5 GB/s in each direction throughput over six high-speed physical wires: four bidirectional data wires and two clock wires. It is optimized for low power. In one embodiment, the interface is a four-wire H4 ensemble mode delivering a 3b4w interface, including six high speed wires total including a differential clock. The interface uses 33% transmitted line power as compared to differential signaling scheme and operates at 4 Gbaud/sec symbol rate, and providing either 1 GB/s or 1.5 GB/s throughput in each direction. In some embodiments, the interface has 3.6 mw/Gbps (43.6 mw) worst case power dissipation (12 Gb/s), and is configured to have 0.50 mm square footprint for interface elements in integrated circuit design. The device interfaces to 1-4 memory devices and connects to the link layer interface (Bee_C_LINK). It may be configured with a 24 bit parallel interface from Bee_C_LINK to PHY and use Command and Address multiplexing implemented in Bee_C_LINK.

In some embodiments, the Package and Channel either does not use equalization or utilizes simple equalization. In general, no skew tolerance circuits required, and a 50 mm FR4 trace maximum channel length may be used. Some embodiments utilize in-package MCM. The interfaces are wire-bond compatible, and may have a tileable layout to allow additional memory interfaces to be implemented on the controller. The pin-out may be chosen to minimize EMI.

In some embodiments, the transmitter sends a half rate clock at either 1.33 GHz or 2 GHz, and data is sent to be aligned to center of rising clock edge, thus no clock and data recovery (CDR) circuit is needed in the RAM. The transmitter slew rate is controlled. The device accepts transaction start and end interface signals from Bee_C_LINK and the device selection may also be input from Bee_C_LINK. In some embodiments, there is a Gearbox selector from the 24 bit system interface to the 3 bit encoder input. The transmitter also encodes a 3-bit input plus start input into a H4 symbol. FIG. 7 illustrates an exemplary encoder that may be included in the Gearbox. As shown in FIG. 7, a Gearbox 720 may make use of a Hadamard matrix H of size n=4. The input 705 of the transformer includes n−1=3 signals which enter the balancer 710. The output of the balancer 710 includes n=4 signals which enter the encoder 715. A task of the encoder 715 is to perform the multiplication of the Hadamard matrix H with the vector of n=4 signals leaving the balancer 710. The output of the encoder 715 corresponds to the vector that is formed by multiplying H with the vector of signals leaving the balancer 710. The output of the encoder 715 is fed to the signal path driver drivers 725 which possibly perform additional amplification and/or filtering. The transmitter may drive four single ended chip select signals at half speed, and is configured in some embodiments to drive the H_IDLE H4 symbol before the chip select is asserted and then the H_START H4 symbol after the chip select is asserted.

The receiver may be configured with on-die channel termination, and the application of the termination may be determined by the statically wired external pin. In some embodiments, the Bee_C_LINK delivers the receive transaction timing to the PHY, and the Bee_C_LINK delivers the device selection. Further, the decoder may be configured to transform H4 symbols into tri-bits plus the start symbol. The Gearbox transforms the tri-bits plus the start and end packet indications into a 24-bit interface to Bee_C_LINK. Some embodiments may include a Phase aligner aligned via a boot-time routine. The receiver may have low power consumption when all input wires are at the common mode.

Power Management functions may include (i) power-down by removal of power from entire memory device; (ii) power-up transition is not very fast (milliseconds); (iii) standby-Active transitions controlled by input from the controller; and/or (v) additional moderate power standby mode.

Manufacturing aspects may include (i) marginable manufacturing loopback BERT test that is useful in-system between Bee devices; (ii) JTAG 1149.6 boundary and internal scan; (iii) 1 KV HBM and 250 V CDM ESD tolerance; and/or (iv) capable of being fully characterized & extended life tested post-silicon.

FIG. 3 is a timing diagram for the controller-to-memory interface packet start timing from the aspect of the memory controller, in accordance with at least one embodiment of the invention.

The Bee_C_PLL Hard IP packet physical layer interface is implemented in a 60 nm (or so) process. It is optimized for low power. The phase locked loop (PLL) may be configured as a 22 mw shareable PLL with 100 MHz input and 2 GHz multi-phase output. In some embodiments the PLL may be shared amongst multiple interfaces and/or may be integrated with other device functions.

The Bee_C_Link Hard IP physical layer interface is implemented in a 60 nm (or so) process that multiplexes and times the data for the Bee_C_PHY. It is optimized for low power. It may be configured to connect to a RAM controller containing an AXI bus controller. It also connects to the Bee_C_PHY.

System-side Transmit accepts full memory transactions from the memory controller and formats those transactions into Kandou Memory Link (KML) packets. The interface is configured to interoperate with at least a subset of the OFNI command set to operate the bi-directional request-response data bus. It may be configured to postpends a link CRC, and also to drive those packets into a FIFO along with the start and end of packet information. The interface may manage the Tx FIFO occupancy by pessimistically back-pressuring the bus interface taking into account the input from the receive side. In some embodiments, the interface implements a link layer retry protocol, at the cost of increased latency.

The PHY-side transmit includes a 24 bit interface out of the FIFO to the Bee_C_PHY, and also drives the start and end of packet timing into the gearbox in the Bee_C_PHY.

The PHY-side receive circuit provides the timing windows for the Bee_C_PHY to look for the H_START packet indication, and also provides the Bee_C_PHY and end of packet signal derived from the P Length field. The receive circuit also accepts a 24 bit input from the interface from Bee_C_PHY and drives it into the FIFO. It may be configured to use cut-thru operations for low latency. The receiver may also check the link CRC and writes the results into the FIFO.

The system-side receive circuit may be configured to manage the Rx FIFO occupancy by pessimistically back-pressuring the Tx side bus interface taking into account both the Rx-FIFO needs of incoming transactions and the existing Rx-FIFO occupancy. It may also be configured to perform response matching of returned packets and handling link layer packets via a non-FIFO path. The receiver circuit also formats the KML responses back into memory transactions suitable for input to the AXI bus controller. In some embodiments, it may also implement a link layer retry protocol, at the cost of latency.

The Bee RAM side comprises the Bee_M_PHY physical layer interface and the Bee_M_Link.link layer interface. FIG. 4 is a block diagram detailing the memory side of this controller-to-memory system, in accordance with at least one embodiment of the invention.

The matching Bee_M_PHY Hard IP (RAM Side) packet physical layer interface is implemented in a DRAM-optimized process that is equivalent to a 100 to 130 nm CMOS process (1 to 1.2 V Vdd), is low power, and uses one of Kandou's vector signaling codes. It is optimized for low power. The differences from the controller-side interface include the following.

Some embodiments may include an additional processor interface accessible from the link. It may be configured to connect to link layer IP (Bee_M_LINK). It may be configured to consume 6.4 mw/Gbps (76.9 mw) worst case power dissipation (12 Gb/s), and be implemented with a 0.95 mm square of implementation footprint for interface elements in DRAM integrated circuit design. The transmitter sends data on each rising edge of the received clock, and the transmitter slew rate is controlled. Multi-drop support is provided via the combination of the chip select assertion and the enumeration. The H_IDLE signal line is driven within a fixed interval after chip select assertion qualified with the enumeration, while the H_START signal line is driven within a fixed interval after the H_IDLE signal line is driven. The Bee_M_LINK delivers a 24 bit interface to the PHY and provides transaction timing to PHY. In some embodiments, it is configured in accordance with a 4:1 parallel implementation.

The Receiver is configured with on-die termination, and a statically wired external pin determines whether termination is applied. In some embodiments, no PLL or CDR is required, as it is configured with DDR forwarded differential clock. When the chip select is asserted, the PHY circuit is configured to finds the H_IDLE and H_START H4 symbols. The decoder transforms H4 symbols into tri-bits plus the start symbol. In addition, the Gearbox transforms the tri-bits plus the start symbol into a 24-bit interface to Bee_M_LINK. The circuit is configured for low power consumption when all input wires are floating at the common mode, and may include a 1:4 parallel implementation.

Power management functions may include (i) power down by removal of power and/or (ii) fast resumption low power standby mode with the state of the wires controlled, rapid detection and indication of activity on the clock, and standby-active transitions via a state machine based on the clock activity.

Manufacturing aspects include (i) marginable manufacturing loopback BERT test that is useful in-system between Bee devices; (ii) JTAG 1149.6 boundary and internal scan; (iii) 1 KV HBM and 250 V CDM ESD tolerance; and (iv) fully characterized and extended life tested post-silicon.

FIG. 5 is a timing diagram for the controller-to-memory packet start timing from the aspect of the memory device, in accordance with at least one embodiment of the invention.

The Bee_M_Link Hard IP physical layer interface is, in some embodiments, implemented in a 60 nm process that multiplexes and times the data for the Bee_M_PHY. It is optimized for low power. The interface connects to the Bee_M_PHY and to the memory controller inside of the RAM.

The PHY-side receive circuit provides the timing windows for the Bee_M_PHY to look for the H_START packet indication and provides the Bee_M_PHY and end of packet signal derived from the P Length field. It may be configured to accept a 24 bit input from the interface from Bee_M_PHY and drives it into the FIFO, and may use cut-thru operation for low latency. The receive circuit writes the results of the CRC calculation after the packet into the FIFO.

The memory-side receiver circuit manages the 24 bit wide Rx FIFO occupancy by pessimistically back-pressuring the Tx side bus interface taking into account Rx-FIFO needs of incoming transactions and the existing Rx-FIFO occupancy. The receiver also: (i) performs response matching of returned packets; (ii) handles link layer packets via a non-FIFO path; (iii) formats the KML responses back into bus transactions suitable for handling by the memory controller; and/or (iv) implements a link layer retry protocol, at the cost of increased latency.

The memory-side transmit circuit is configured to (i) accept full bus transactions from the memory controller; (ii) format those transactions into Kandou Memory Link (KML) packets; (iii) is compatible with the OFNI command set to operate the bi-directional request-response data bus; (iv) prepends a fixed link layer preamble; (v) postpends a link CRC; (vi) drives those packets into a 24 bit wide FIFO along with the start and end of packet information; (vii) manages the Tx FIFO occupancy by pessimistically back-pressuring the bus interface taking into account the input from the receive side; and in some embodiments implements a link layer retry protocol, at the cost of increased latency.

The PHY-side transmit circuit drives a 24 bit wide interface out of the FIFO to the Bee_M_PHY and drives the start and end of packet timing into the gearbox in the Bee_M_PHY.

The enumeration function automatically enumerates a daisy chain of memory devices using the ENi and ENo pins to extend the addressability of the chip selects as per the OFNI specification or an extension of that specification.

A gearbox according to present embodiments can be succinctly described in terms of a class of matrices known to those of skill in the art as Hadamard matrices. A Hadamard matrix of size n is a square matrix of size n which contains as entries either +1 or −1, and for which any two different rows are orthogonal. A square matrix in which different rows are orthonormal is known as an orthogonal matrix in the literature. Therefore, a Hadamard matrix with normalized rows and columns is an orthogonal matrix. In what follows, the term “Hadamard matrix” may be read as “Hadamard matrix with normalized rows and/or columns” unless clearly contradicted by context. FIG. 6 describes a use of the Kandou H4 Line Code as part of a communications protocol in accordance with at least one embodiment of the invention. KH4C is a 3b4w (3 bits over 4 wires) code appropriate for narrow high performance interfaces. The H4 code is generated using a size n=4 Hadamard matrix. It is a balanced code of four symbols per codeword, one symbol taking on the value +1 or −1, with the remaining three symbols taking on the value −⅓ or +⅓, respectively.

Another embodiment of the invention supports a 3b5w (3-bits conveyed over 5 wires) code where each data value may be encoded as either of two equivalent codewords. Alternation of such equivalent codewords provides an effective return clock, making receipt of a sequence of such code words self-clocking. Another embodiment provides two additional clock lines that a selected memory device uses to reflect its received clock back to the controller, similarly providing synchronization of symbols transmitted in the memory-to-controller direction.

The following is a description of the Kandou Memory Link (KML) protocol, in accordance with at least one embodiment of the invention. KML is a protocol appropriate for a high-speed, narrow interface to a memory device. It supports variable-size block write and block read operations at arbitrary start addresses, with data transfer integrity verified using a cyclic-redundancy check code. The protocol may also optionally support access to link-level command/information packets for use by additional control and monitoring applications.

The memory side send a response packet or a link layer packet.

In the memory to controller direction, a 1 symbol preamble is added: H_START.

In the controller to memory direction, a 1 symbol preamble is added: H_START.

Write Packets

• • P_Command—8 bits
  • P_SeqNum—4 bits (TBD—if retry)
  • P_Tag—4 bits
  • P_Address—32 bit
  • P_Length—8 bits
  • P_Data—8 to 2048 bits
  • P_CRC—8 to 32 bitsRead Request Packets
  • P_Command—8 bits
  • P_SeqNum—4 bits (TBD—if retry)
  • P_Tag—4 bits
  • P_Address—32 bit
  • P_Length—8 bits
  • P_CRC—8 to 32 bitsResponse Packets
  • P_Command—8 bits
  • P_SeqNum—4 bits (TBD—if retry)
  • P_Tag—4 bits
  • P_Length—8 bits
  • P_Data—8 to 2048 bits
  • P_CRC—8 to 32 bitsLink Layer Packets (for some embodiments)
  • P_Command—8 bits
  • P_Info—16 bits
  • P_CRC—8 to 32 bits

In one embodiment, a collection of interconnection signal lines; a memory-controller interface circuit; a link layer signaling protocol control circuit; a physical layer signaling protocol control circuit that maps symbols of a vector signaling code to the collection of interconnection signal lines and provides timing information for symbol communication, wherein the link layer signaling protocol circuit provides bidirectional address and data transmission to the memory controller interface circuit. The collection of interconnection signal lines may take the form of four bidirectional data lines and two clock lines. In a further embodiment, the physical layer signaling protocol control circuit communicates three data bits over the four data lines using a balanced code of symbols having four distinct signal levels. The collection of interconnection signal lines may additionally comprise two clock lines carrying a return clock signal to the controller device. In yet a further embodiment, the collection of interconnection lines comprises five bidirectional data lines and two clock lines. In a further embodiment, the physical layer signaling protocol control circuit may communicate three data bits over five lines, and the link layer protocol circuit is self-clocking in the memory-to-controller direction.

In a further embodiment, a method comprises: transmitting messages from a memory controller using a vector signaling code, the messages selected from the group consisting of a memory write, a memory read, and a status interrogation command; receiving a response message in the form of one or more vector signaling codes, the response message selected from the group consisting of a memory write complete, a memory read result, a status response, and an error report message, wherein each transmitted message and received response message comprises a series of vector signaling code words, each code word communicated as symbols carried as physical signals on a set of lines, and wherein consecutive code words of each message is synchronized by a symbol clock also carried as physical signals on the set of lines. The memory write and memory read operations may be configured to access a contiguous block of memory of a specified size at a specified memory address. The set of lines in one embodiment comprises four bidirectional data lines and two unidirectional symbol clock lines. In a further embodiment, the vector signaling code communicates three binary bits on four lines using a balanced code of four levels. In other embodiments, the series of vector signaling words corresponding to the response message is self-clocking. The self-clocking may be obtained by receipt of a physical clock signal at the memory controller. The self-clocking may be obtained by alternation of redundant code words of the vector signaling code representing the same data value.

Claims

1. A method comprising: obtaining memory transaction data at a link layer memory interface, and responsively forming a high-speed memory link packet having a set of multi-bit words;storing each multi-bit word of the high-speed memory link packet as an entry in a first-in-first-out (FIFO) buffer;obtaining, at an orthogonal signaling physical layer, a multi-bit word from the FIFO buffer, and consecutively encoding portions of the obtained multi-bit word into data codewords of an H4 balanced vector signaling code, wherein each data codeword comprises four symbols, one symbol having a value ±1 and a remaining three symbols having a value ∓⅓, respectively;transmitting a pre-designated packet start codeword of the balanced vector signaling code via high-speed data wires of a multi-wire bus; andtransmitting each data codeword via the high-speed data wires of the multi-wire bus.

2. The method of claim 1, further comprising formulating link layer packets at a first link layer controller for transmission over the orthogonal signaling physical layer to a second link layer controller.

3. The method of claim 1, further comprising transmitting chip-select signals via chips-select wires of the multi-wire bus.

4. The method of claim 1, further comprising transmitting a clock signal over a pair of high-speed clock wires of the multi-wire bus.

5. The method of claim 1, further comprising transmitting a pre-designated idle codeword prior to transmitting the pre-designated packet start codeword.

6. The method of claim 1, wherein the high-speed memory link packet is one of a memory write packet and a memory read request packet.

7. The method of claim 1, wherein the high-speed memory link packet is a memory read result packet.

8. The method of claim 1, wherein packet start and packet end timing is further obtained at the physical layer from the link layer memory interface.

9. An apparatus comprising: a link layer memory interface configured to obtain memory transaction data, to responsively form a high-speed memory link packet having a set of multi-bit words, and to store each multi-bit word of the high-speed memory link packet as an entry in a first-in-first-out (FIFO) buffer; andan orthogonal signaling physical layer configured to: obtain a multi-bit word from the FIFO buffer, and to consecutively encode portions of the obtained multi-bit word into data codewords of an H4 balanced vector signaling code, wherein each data codeword comprises four symbols, one symbol having a value ±1 and a remaining three symbols having a value ∓⅓, respectively;transmit a pre-designated packet start codeword of the balanced vector signaling code via high-speed data wires of a multi-wire bus; andtransmit each data codeword via the high-speed data wires of the multi-wire bus.

10. The apparatus of claim 9, wherein the link layer is configured to formulate link layer packets at a first link layer controller for transmission over the orthogonal signaling physical layer to a second link layer controller.

11. The apparatus of claim 9, wherein the orthogonal signaling physical layer is further configured to transmit chip-select signals via chips-select wires of the multi-wire bus.

12. The apparatus of claim 9, wherein the orthogonal signaling physical layer is further configured to transmit a clock signal over a pair of high-speed clock wires of the multi-wire bus.

13. The apparatus of claim 9, wherein the orthogonal signaling physical layer is further configured to transmit a pre-designated idle codeword prior to transmitting the pre-designated packet start codeword.

14. The apparatus of claim 9, wherein the high-speed memory link packet is one of a memory write packet and a memory read request packet.

15. The apparatus of claim 9, wherein the high-speed memory link packet is a memory read result packet.

16. The apparatus of claim 9, wherein the physical layer is further configured to obtain packet start and packet end timing from the link layer memory interface.