Patent Application
20200052106
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and more specifically, to semiconductor devices having gates of varying width but with substantially the same gate metal heights.
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region.
In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative finFET device, which is a 3-dimensional structure. More specifically, in a finFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a trigate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the finFET device only has a dual-gate structure.
In the continuing effort to increase the capabilities of semiconductor devices, designers have created semiconductor devices having varying gate widths among the gates of a single device. However, changing the widths of gates may lead to variations in the height of gate metal between narrower and wider gates, with wider gates typically having undesirably low gate metal heights relative to narrower gates.
The present disclosure may address and/or at least reduce one or more of the problems identified above.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally, the present disclosure is directed to various methods, apparatus, and systems for forming semiconductor devices comprising gates of different widths with substantially uniform gate metal heights.
In one embodiment, the present disclosure relates to a method comprising forming a first gate having a first width and comprising a first work function metal; a first liner disposed over the first liner; a first gate metal over the first liner and having a first height above the height of the first work function metal; and a first spacer on the sides of the first gate and having a first spacer height greater than the first height; forming a second gate having a second width and comprising a second work function metal; a second liner disposed over the second liner; and a second gate metal over the second liner and having a second height, wherein the first width is less than the second width and the first height is greater than the second height; and a second spacer on the sides of the second gate and having a second spacer height greater than the second height; filling a first region between the first spacer on the sides of the first gate and above the first gate metal with a third spacer material up to at least the first spacer height; depositing conformally the third spacer material in a second region between the second spacer on the sides of the second gate, and on a top of the second gate metal up to a third spacer material height below the second spacer height; removing the third spacer material from the top of the second gate metal, wherein the first gate metal remains covered by the third spacer material; adding metal to the second gate metal, thereby raising the top of the second gate metal to about the first height.
In one embodiment, the present disclosure relates to a semiconductor device, comprising a first gate having a first width and comprising a first work function metal (WFM); a first liner disposed over the first WFM; a first gate metal over the first liner and having a first height above the height of the first work function metal; a first spacer on the sides of the first gate and having a first spacer height greater than the first height; a first pinch-off spacer over the first WFM, the first liner, and the first gate metal to above the first height and below the first spacer height; and a second gate having a second width greater than the first width, and comprising a second WFM; a second liner disposed over the second WFM; a second gate metal over the second liner and having substantially the first height; a second spacer on the sides of the second gate and having a second spacer height greater than the first height; and a first conformal spacer over the second WFM and the second liner.
In one embodiment, the present disclosure relates to a system comprising a semiconductor device processing system to manufacture a semiconductor device; and a processing controller operatively coupled to the semiconductor device processing system, the processing controller configured to control an operation of the semiconductor device processing system; wherein the semiconductor device processing system is adapted to implement a method referred to above.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present subject matter will now be described with reference to the attached Figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
Embodiments herein provide for semiconductor devices comprising gates of different widths with substantially uniform gate metal heights.
Turning now to
The first gate metal 128 has a first height above the substrate 110 of H1, and the second gate metal 138 has a second height above the substrate 110 of H2. The first height H1 is above the height of the first work function metal 124. Similarly, the second height H2 is above the height of the second work function metal 134. The first height is greater than the second height, i.e., H1>H2.
The first gate 120 also comprises a first spacer 122 on the sides of the first gate 120. The first spacer 122 has a first spacer height SH1 greater than the first height H1. Accordingly, between the first spacer 122 on the sides of the first gate 120 and above the first WFM 124, the first liner 126, and the first gate metal 128 is defined a first region 121. Similarly, the second gate 130 also comprises a second spacer 132 on the sides of the second gate 130. The second spacer 132 has a second spacer height SH2 greater than the second height H2. Accordingly, between the second spacer 132 on the sides of the second gate 130 and above the second WFM 134, the second liner 136, and the second gate metal 138 is defined a second region 131.
The first spacer 122 and the second spacer 132 also define the widths of the first gate 120 (width W1) and the second gate 130 (width W2). The width of the second gate 130 is greater than the width of the first gate 120, i.e., W2>W1.
The various structures 120, 122, 124, 126, 128, 132, 134, 136, and 138 depicted in
In one embodiment, the first liner 126 and the second liner 136 both comprise titanium nitride.
In one embodiment, the first spacer 122 and the second spacer 132 both comprise a low-k dielectric spacer.
In one embodiment, the first gate metal 128 and the second gate metal 138 may be formed by overfilling regions 121 and 131 with metal, e.g., tungsten; performing chemical-mechanical polishing (CMP) to reduce the tops of the metal to no higher than the first and second spacers 122, 132; and recessing the metal to yield the formations depicted in
Although
Also,
The third spacer material 223, 233 may comprise any material known to the person of ordinary skill in the art. In one embodiment, the third spacer material 223, 233 may comprise silicon nitride (SiN). In another embodiment, the third spacer material 223, 233 may form an etch stop layer (ESL).
Deposition of the third spacer material 223, 233 may involve any known technique. In one embodiment, the deposition process conditions are selected such that filling the first region 121 with the third spacer material 223 and depositing conformally the third spacer material 233 in the second region 131 may be performed simultaneously. In another embodiment, one of the first gate 120 and the second gate 130 may be masked and the third spacer material 223 or 233 deposited in the first or second region 121 or 131 of the unmasked gate, followed by unmasking, masking the other gate, and depositing the third spacer material 223 or 233 in the newly-unmasked gate.
Process conditions for the partial removal of the third spacer material 223, 233 may be routinely selected by the person of ordinary skill in the art having the benefit of the present disclosure and need not be discussed in detail.
Techniques for selective growth of a metal on the second gate metal 138 may be routinely selected by the person of ordinary skill in the art having the benefit of the present disclosure and need not be discussed in detail.
The cap spacer 627, 637 may comprise any appropriate material. In one embodiment, the cap spacer 627, 637 comprises SiN. Alternatively or in addition, the cap spacer 627, 637 may comprise the third spacer material 323, 333.
Thereafter, one or more additional processes known to the person of ordinary skill in the art (not shown) may be performed to produce a final product comprising the structure of
In one embodiment, as shown in
a first gate 120 having a first width W1 and comprising a first work function metal 124; a first liner 126 disposed over the first work function metal 124; a first gate metal 128 over the first liner 126 and having a first height H1 above the height of the first work function metal 124; a first spacer 122 on the sides of the first gate 120 and having a first spacer height SH1 greater than the first height H1; and a first pinch-off spacer 323 over the first WFM 124, the first liner 126, and the first gate metal 128 to above the first height H1 and below the first spacer height SH1; and
a second gate 130 having a second width W2 greater than the first width W1, and comprising a second work function metal 134; a second liner 136 disposed over the second WFM 134; a second gate metal 438 over the second liner 136 and having substantially the first height H1; a second spacer 132 on the sides of the second gate 130 and having a second spacer height SH2 greater than the first height H1; and a first conformal spacer 333 over the second WFM 134 and the second liner 136.
In one embodiment, the first liner 126 and the second liner 136 comprise titanium nitride.
In one embodiment, the first pinch-off spacer 323 and the first conformal spacer 33 comprise SiN.
In one embodiment, the semiconductor device 100 further comprises a first cap spacer 627 above the first pinch-off spacer 323, up to the first spacer height SH1; and a second cap spacer 637 above the second gate metal 438 and adjacent the first conformal spacer 333, up to the second spacer height SH2.
In one embodiment, the first cap spacer 627 comprises SiN.
In one embodiment, the second cap spacer 637 comprises SiN.
In one embodiment, the first cap spacer 627, the second cap spacer 637, the first pinch-off spacer 323, and the first conformal spacer 333 comprise the same spacer material.
In one embodiment, the first liner and the second liner comprise titanium nitride.
The method 600 additionally comprises filling (at 620) a first region between the first spacer on the sides of the first gate and above the first gate metal with a third spacer material up to at least the first spacer height. The method 600 further comprises depositing conformally (at 630) the third spacer material in a second region between the second spacer on the sides of the second gate, and on a top of the second gate metal up to a third spacer material height below the second spacer height. The filling (at 620) and the depositing conformally (at 630) may be performed sequentially or simultaneously.
In one embodiment, the third spacer material comprises silicon nitride (SiN).
The method 600 also comprises removing (at 640) the third spacer material from the top of the second gate metal, wherein the first gate metal remains covered by the third spacer material.
The method 600 further comprises adding (at 650) metal to the second gate metal, thereby raising the top of the second gate metal to about the first height.
In one embodiment, the method 600 further comprises filling (at 655) the first region and the second region with a cap spacer. In one embodiment, the cap spacer comprises SiN. Alternatively or in addition, the cap spacer may comprise the third spacer material.
Turning now to
The system 700 of
The semiconductor device processing system 710 may comprise various processing tools, such as etch process stations, photolithography process stations, oxide deposition process stations, CMP process stations, epitaxy (EPI) process stations, etc. The semiconductor device processing system 710 may also comprise one or more metrology tools. One or more of the processing steps performed by the processing system 710 may be controlled by the processing controller 720. The processing controller 720 may be a workstation computer, a desktop computer, a laptop computer, a tablet computer, or any other type of computing device comprising one or more software products that are capable of controlling processes, receiving process feedback, receiving test results data, performing learning cycle adjustments, performing process adjustments, etc. Generally, the processing controller 720 may communicate to the semiconductor device processing system 710 via an interface.
The semiconductor device processing system 710 may produce semiconductor devices on a medium, such as silicon wafers. More particularly, the semiconductor device processing system 710 may produce semiconductor devices as described above.
The production of integrated circuits by the device processing system 710 may be based upon the circuit designs provided by the integrated circuits design unit 740. The processing system 710 may provide processed integrated circuits/devices 77 on a transport mechanism 750, such as a conveyor system. In some embodiments, the conveyor system may be sophisticated clean room transport systems that are capable of transporting semiconductor wafers.
In some embodiments, the items labeled “715” may represent individual wafers, and in other embodiments, the items 715 may represent a group of semiconductor wafers, e.g., a “lot” of semiconductor wafers. The semiconductor device 715 may comprise a transistor, a capacitor, a resistor, a memory cell, a processor, and/or the like.
The system 700 may be capable of performing analysis and manufacturing of various products involving various technologies. For example, the system 700 may design and manufacturing-data for manufacturing devices of CMOS technology, Flash technology, BiCMOS technology, power devices, memory devices (e.g., DRAM devices), NAND memory devices, and/or various other semiconductor technologies.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
