Patent Application
20160260606
1. Field of the Invention
The present disclosure generally relates to methods of forming a masking pattern and to a semiconductor device structure and, more particularly, to the formation of masking patterns enabling sub-nominal lines/spaces and contact patterns for advanced semiconductor device structures, e.g., memory cell arrays.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. In particular, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes significantly smaller than 1 μm, the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 100 nm or less. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs may be made much smaller than any discreet circuit composed of separate independent circuit components. Indeed, the majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors or MOSFETs, occasionally also simply referred to as MOS transistors, and passive elements, such as resistors, e.g., diffusion resistors, and capacitors, integrated on a semiconductor substrate within a given surface area. Typical present-day ICs involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a MOSFET is that of an electronic switching element, controlling a current through a channel region provided between two junction regions which are referred to as source and drain. The control of the conductivity state of the channel region is achieved by means of a gate electrode being disposed over the channel region and to which gate electrode a voltage relative to source and drain is applied. In common planar MOSFETs, the channel region extends in a plane between source and drain. Generally, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of the channel is changed and switching between a conducting state or “ON-state” and a non-conducting state or “OFF-state” may be achieved. It is important to note that the characteristic voltage level at which the conductivity state changes (usually called the “threshold voltage”) therefore characterizes the switching behavior of the MOSFET and it is generally an issue to keep variations in the threshold voltage level low when implementing a desired switching characteristic. However, with the threshold voltage depending nontrivially on the transistor's properties, e.g., materials, dimensions, etc., the implementation of a desired threshold voltage value during fabrication processes involves careful adjustment and fine tuning during the fabrication processes, which makes the fabrication of complex semiconductor devices by advanced technologies more and more difficult.
At present, the scaling of semiconductor devices down to smaller sizes follows so-called Moore's Law according to which the number of transistors in a dense integrated circuit doubles approximately every two years. Originally intended as a prediction to describe the trend of the development of computing hardware in an article by Gordon Moore in 1965, Moore's Law became a long-term guide which the semiconductor industry follows as a roadmap for planning and setting targets in research and development of advanced semiconductor devices. Until today, Moore's Law drives the scaling of semiconductor devices and structures down to continuously decreasing sizes.
The continued scaling constantly raised new challenges which are met by increasingly complex technical solutions developed in the art. For example, patterning small parts of a thin film or the bulk of a substrate at advanced technology nodes has been achieved by photolithography, which became an important technique used in micro fabrication processes. In photolithography, an image is projected onto a substrate by one or more optical masks via a light sensitive chemical photoresist deposited on the substrate. Then, a series of chemical treatments either engraves the exposure pattern into, or enables the position of a new material in the desired pattern upon, the material underneath the photoresist. However, the continued scaling following Moore's Law has led, at present, to the issue of printing half pitches of about 20 nm or less. As contemporary photolithographical techniques do not allow printing of such small pitches, a satisfactory solution does not exist in the art.
It is, therefore, desirable to provide for methods of forming a masking pattern that complies with a lithography roadmap to continue the scaling of integrated circuit structures down to smaller technology scales in accordance with Moore's Law. Furthermore, it is desirable to provide a semiconductor device structure that has a printed half pitch of about 20 nm or less.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
In various aspects, the present disclosure provides for methods of forming a masking pattern and a semiconductor device structure, wherein printed half pitches of dimensions which are substantially smaller than a minimum feature size that may be reached by known lithography techniques and/or known lithography tools may be formed, such as, for example, dimensions of about 24 nm or less.
According to a first aspect of the present disclosure, a method of forming a masking pattern is provided. In accordance with some illustrative embodiments herein, the method comprises forming an unpatterned mask layer over a semiconductor device structure provided in and on an upper surface of a semiconductor substrate, and patterning the unpatterned mask layer for forming the masking pattern over the semiconductor device structure. Herein, the unpatterned mask layer is patterned by forming a dummy pattern on the unpatterned mask layer, wherein the dummy pattern has at least one recess, forming a first sidewall spacer structure adjacent to sidewalls of the at least one recess, wherein a first width dimension of the first sidewall spacer structure is smaller than half a width of the recess, removing the dummy pattern while maintaining the first sidewall spacer structure over the unpatterned mask layer, forming a second sidewall spacer structure on the first sidewall spacer structure, wherein a second width dimension of the second sidewall spacer structure is smaller than half the width of the recess, removing the first sidewall spacer structure while maintaining the second sidewall spacer structure over the unpatterned mask layer, and etching the unpatterned mask layer in alignment with the second sidewall spacer structure.
In a second aspect of the present disclosure, a method of forming a masking pattern having a minimum size that is substantially smaller than a minimum feature size (F) to be reached by lithography techniques is provided. In accordance with some illustrative embodiments herein, the method includes forming an unpatterned hard mask layer over a plurality of gate electrodes provided on an upper surface of a semiconductor substrate, forming an insulating material layer on the unpatterned hard mask layer, wherein the insulating material layer has a thickness which is substantially greater than the minimum feature size F, and patterning the unpatterned mask layer so as to form a plurality of masking strips extending along one of a parallel and a transverse direction relative to the gate electrodes such that the masking pattern is formed over the semiconductor device structure, wherein the plurality of masking strips has a width dimension which is substantially smaller than the minimum feature size F. Herein, the unpatterned hard mask layer is patterned by forming a dummy pattern on the unpatterned hard mask layer, comprising patterning the insulating material layer, wherein the dummy pattern has at least one recess, forming a first sidewall spacer structure adjacent to sidewalls of the at least one recess by depositing a polysilicon layer on the dummy pattern and anisotropically etching the polysilicon layer, wherein a first width dimension of the first sidewall spacer structure is smaller than half a width of the recess, removing the dummy pattern while maintaining the first sidewall spacer structure over the unpatterned mask layer, forming a second sidewall spacer structure with a second width dimension on the first sidewall spacer structure by depositing a nitride layer on the first sidewall spacer structure and anisotropically etching the nitride layer, wherein the second width dimension is smaller than half the width of the recess, removing the first sidewall spacer structure by selectively etching the first sidewall spacer structure such that the second sidewall spacer structure is maintained over the unpatterned mask layer, and etching the unpatterned mask layer in alignment with the second sidewall spacer structure.
In accordance with a third aspect of the present disclosure, a semiconductor device structure is provided. In accordance with some illustrative embodiments herein, the semiconductor device structure includes at least one gate electrode disposed on an upper surface of a semiconductor substrate, and a plurality of source contacts and a plurality of drain contacts formed on respective source and drain regions aligned to the at least one gate electrode, wherein a first separation between two neighboring source contacts of the plurality of source contacts is smaller than about 24 nm and a second separation between two neighboring drain contacts of the plurality of drain contacts is smaller than about 24 nm.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present disclosure will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details which are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary or customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition shall be expressively set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The present disclosure relates to a method of forming a semiconductor device and to semiconductor devices, wherein the semiconductor devices are integrated on or in a chip. In accordance with some illustrative embodiments of the present disclosure, the semiconductor devices may substantially represent FETs, e.g., MOSFETs or MOS devices. When referring to MOS devices, the person skilled in the art will appreciate that, although the expression “MOS device” is used, no limitation to a metal-containing gate material and/or to an oxide-containing gate dielectric material is intended.
Semiconductor devices of the present disclosure concern devices which are fabricated by using advanced technologies, i.e., the semiconductor devices are fabricated by technologies applied to approach technology nodes smaller than 100 nm, for example, smaller than 50 nm or smaller than 35 nm. The person skilled in the art will appreciate that, according to the present disclosure, ground rules smaller or equal to 45 nm may be imposed. The person skilled in the art will appreciate that the present disclosure proposes semiconductor devices with structures of minimal length dimensions and/or width dimensions smaller than 100 nm, for example, smaller than 50 nm or smaller than 35 nm. For example, the present disclosure may provide semiconductor devices fabricated by using 45 nm technologies or below, e.g., 28 nm or even below.
The person skilled in the art will appreciate that semiconductor devices may be fabricated as P-channel MOS transistors or PMOS transistors and N-channel transistors or NMOS transistors; both types of transistors may be fabricated with or without mobility-enhancing stressor features or strain-inducing features. It is noted that a circuit designer can mix and match device types, using PMOS and NMOS devices, stressed and unstressed, to take advantage of the best characteristics of each device type as they best suit the semiconductor device under design.
In the following, various illustrative embodiments of the present disclosure will be explicitly described with regard to the enclosed figures, wherein a masking pattern of sub-nominal spacings is formed over an upper surface of a substrate.
With regard to
In accordance with illustrative embodiments of the present disclosure, a patterning process for patterning the insulating material layer 30 is described, wherein a dummy pattern (see reference numeral 36 in
According to
Referring to
Next, as illustrated in
Referring to
Subsequent to the second process step 44, or alternatively as a part of the second process step 44, the auxiliary mask portions 34 are stripped off.
Referring to
Subsequently, an etching process 46 may be performed for anisotropically etching the first sidewall spacer forming material layer 52 so as to form a plurality of first sidewall spacers 54 for forming a first sidewall spacer structure (see reference numeral 56 in
In accordance with some illustrative embodiments of the present disclosure, the dummy pattern may be removed by a wet etch step (not illustrated) which is configured for selectively removing the insulating material of the dummy mask portions 38 relative to the material of the side plurality of first sidewall spacers 54. In some explicit examples herein, the dummy pattern 36 may be removed by a wet removal of oxide material using DHF which is highly selective to silicon material and TiN in case that the first sidewall spacer structure 56 is formed by an oxide material, while the dummy pattern 36 is provided by a silicon material, whereas the unpatterned mask layer 20 is formed by TiN.
Referring to
Referring to
In accordance with some illustrative embodiments of the present disclosure, the second sidewall spacer forming material layer 62 is subsequently exposed to an anisotropic etch step (not illustrated) for anisotropically etching the second sidewall spacer forming material layer 62 such that a second sidewall spacer structure 66 (see
Subsequently to forming the second sidewall spacer structure 66, the first sidewall spacer structure 56 may be removed by a wet etch process, wherein the first sidewall spacer structure 56 is selectively etched relative to the second sidewall spacer structure 66, where the unpatterned mask layer 20 is used as an etch stop. In accordance with an explicit example herein, the wet etch step may comprise one of TMAH and ammonia.
Referring to
Next, an anisotropic etch step (not illustrated) is performed, e.g., an RIE etch step, to open the unpatterned mask layer 20 in accordance with the second spacer structure 66 and, after the second spacer structure 66 is removed, a masking pattern 22 formed by masking strips 24 is obtained over the semiconductor device structure 10, as shown in
With regard to some illustrative applications of the above described patterning technique, the person skilled in the art will appreciate that the afore described patterning of the unpatterned mask layer 20 may be applicable to equal line space patterns, for example for memory arrays, such as SRAM/DRAM.
With regard to
Subsequent to forming the masking pattern 120, the trenches 130 between the masking strips 120 are subsequently filled with a contact forming material, e.g., tungsten (W), as indicated by the broken lines in
Referring to
Next, the masking strips 120 are removed and the contact forming material 132 is polished down to the gate electrodes 110, for example, using the gate electrodes 110 as an indicator for the end of the polishing process, such that the gate electrodes 110 separate the contact forming material 132 in
With regard to
With regard to
Referring to
Next, as illustrated in
Next, a contact structure 345 comprising silicide regions and contacts, e.g., formed by tungsten (W), may be formed within the contact trenches 344 in accordance with conventional techniques, resulting in the semiconductor device structure 340 as illustrated in
The person skilled in the art will appreciate that, in accordance with the application illustrated in
In a second lithographical step, one or more large windows, e.g., the windows 320 and 330 in
The person skilled in the art will appreciate that the present disclosure provides, in various aspects, for an enabler for a half pitch patterning down to dimensions of about 24 nm and less, e.g., 8 nm. The person skilled in the art will appreciate that the techniques as proposed by the present disclosure allow for a lowering of costs for exposure tools.
In some aspects of the present disclosure, a smart spacer technique is used for patterning half pitches that are three times smaller than smallest printable sizes. The person skilled in the art will appreciate that the disclosed techniques allow for an extension of the usage of lower resolution litho equipment at vary small scales.
In accordance with some aspects of the present disclosure, a pitch fragmentation process (i.e., the patterning process as described above with regard to
In accordance with some applications of the present disclosure, this technique allows patterning of gates in memory arrays with a resolution of F/3, where F denotes a nominal feature size such as a minimum feature size that may be reached by known lithography techniques and/or known lithography tools, e.g., about 24 nm or less. In some illustrative examples, contacts can be patterned by using the techniques as presented by the present disclosure and a 20 LP like approach may be performed to create a block-and-line mask for forming long hole contacts.
The explicit embodiments as described above employ forming two sidewall spacer structures when patterning the unpatterned mask layer over the semiconductor device structure. This does not pose any limitation on the present disclosure and the person skilled in the art will appreciate that more than two sidewall spacers may be formed instead. For example, a third sidewall spacer structure may be formed subsequent to forming the second sidewall spacer structure and before patterning the unpatterned mask layer, the third sidewall spacer having a third width which is substantially smaller than half of a width of recesses defined by the second sidewall spacer structure. Herein, the third sidewall spacer structure is formed adjacent to the second sidewall spacer structure so as to iterate the step of forming the second sidewall spacer structure adjacent to the first sidewall spacer structure.
In summary, the present disclosure provides for methods of forming a masking pattern and a semiconductor device structure, wherein printed half pitches having dimensions which are substantially smaller than a minimum feature size that may be reached by known lithography techniques and/or known lithography tools may be formed, such as, for example, of about 24 nm or less. In accordance with a first aspect of the present disclosure, a method of forming a masking pattern is provided, wherein an unpatterned mask layer is formed over a semiconductor device structure provided in and on an upper surface of a semiconductor substrate, and the unpatterned mask layer is patterned for forming the masking pattern over the semiconductor device structure. Herein, the unpatterned mask layer is patterned by forming a dummy pattern on the unpatterned mask layer, wherein the dummy pattern has at least one recess, forming a first sidewall spacer structure adjacent to sidewalls of the at least one recess, wherein a first width dimension of the first sidewall spacer structure is smaller than half a width of the recess, removing the dummy pattern relative to the first sidewall spacer structure, forming a second sidewall spacer structure on the first sidewall spacer structure, wherein a second width dimension of the first sidewall spacer structure is smaller than half the width of the recess, removing the first sidewall spacer structure relative to the second sidewall spacer structure, and etching the unpatterned mask layer in alignment with the second sidewall spacer structure.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is, therefore, evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
