Patent Application
20250118547
This application claims foreign priority to European Patent Application EP 23202146.9, filed Oct. 6, 2023, the content of which is incorporated by reference herein in its entirety.
The disclosed technology generally relates to methods of forming memory structures for nonvolatile memory devices, and in particular a three-dimensional flash memory.
The bit density in the 3D NAND flash memory road map increases every year. Thus far, the increase has been enabled by increasing the number of stacked memory cells along the vertical dimension. However, this route is becoming increasingly difficult and costly. Hence, there is increasing interest in techniques for scaling the cells along the vertical dimension. Vertical scaling (“z-pitch scaling”) is achieved by reducing the thickness of the layers in the layer stack, e.g., the word line (gate) layers and oxide inter-gate spacer layers.
Z-scaling however results in a reduced inter-cell separation which in turn leads to an increased parasitic capacitance between the word lines of the cells, thus making it difficult to control the cell-to-cell interference. Increased cell-to-cell interference may degrade the performance related parameters of the memory device, notably decrease the threshold voltage and increase increased the program voltage. It is therefore desirable for scalable techniques allowing better control over the cell-to-cell interference.
An efficient way to control cell-to-cell interference can be to introduce air gap structures between the gate/word line layers. It is therefore an object of the disclosed technology to provide methods of forming a memory structure suitable for a nonvolatile memory such as a 3D NAND flash memory, for example, allowing the forming of air gap structures in the memory structure also at aggressive z-pitch scaling.
Hence, according to an aspect of the disclosed technology, there is provided a method of forming a memory structure for a 3D NAND flash memory, the method comprising:
Thus, the method according to one aspect of the disclosed technology enables forming of a memory structure comprising discrete lateral memory stacks in each gate/word line layer (or equivalently, for each memory cell), wherein the lateral memory stacks are vertically separated by air gap structures. Due to the low dielectric constant (low k) of an air gap structure, inter-cell interference may hence be efficiently reduced. For example, an air gap structure has a lower k than oxides suitable for forming the inter-gate spacer layers.
The term “air gap structure” can herein mean a space or void enclosed by a pair of lateral memory stacks, the liner layer and an inter-gate spacer layer. The space may contain air and/or other ambient gases which may be present in the process environments in which the steps of the method are performed, or traces of non-polymer material (e.g., in solid-phase, forming a porous structure in the second recessed areas) remaining from the converted dummy layers.
A further advantage of one aspect is that the air gaps separate the charge trap layer. Generally, the charge trap layer has been deposited as a continuous layer along the sidewall of the memory hole in the layer stack. The reduced inter-cell separation entailing z-scaling results in a reduced inter-cell separation which in turn may reduce the retention performance of a continuous charge trap layer. By one aspect of the disclosed technology however, a separate discrete charge trap layer can be formed for each gate layer, thereby enabling an improved retention performance of each cell.
The use of a thermal treatment process, can allow reliable conversion of the dummy layers into air gap structures (e.g., removing the dummy layers by heating to form air gap structures) although the dummy layers may be enclosed by the lateral memory stacks, the liner layer and the inter-gate spacer layers. Meanwhile, in some embodiments, the liner layer can ensure that subsequently deposited materials do not fill the air gap structures.
A possible challenge introduced by the presence of dummy layers in the layer stack, is that materials which may be converted into air gap structures (e.g., polymers) may have poor compatibility with other materials of the layer stack. For instance, dummy materials suitable for the thermal treatment process may introduce mechanical stress into the layer stack, or reduce adhesion between the stacked layers. As the inter-gate space layers according to one aspect of the disclosed technology are partially preserved in the layer stack (e.g., implying that the dummy layers and thus the air gap structures are locally introduced between the lateral memory stacks), there is however a reduced risk of the dummy layers introducing structural defects into the layer stack. Consider as an illustrative comparative example, a hypothetical process comprising completely replacing the inter-gate space layers by dummy layers, wherein the risk of deformation or delamination of the layer stack would be considerably greater than in the disclosed technology.
Moreover, by forming the air gap structure prior to the channel layer, the thermal budget for the channel layer formation may be selected without considering the risk of inadvertently affecting the dummy layers (e.g., the thermal budget for poly-Si deposition may exceed the decomposition temperature for many suitable polymer dummy materials).
Reference is herein made to “first recessed areas” and “second recessed areas”. It is to be noted that “first” and “second” here are mere labels, and do not imply any particular temporal order of forming the respective recessed areas. That is, as will become apparent from the following disclosure, in some embodiments the “first” recessed areas may be formed prior to the “second” recessed areas, and in some embodiments the “second” recessed areas may be formed prior to the “first” recessed areas. As used herein, reference to “each” of a particular element (e.g., “each first recessed area”) may refer to two or more of the elements, and may or may not refer to every one of the elements in the structure. For example, “each first recessed area” may refer to individual ones of a plurality of first recessed areas and not necessarily every single first recessed area in the structure.
In some embodiments, the dummy layers are formed of a polymer-comprising material. There exists many polymers that may be efficiently and reliably removed using a thermal treatment process, e.g., by evaporation, leaving substantially no organic residues in the layer stack (although non-polymer traces may remain, as discussed below). Other processes are possible, such as volatile oxide formation or chemical etching.
In some embodiments the treatment process removes the polymer-comprising material of the dummy layers from the second recessed areas.
Optionally, trace amounts of dummy material (e.g., decomposed dummy material) may remain in the second recessed areas to form the air gap structures, such as a silicate compound.
In some embodiments, the liner layer is deposited at a temperature below a temperature causing conversion of the dummy layers into the air gap structures. Accidental conversion of the dummy layers before the second recessed areas are “sealed off” by the liner layer may thus be avoided.
In some embodiments, the liner layer is formed of a low thermal oxide (LTO). A low thermal oxide (e.g., LTO silicon dioxide or LTO SiO2) may be reliably deposited without triggering conversion of the dummy layers.
In some embodiments, a thickness of the liner layer is in a range of 1-4 nm, or 1-2 nm.
In some embodiments, a lateral depth of the second recessed areas is such that the air gap structures undercut at least the charge trap material of the lateral memory stacks. The air gap structures may thus be formed at the locations where they have the greatest impact on cell-to-cell interference, namely between the charge trap material in some embodiments.
In some embodiments, the lateral depth of the second recessed areas is such that the air gap structures further undercut the blocking oxide of the lateral memory stacks. The air gap structures may thus extend laterally along the full (lateral) thickness dimension of the lateral memory stack, further reducing inter-cell interference in some embodiments.
In some embodiments, the gate layers are sacrificial gate layers and the method further comprises, subsequent to forming the air gap structures, replacing the sacrificial gate layers by a replacement metal gate stack (e.g., removing and replacing the sacrificial gate layers with a replacement metal gate stack). The sacrificial gate layers may be removed by etching back the sacrificial gate layers from a second hole in the layer stack, different from the memory hole, and subsequently forming a replacement metal gate stack replacing the sacrificial gate layers.
In some embodiments, a lateral depth of the second recessed areas is such that the air gap structures undercut the charge trap material of the lateral memory stacks but do not undercut the blocking oxide of the lateral memory stacks. The air gap structures may thus be protected during the replacement metal gate stack deposition.
In some embodiments, the method further comprises depositing a further liner layer of a dielectric material in the second recessed areas prior to forming the dummy layers, wherein the further liner layer is used as an etch stop layer when replacing the sacrificial gate layers by the replacement metal gate stack. The air gap structures may thus be protected during the replacement metal gate stack deposition, even if the second recessed areas undercut also the blocking oxide.
In some embodiments, the second recessed areas are formed after forming the lateral memory stacks in the first recessed areas. A risk of the deposition of the blocking oxide and charge trap material depositions causing accidental conversion of the dummy layers before the second recessed areas are “sealed off” by the liner layer may thus be avoided in some embodiments.
In some embodiments, the method further comprises, prior to forming the first recessed areas:
Accordingly, rather than depositing a continuous charge trap layer and subsequently “cutting” the charge trap layer into a number of discrete portions by etching, some embodiments of the method “directly” deposits the discrete charge trap layers using an area selective deposition process (ASD), wherein the sacrificial layers are used to define deposition-inhibiting areas (“non-growth areas”). In some embodiments, deposition of the charge trap material in areas vertically between the gate layers may hence be avoided, thus obviating the need for cutting the charge trap material by etching. By obviating the need for etching, the thickness dimension of the charge trap layers (as seen along the lateral dimension) may be precisely controlled by maintaining the growth conditions of the selective deposition until a target thickness has been achieved. The preceding discussion can apply correspondingly to the blocking oxide.
Since the inter-gate spacer layers are formed of a dielectric material (typically an oxide) it is envisaged that depositing the blocking oxide and the charge trap material selectively in the first recessed areas (e.g., in vertical levels of the gate layers) without any appreciable concurrent deposition on the inter-gate spacer layers would be challenging. However, by etching back the inter-gate spacer layers to form the initial recessed areas in the sidewall and then forming sacrificial layers in the initial recessed areas (e.g., filling the initial recessed areas with sacrificial layer material), a considerably improved area selectivity may be achieved. For example, the sacrificial layer material may be selected to facilitate the area selective deposition without regard to its suitability in a finished functional memory device. In general, the sacrificial layers may be formed of a sacrificial layer material selected to be deposition-inhibiting for the selective deposition of the blocking oxide.
A further advantage of the deposition-inhibiting properties of the sacrificial layers is that the risk for pinch-off of the first recessed areas by either the blocking oxide or charge trap material deposition may be avoided in various embodiments.
In some embodiments, the initial recessed areas are the second recessed areas and the method further comprises, after forming the lateral memory stacks, removing the sacrificial layers from the second recessed areas by etching from the memory hole and thereafter forming the dummy layers in the second recessed areas.
Hence, a re-growth of the inter-gate spacer layers in the initial recessed areas and subsequent lateral etch back thereof to form the second recessed areas may in this approach be omitted. The sacrificial layers may thus, in addition to their deposition-inhibiting function while forming the lateral memory stacks, act as a place-holder for the dummy layers, and thus be replaced by the dummy layers after forming the lateral memory stacks. In this approach, the sacrificial layer material may further be selected to be etchable selectively to the charge trap material, the blocking oxide and the material of the gate layer (e.g., the sacrificial layer material may be etched at a greater rate than each of the charge trap material, the blocking oxide and the material of the gate layer) so as to allow a selective removal of the sacrificial layers from the initial/second recessed areas.
Alternatively, in some embodiments, the method further comprises, after forming the lateral memory stacks:
Thereby, the materials of the sacrificial layers and the dummy layers may be selected independently from one another (e.g., to separately optimize the deposition-inhibiting properties of the sacrificial layers and the conversion of the dummy layers into air gap structures), and to form the initial recessed areas and the second recessed areas with respective depths, chosen independently from one another. In this approach, the sacrificial layer material may further be selected to be etchable selectively to the charge trap material, the blocking oxide and the material of the gate layer (e.g., the sacrificial layer material may be etched at a greater rate than each of the charge trap material, the blocking oxide and the material of the gate layer) so as to allow a selective removal of the sacrificial layers from the initial recessed areas. In some embodiments, the sacrificial layers are metal oxide-layers, such as aluminum oxide (Al2O3) or titanium oxide (TiO2) layers, metal-nitride layers, such as aluminum nitride (AlN) or titanium nitride (TiN) layers, metal layers, such as cobalt (Co), ruthenium (Ru), copper (Cu), tungsten (W) or molybdenum (Mo) layers, or carbon-comprising layers, such as amorphous carbon or organic spin-on layers. Sacrificial materials of any of these types facilitates process control as they tend to define deposition-inhibiting surfaces with respect to ASD of the blocking oxide and the charge trap material. These sacrificial materials further enable etch selectivity with respect to the charge trap material, the blocking oxide and the material of the gate layer (be it polysilicon or a nitride-comprising material). This can apply for example, to carbon-comprising layers, such as amorphous carbon or organic spin-on layers.
Alternatively, in some embodiments, the initial recessed areas are the second recessed areas and the sacrificial layers are the dummy layers. The dummy layers (e.g., formed of a polymer-comprising material) may thus both be used as a deposition-inhibiting layer to facilitate ASD of the blocking oxide and the charge trap material, and subsequently be converted into air gap structures by the thermal treatment process.
This and other aspects of the disclosed technology will now be described in more detail, with reference to the appended drawings showing embodiments of the disclosed technology.
Embodiments of methods of forming a memory structure for a 3D NAND flash memory, such as a 3D-Gate-All-Around-NAND (3D GAA NAND), will now be described with reference to the drawings. The drawings are only schematic and that the relative dimensions of some structures and layers may be exaggerated and not drawn on scale. Rather the dimensions may be adapted for illustrational clarity and to facilitate understanding of the following description. When present in the figures, the indicated axes X, Y and Z consistently refer to a first horizontal or lateral direction, a second horizontal or lateral direction, and a vertical direction, respectively. As used herein, the terms “horizontal” and “lateral” can refer to directions parallel to a supporting substrate of the memory structure. The term “vertical” can refer to a direction parallel to a normal direction of the substrate, for example, transverse to the substrate.
The layer stack 10 is formed over a substrate 2 and comprises an alternating sequence (e.g., vertically alternating sequence) of gate layers 14 and inter-gate spacer layers 12. In some instances, a memory hole 4 may be formed through the layer stack 10.
The substrate 2 may be any substrate, suitable for semiconductor processing and for supporting a memory structure for a 3D NAND flash memory. The substrate 2 may for instance be a silicon (Si) substrate, a germanium (Ge) substrate or a silicon-germanium (SiGe) substrate. Other examples include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate or a silicon-germanium-on-insulator (SiGeOI) substrate.
The gate layers 14 may be nitride-comprising layers, such as silicon nitride (SiN) layers, thus forming sacrificial gate layers 14 intended to be replaced by a replacement metal gate (RMG) stack in subsequent process steps. The gate layers 14 may also be functional gate layers, e.g., highly doped polysilicon-comprising layers.
The inter-gate spacer layers 12 may be oxide-comprising layers, such as silicon dioxide (SiO2) layers or another suitable inter-layer dielectric (e.g., a dielectric having a low dielectric constant k or a dielectric of low-k). The inter-gate spacer layers 12 are arranged in the layer stack 10 to provide vertical separation between the memory cells/word lines of the memory device which is to be formed.
The layer stack 10 may be formed by interchangeably depositing layers of gate material (e.g., nitride) and inter-gate spacer material (e.g., oxide) using deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).
The inter-gate spacer layer 12 and the gate layers 14 may be formed in numbers in accordance with the intended number of stacked memory cells of the memory device. It is to be noted that the number of layers 12, 14 of the illustrated layer stack 10 merely is a non-limiting example and that the method disclosed herein is compatible with stacks of memory cells of essentially any number currently used, or contemplated, in the industry, such as 64, 128, 256 or greater.
The inter-gate spacer layers 12 and the gate layers 14 may be formed with a respective layer thickness in a range of 5-25 nm, as an example. A z-pitch of the layer stack 10 (for example, the combined thickness of one inter-gate spacer layer and one gate layer 14) may be in a range from about 15 nm to 45 nm or less than 15 nm to 45 nm.
The layer stack 10 may, as shown, further comprise a capping layer in the form of a semiconductor layer 16, deposited on top of the top-most inter-gate spacer layer 12. The semiconductor layer 16 may for instance be formed of Si.
After depositing the layers 12 and 14 (and optionally 16) of the layer stack 10, a memory hole 4 may be patterned in the layer stack 10, e.g., by a lithography and etching process. While
While not shown in
In
The gate layers 14 are laterally etched back (along the X-axis) selectively to the inter-gate spacer layers 12 such that the first recessed areas 18 are formed between the inter-gate spacer layers 12. For example, each recessed area/recess of the first recessed areas 18 is formed between a pair of inter-gate spacer layers 12. Due to the circumferential extension of the sidewall about the memory hole 4, the first recessed areas 18 may extend circumferentially about the memory hole 4. In the example of a circular memory hole 4, the first recessed areas 18 may be annular.
The gate layers 14 may be etched back using an etching process adapted to etch the gate layers 14 selectively to the inter-gate spacer layers 12. For instance, the etching process may be adapted to etch (for example, remove) the material (e.g., the nitride material) of the gate layers 14 selectively to the material (e.g., the oxide material) of the inter-gate spacer layers 12, for example, such that the gate layers 14 may be laterally etched back without causing any substantial etch-back of the inter-gate spacer layers 12. The etching process may be applied to the sidewall of the layer stack 10 via the memory hole 4. Any suitably selective etching process, wet or dry, providing a sufficient lateral etching component with respect to the gate layers 14 (such as an isotropic etching process) may be used.
The first recessed areas 18 may be formed with a depth (along the X-axis) matching an intended lateral thickness of the lateral memory stacks 19 to be formed at the levels of the gate layers 14 (see for example,
Each lateral memory stacks 19 can form, as shown, a discrete lateral memory stack 19 in a respective recessed area 18, each comprising a discrete blocking oxide portion or layer (which in the following also may be referred to using reference sign 20) and a discrete charge trap material portion or layer (which in the following also may be referred to using reference sign 21).
The blocking oxide 20 may be formed with a lateral thickness (along the X-axis) in a range of 4-12 nm. The charge trap material (or layers) 21 may be formed with a lateral thickness (along the X-axis) in a range of 4-8 nm. More generally, the blocking oxide 20 and the charge trap material 21 may fill the first recessed areas 18 such that the inner end surfaces of the charge trap material (layers) 21 (e.g., facing inwardly with respect to the memory hole 4) are substantially flush with the inner end surfaces of the inter-gate spacer layers 12. The lateral memory stacks 19 may thus fill the lateral depth of the first recessed areas 18, thereby restoring the sidewall surrounding the memory hole 4 to a substantially straight profile.
The blocking oxide 20 may comprise or be SiOx (e.g., SiO2), or some other oxide material suitable to be used as a blocking oxide. The charge trap material 21 may comprise or be SiN (e.g., Si3N4), or some other nitride material suitable to be used as a charge trap material.
The lateral memory stacks 19 may be formed using both area-selective and non-area-selective deposition techniques.
Using a non-area selective deposition technique, the forming of the lateral memory stacks 19 may comprise conformally depositing (e.g., using ALD) an initial blocking oxide layer in each first recessed area 18 and to cover the sidewall of the memory hole 4, e.g., including the inner end surfaces of the inter-gate spacer layers 12. The initial blocking oxide layer may subsequently be laterally etched back (e.g., using an isotropic etch) such that the inner end surfaces of the inter-gate spacer layers 12 at the sidewall of the memory hole 4 are exposed and discrete portions of the blocking oxide remain in the first recessed areas 18. Subsequently, an initial charge trap material layer may be conformally deposited (e.g., using ALD) in a corresponding fashion in each first recessed area 18 (e.g., on the blocking oxide 20) and to cover the sidewall of the memory hole 4, e.g., including the inner end surfaces of the inter-gate spacer layers 12. The initial charge trap material layer may subsequently be laterally etched back (e.g., using an isotropic etch) such that the inner end surfaces of the inter-gate spacer layers 12 at the sidewall of the memory hole 4 are exposed and discrete portions of the charge trap material 21 remain in the first recessed areas 18, e.g., on the blocking oxide 20.
Using an area-selective deposition technique, the lateral memory stacks 19 may be formed by selectively depositing, in the first recessed areas 18, the blocking oxide 20 and, subsequently, the charge trap material 21. Hence, both the blocking oxide 20 and the charge trap material 21 are selectively deposited, wherein the inter-gate spacer layers 12 define deposition-inhibiting areas (non-growth areas) for the selective deposition of the blocking oxide 20 and the charge trap material 21. As the blocking oxide 20 and the charge trap material 21 are selectively deposited in the first recessed areas 18, the blocking oxide 20 may be directly deposited to define a discrete blocking oxide layer in each first recessed area 18 and the charge trap material 21 may be directly deposited to form a discrete charge trap layer in each first recessed area 18. The blocking oxide 20 may be deposited using any deposition process (e.g., an ALD or CVD process) allowing area-selective deposition of the blocking oxide 20 (e.g., SiO2) such that the blocking oxide 20 is deposited on growth-promoting or seeding surface portions in the first recessed areas 18, but not on the growth-inhibiting areas of the inter-gate spacer layers 12. The growth-promoting surface portions may in particular, be defined by the surface portions (e.g., the end surfaces 14a indicated in
To facilitate a selective deposition of the blocking oxide 20, the layer stack 10 may be subjected to a treatment step prior to depositing the blocking oxide 20, adapted to functionalize the surface portions/end surfaces 14a of the etched back gate layers 14 in the first recessed areas 18 and thereafter depositing the blocking oxide 20 on the functionalized surface portions in the first recessed areas 18. For instance, as schematically indicated in one of the recessed areas 18 of
In
The inter-gate spacer layers 12 may be etched back using an etching process adapted to etch the inter-gate spacer layers 12 selectively to the charge trap material 21. For instance, the etching process may be adapted to etch (e.g., remove) the material (e.g., the oxide material) of the inter-gate spacer layers 12 selectively to the material (e.g., the SiN) of the charge trap material 21, for example, such that the inter-gate spacer layers 12 may be laterally etched back without causing any substantial etch-back of the charge trap material 21. The etching process may be applied to the sidewall of the layer stack 10 via the memory hole 4. Any suitably selective etching process, wet or dry, providing a sufficient lateral etching component with respect to the inter-gate spacer layers 12 (such as an isotropic etching process) may be used.
Providing a semiconductor layer 16 as a top layer of the layer stack 10, can ensure in some embodiments, that also the top-most inter-gate spacer layer 12 may be recessed. For example, the semiconductor layer 16 may act as an etch mask for top-most inter-gate spacer layer 12 so as to counteract a vertical etch back thereof during the lateral etch-back.
The second recessed areas 22 may be formed with a depth (along the X-axis) to undercut at least the charge trap material 21. This can enable the air gap structures 28 which are to be formed (see for example,
The dummy layers 24 define temporary place holders for the air gap structures 28 which later are to be formed. The dummy layers 24 are formed of a dummy material selected so as to convertible into air gap structures 28 by a thermal treatment process (e.g., to remove the dummy layers 24 to form air gap structures 28). Example materials for the dummy layers 24 include polymer-comprising materials, such as a tetracyclododecene (TD)-based sacrificial polymer, polycycloolefin polymers (such as polynorbornene polymers), or some other thermally degradable polymer which may be deposited to fill the second recessed areas 22.
The liner layer 26 can be deposited with a thickness so as to allow the decomposed components (e.g., vapor-phase components) of the dummy layers 24, formed when the dummy layers 24 are converted into air gap structures 28 during the subsequent thermal treatment process, to exit (e.g., diffuse) through the liner layer 26. The liner layer 26 may be formed with a thickness in a range of 1-4 nm, or 1-2 nm. The liner layer 26 may be a low thermal oxide (LTO), such as LTO SiO2. By depositing the liner layer 26 at a thermal budget with a sufficient margin towards the conversion temperature of the dummy material of the dummy layers 24, premature conversion of the dummy layers 24 may be avoided in some embodiments. For example, for any of the above examples of dummy materials, a deposition temperature of the liner layer 26 at 300° C. or lower may typically provide a sufficient margin.
It is further contemplated that the dummy material may include components or additives which during the thermal treatment process are converted to, or remain to, form low k sparse matrix or porous air gap structures 28 (organic or non-organic), e.g., of silicate compounds such as (low k) organo silicate (e.g., SiOC) or fluorinated silicate (e.g., SiOF). The air gap structures 28 are hence not limited to a void spanning the full volume previously occupied by the dummy material, but may also include low k sparse structures surrounded by air, or including pores with air. However, even in the case of a remaining sparse structure, at least a major portion of the volume spanned by the air gap structure 28 can typically be filled with air.
The lateral depth or extent (along the X-axis) of the air gap structures 28 can be determined by the lateral thickness or extent (along the X-axis) of the dummy layers 24, and accordingly of the lateral depth or extent of the second recessed areas 22. This can apply correspondingly to the degree the air gap structures 28 undercut the lateral memory stacks 19. In the illustrated example, the air gap structures 28 undercut lateral memory stacks 19 along their full lateral thickness, e.g., both the blocking oxide 20 and the charge trap material 21. However, in some instances, by forming the second recessed structures 22 to only undercut the charge trap material 21, the air gap structures 28 will not undercut the blocking oxide 20.
In
The tunneling oxide layer 30 may be formed of any material used in the industry for tunneling oxide layers, one non-limiting example being silicon oxynitride (SiON). The channel layer 32 may similarly be formed by any suitable channel material for channel layers, for example, a semiconductor material such as Si, SiGe or Ge. While not shown in
If the gate layers 14 are sacrificial gate layers, the method may as shown in
Provided the lateral depth of the second recessed areas 22 is such that the second recessed areas 22 undercut the charge trap material 21 (completely or partially) but not undercut the blocking oxide 20, the air gap structures 28 may thus be sealed or closed from the gate cavities formed by removing the sacrificial gate layers 14. A risk of the RMG resulting in metal gate stack deposition in the air gap structures 28 may thus be mitigated.
If the second recessed areas 22 are formed to undercut also the blocking oxide 20, the air gap structures 28 may be sealed off during the RMG by, prior to forming the dummy layers 24, depositing a further liner layer 27 (as indicated by the dashed layer 27 in one of the second recessed areas 21 of
The dielectric liner 101 may, like the blocking oxide 20, be selectively deposited in the first recessed areas 18, e.g., using a deposition process allowing the liner material of the dielectric liner 101 to deposit selectively on growth-promoting or seeding surface portions in the first recessed areas 18 but not on the growth-inhibiting areas defined by the inter-gate spacer layers 12. The deposition of the dielectric liner 101 may be preceded by one or more treatment processes for functionalization and/or inhibition of the gate layers 14 and inter-gate spacer layers 12, respectively, as discussed above in connection with the selective deposition of the blocking oxide 20. The dielectric liner 101 may accordingly be deposited on the end surfaces 14a (see
In the above illustrated example methods, the first recessed areas 18 are formed prior to the second recessed areas 22. While this may confer an advantage of allowing an increased thermal budget for depositing the blocking oxide and the charge trap material, the opposite order is also possible, for example, provided the thermal budget for the depositions of the blocking oxide and charge trap material is below the conversion temperature of the dummy material.
The inter-gate spacer layers 12 may be etched back using an etching process adapted to etch the inter-gate spacer layers 12 selectively to the gate layers 14. For instance, the etching process may be adapted to etch (for example, remove) the material (e.g., the oxide material) of the inter-gate spacer layers 12 selectively to the material (e.g., the nitride material) of the gate layers 14, for example, such that the inter-gate spacer layers 12 may be laterally etched back without causing any substantial etch-back of the gate layers 14. The etching process may be applied to the sidewall of the layer stack 10 via the memory hole 4. Any suitably selective etching process, wet or dry, providing a sufficient lateral etching component with respect to the inter-gate spacer layers 12 (such as an isotropic etching process) may be used.
The initial recessed areas 118 may be formed with a depth (along the X-axis) matching or exceeding an intended lateral thickness of at least the charge trap material 21 of the lateral memory stacks 19, optionally the intended lateral thickness of the full lateral memory stacks 19, to be formed at the levels of the gate layers 14. The depth (e.g., the amount of lateral etch back) of the initial recessed areas 118 may for example be in a range of 4-40 nm. The depth of the recessed areas 118 may be controlled by timing the lateral etch back.
In
The sacrificial layers 120 may be formed by selectively depositing the sacrificial material to fill the initial recessed areas 118 using an ASD process, wherein the gate layers 14 define non-growth areas while the inter-gate spacer layers 12 growth areas with respect to the ASD process. The deposition of the sacrificial material may be continued until the initial recessed areas 118 are filled with the sacrificial material and the inner end surfaces of the sacrificial layers 120 are substantially flush with the inner end surfaces of the gate layers 14. Alternatively, forming the sacrificial layers 120 may comprise conformally depositing sacrificial material (e.g., by ALD) to fill the initial recessed areas 118 and cover the sidewall of the memory hole 4. The sacrificial material layer may subsequently be etched back (e.g., using an isotropic etch) to expose the inner end surfaces of the gate layers 14 at the sidewall of the memory hole 4.
In
By forming the first recessed areas 18 with a smaller lateral depth than the initial recessed areas 118, the inter-gate spacer layers 12 may be masked during the etch back of the gate layers 14, e.g., since the inter-gate spacer layers 12 then may be masked by the sacrificial layers 120 and the (etched-back) gate layers 14. If this is not the case, the etching process used to etch back the gate layers 14 may advantageously be adapted to etch the material (e.g., the nitride material) of the gate layers 14 selectively to both the sacrificial material of the sacrificial layers 120 and the material (e.g., oxide) of the inter-gate spacer layers 12.
The method may then proceed as shown in
The blocking oxide 20 may be deposited using any deposition process (e.g. an ALD process) allowing area-selective deposition of the blocking oxide 20 (e.g., SiO2) such that the blocking oxide 20 is deposited on growth-promoting or seeding surface portions in the first recessed areas 18 (e.g., the end surfaces of the etched back gate layers exposed in the first recessed areas 18) but not on the growth-inhibiting areas defined by the sacrificial layers 120. Correspondingly, the charge trap material 21 may be deposited using any deposition process (e.g., an ALD process) allowing area-selective deposition of the charge trap material 21 (e.g., SiN) such that the charge trap material 21 is deposited on growth-promoting or seeding surface portions in the first recessed areas 18 (e.g., the already deposited blocking oxide 20) but not on the growth-inhibiting areas defined by the sacrificial layers 120.
The above discussion of the possibility of applying a treatment step prior to depositing the blocking oxide 20, adapted to functionalize the end surfaces 14a of the etched back gate layers 14 and thereafter depositing the blocking oxide 20, and/or to passivate exposed surface portions of the inter-gate spacer layers 12, can apply correspondingly to the structure 1″ and the sacrificial layers 120. For instance, a treatment process may be adapted to increase an occurrence of hydrogen terminated bonds on the gate layers 14 (thus promoting deposition thereon) and/or reduce an occurrence of hydrogen terminated bonds on the sacrificial layers 120 (thus inhibiting deposition thereon). This is however merely one non-limiting example and other techniques are possible.
As an illustrative example, the gate layers 14 may be SiN layers and the sacrificial layers 20 may be Al2O3 layers, wherein a blocking oxide 20 of SiO2 may be selectively deposited using a plasma-enhanced ALD (PEALD) process comprising repeatedly performing a deposition cycle of: A) passivation of the sacrificial layers 120 using acetylacetone, B) introducing a Si precursor Bis(diethylamino) silane (BDEAS), and C) providing an O2 plasma as co-reactant. The acetylacetone can cause grafting of the surface of the Al2O3 thus making the surface of the sacrificial layers 120 (but not the SiN of the gate layers 14 in various embodiments) relatively inert to the Si precursor, such that the SiO2 blocking oxide can be selectively deposited in the first recessed areas 18. Selective deposition of charge trap material 21 of SiN may be achieved in a corresponding fashion, e.g., using a PEALD process comprising repeatedly performing a deposition cycle of A) passivation of the sacrificial layers 120, B) introducing a Si precursor, and C) providing an N2 or NH3 plasma. Various variations of these approaches are contemplated. For instance, the sacrificial layers 120 may be formed of another metal oxide, such as TiO2. Passivation of sacrificial layers 120 may be achieved using an organic carboxylic acid such as pivalic acid, butyric acid, or the like. Instead of BDEAS some other relatively bulky Si precursor may be used. Furthermore, a thermal ALD process may be used instead of a PEALD process.
After forming the lateral memory stacks 19, the method may proceed by removing the sacrificial layers 120 employing a selective etch, etching the sacrificial material selectively to the charge trap material 21 and the blocking oxide 20. Any suitably selective etching process, wet or dry, providing a sufficient lateral etching component with respect to the sacrificial layers 120 (such as an isotropic etching process) may be used. By removing the sacrificial layers 120, the initial recessed areas 118 may be restored or re-opened.
Subsequently, the inter-gate spacer layers 12 may be re-grown in the restored initial recessed areas 118. The lateral memory stacks 21 (comprising the blocking oxide 20 and the charge trap material 21) in the first recessed areas 18 can thus vertically separated by the re-grown inter-gate spacer layers 12, corresponding to the structure 1 as shown in
According to an example variation of the preceding flow, instead of re-growing the inter-gate spacer layers 12, the method may after removing the sacrificial layers 120 directly proceed with forming dummy layers 24 in the initial recessed areas 118. The initial recessed areas 118 may accordingly in this example define the second recessed areas 22 shown and discussed in relation
According to yet another example variation, provided the sacrificial layers 120 are formed of any one of the example dummy materials for the dummy layer 18, the sacrificial layers 120 need not be removed after forming the lateral memory stacks 19, but rather remain in the structure 1″ to define the dummy layers 18 which, after lining the sidewall of the memory hole 4 with liner layer 26 may be converted into air gap structures 28. This approach may be applied provided the dummy material (e.g., polymer-comprising) provides the desired deposition-inhibiting properties during deposition of the blocking oxide 20 and the charge trap material 21.
The person skilled in the art realizes that the disclosed technology by no means is limited to the embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 23202146.9 | Oct 2023 | EP | regional |
