BRIEF DESCRIPTION OF THE DRAWINGS
Following are brief descriptions of exemplary drawings. They are mere exemplary embodiments and the scope of the present invention should not be limited thereto.
FIG. 1 is a cross-sectional view of a prior art gate structure.
FIGS. 2A-2H are schematic cross-sectional views of an exemplary process of forming a gate structure.
DESCRIPTION OF THE PREFERRED EMBODIMENT
This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation.
FIGS. 2A-2H are schematic cross-sectional views of an exemplary process of forming a gate structure.
Referring to FIG. 2A, a dielectric layer 210 is formed over a substrate 200. The substrate can be a P-type or N-type silicon substrate, III-V compound substrate, display substrate such as a substrate suitable for a liquid crystal display (LCD), plasma display, electro luminescence (EL) lamp display, a light emitting diode (LED) substrate (collectively referred to as, substrate 200), or the like, for example. The dielectric layer 210 may comprise, for example, an oxide layer, nitride layer, oxynitride layer or the like. The dielectric layer 210 is provided for allowing a subsequent high-k dielectric layer, e.g. dielectric layer 220, to be desirably formed over the substrate 200. For example, molecules of precursors provided for the formation of the high-k dielectric layer 220 can desirably attach to, or bond with, the dielectric layer 210. The dielectric layer 210 can be formed, for example, by a chemical process (e.g., standard clean 1 (SC1) process), thermal oxidation process, chemical vapor deposition process or other method that is able to form a thin dielectric layer. An SC1 process is cost-effective in view of its processing time and cost. For embodiments using 65-nm technology, the dielectric layer 210 is formed to be between about 4 Å and about 9 Å, preferably about 8.5 Å.
In some embodiments, the step of forming the dielectric layer 210 is optional if the high-k dielectric layer 220 can be desirably formed over the substrate 200 without the intervening dielectric layer 210.
As shown in FIG. 2B, a high-k dielectric layer 220 is formed over the dielectric layer 210 if the dielectric layer 210 is included as described above. The high-k dielectric layer 220 may have a permittivity of about 8 or more, and more preferably have a permittivity of about 10 or more, and even more preferably have a permittivity of about 20 or more. The high-k dielectric layer 220, due to its high dielectric constant, is formed to provide a desired equivalent oxide thickness (EOT), when a voltage drop is applied across the high-k dielectric layer 220. The high-k dielectric layer 220 may comprise a hafnium (Hf) containing dielectric layer, such as HfSiON, HfO2, HfTaO, HfZrO, HfTaTiO, HfAlON, combinations thereof or the like. The high-k dielectric layer 220 may be formed, for example, by a CVD process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, metal organic CVD (MOCVD) process, combinations thereof, or the like. For embodiments using 65-nm technology, the high-k dielectric layer 220 is formed to be between about 15 Å and about 45 Å, preferably about 30 Å.
Turning to FIG. 2C, an annealing process 223 processes the high-k dielectric layer 220. The annealing process 223 is provided to reduce and/or remove damage or defects existing on or within the high-k dielectric layer 220. In this art, the annealing process is referred to as “post deposition annealing” (PDA). The damage or defects within the high-k dielectric layer 220 may adversely affect electrical characteristics, e.g., dielectric constant or leakage resistance, of the high-k dielectric layer 220. The annealing process 223 may include a processing temperature ranging from about 400° C. to about 1,200° C., preferably about 500° C., and may be performed within a chamber having an environment of oxygen (O2), nitrogen (N2), hydrogen (H2), deuterium (D2), ammonia (NH3), inert gas (e.g., argon (Ar)), combinations thereof, or the like. The annealing process may be performed by a furnace, rapid thermal annealing (RTA) apparatus, single-wafer thermal apparatus, combinations thereof, or the like.
As shown in FIG. 2D, a process 227 using an oxygen-containing solution is provided to treat the high-k dielectric layer 220. The process 227 may comprise a wet process, vapor treatment, combinations thereof, or the like. For example, the process 227 is performed by a wet bench, single wafer processing apparatus or the like. The substrate 200 having the high-k dielectric layer 220 formed thereover is immersed into the oxygen-containing solution introduced in a wet bench, or the oxygen-containing solution is dispensed or sprayed over the high-k dielectric layer 220 supported by a single wafer processing apparatus. The process 227 may also be performed in a chamber in which the oxygen-containing solution is vaporized, so as to process the high-k dielectric layer 220 configured within the chamber.
The process 227 may have a processing temperature between of about 20° C. and about 200° C. The oxygen-containing solution comprises hydrogen peroxide (H2O2), ozone (O3), sulfuric acid (H2SO4), phosphoric acid (H3PO4), acetic acid (CH3COOH), ammonia and hydrogen peroxide mixture (APM), sulfuric and hydrogen peroxide mixture (SPM) and hydrochloric and hydrogen peroxide mixture (HPM), combinations thereof or the like. In a preferred embodiment, the high-k dielectric layer 220 is processed by a single wafer process tool for about 120 seconds at a processing temperature of about 25° C., and the oxygen-containing solution is H2O2 having a concentration of about 31% in weight.
The process 227 provides a desired amount of oxygen that binds with dangling bonds or traps existing on the surface of, or within, the high-k dielectric layer 220 so as to reduce the level of the dangling bonds or traps. Removing or reducing the level of dangling bonds or traps improves electrical characteristics, e.g., capacitance or current leakage.
In some embodiments, the sequence of the processes 223 and 227 can be switched. In other embodiments, the annealing process 223 can optionally be omitted, if the process 227 can provide a desired amount of oxygen for removing or reducing dangling bonds or traps of the high-k dielectric layer 220. In the embodiments, the processing step 227 replaces the annealing step 223. Further, the omission of the annealing process 223 will reduce the thermal budget of forming a transistor.
Referring to FIG. 2E, a metal-containing layer 230 is formed over the high-k dielectric layer 220. The metal-containing layer 230 may comprise an N-type metal-containing layer which includes tantalum (Ta), for example; or a P-type metal-containing layer which includes tungsten (W), Molybdenum (Mo), ruthenium (Ru), combinations thereof or the like. The metal-containing layer 230 may be formed, for example, by a CVD process, PVD process, MOCVD process, ALD process, combinations thereof or the like. For embodiments using 65-nm technology, the metal-containing layer 230 is formed to be between about 10 Å and about 300 Å, preferably about 100 Å. Use of the metal-containing layer 230 can substantially eliminate a gate depletion concern as described above.
A cap layer 240 is then formed over the metal-containing layer 230 as shown in FIG. 2F. The cap layer 240 is formed for preventing oxidation of the metal-containing layer 230 resulting from a subsequent thermal process, such as an annealing process. Oxidation of the metal-containing layer 230 may increase the resistance thereof, adversely affecting electrical characteristics, such as capacitance or current leakage, of the metal-containing layer 230.
The cap layer 240 may comprise, for example, a tantalum nitride (TaN) layer, titanium nitride (TiN) layer, TaSiN layer, combinations thereof or the like, and may be formed by, for example, a CVD process, PVD process, MOCVD process, ALD process or the like. For embodiments using 65-nm technology, the cap layer 240 is between about 10 Å and about 1,000 Å in thickness. The cap layer 240 may prevent metal oxidation occurring to the metal-containing layer 230. It may depend on material property of the metal-containing layer 230. For example, the metal-containing layer 230 is a P-type layer, e.g., including material of Mo, W and/or Ru. This P-type metal-containing layer is not stable and is vulnerable to metal oxidation. For embodiments using an N-type metal-containing layer, e.g., including a Ta material, this N-type metal-containing layer 230 is stable and the cap layer 240 may be optionally omitted. In other words, the cap layer 240 is optional if the oxidation of the metal-containing layer 230 is not a concern within a given manufacturing process.
As shown in FIG. 2G, a material layer 250 is formed over the cap layer 240, if the cap layer 240 is included. The material layer 250 may comprise, for example, a polysilicon layer, amorphous silicon layer, P-type silicon layer, N-type silicon, combinations thereof or the like. The material layer 250 is provided to prevent contamination resulting from the metal-containing layer 230. In some embodiments, the material layer 250 is provided to achieve a desired height of the gate structure. For example, a polysilicon gate structure is higher than a metal-containing gate structure, if they are provided to form transistors having the same gate feature size, e.g., gate length. A manufacturing process of forming a transistor having a polysilicon gate structure may be used to form a transistor having a metal-containing gate structure. However, due to the different heights of the polysilicon and metal-containing gates, the manufacturing process for the polysilicon gate cannot be directly applied without modification to form a metal-containing gate transistor. One or more steps of the manufacturing process, e.g., photolithographic or etch steps, should be modified due to a different topography encountered when forming the metal-containing gate. By adding the material layer 250, modification of the manufacturing process can be substantially eased. The material layer 250 can be formed, for example, by a CVD process. For embodiments using 65-nm technology, the material layer 250 is between about 400 Å and about 1,000 Å in thickness, preferably about 1,000 Å. In some embodiments, the material layer 250 may optionally be omitted if contamination and/or gate height difference set forth above are not concerns.
Referring to FIG. 2H, a gate structure 260, including the dielectric layer 210a, high-k dielectric layer 220a, metal-containing layer 230a, cap layer 240a and material layer 250a, is sequentially formed over the substrate 200. In order to form the gate structure 260, a photoresist pattern (not shown) corresponding to the patterned layers 210a-250a is formed over the structure shown in FIG. 2G by a photolithographic process, for example. An etch process, which may include multiple etch steps corresponding to the layers 210-250, is performed for partially removing the layers 210-250, thereby forming the gate structure 260 as shown in FIG. 2H. As described above, the layers 210, 240 and/or 250 are optional. The etch process may be modified corresponding to the variation of the gate structure 260. After the etch process, the patterned photoresist is removed by a photolithographic removal process, for example.
Though dimensions of the layers 210a-250a of the gate structure 260 are shown for an example using 65-nm technology, the present invention, however, is not limited thereto. Dimensions of these layers 210-250a may vary in accordance with the feature size of the semiconductor technology. One of ordinary skill in the art can readily modify the dimensions of these layers to achieve a desired gate structure.
Although the present invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly to include other variants and embodiments of the invention, which may be made by those skilled in the field of this art without departing from the scope and range of equivalents of the invention.
Patent Application
20080050879
