Methods of packaging and testing microelectronic imaging devices

Abstract

Microelectronic imaging devices and methods of packaging microelectronic imaging devices are disclosed herein. In one embodiment, a microelectronic imaging device includes a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The imaging device further includes a cover over the image sensor and a plurality of interconnects in and/or on the cover that are electrically coupled to corresponding bond-pads of the die. The interconnects provide external electrical contacts for the bond-pads of the die. The interconnects can extend through the cover or along a surface of the cover.

Description

TECHNICAL FIELD

The present invention is related to microelectronic devices and methods for packaging microelectronic devices. Several aspects of the present invention are directed toward packaging microelectronic imaging devices that are responsive to radiation in the visible light spectrum or radiation in other spectrums.

BACKGROUND

Microelectronic imagers are used in digital cameras, wireless devices with picture capabilities, and many other applications. Cell phones and Personal Digital Assistants (PDAs), for example, incorporate microelectronic imagers for capturing and sending digital images. The use of microelectronic imagers in electronic devices has been steadily increasing as imagers become smaller and produce higher quality images with increased pixel counts.

Microelectronic imagers include image sensors that use Charged Coupled Device (CCD) systems, Complementary Metal-Oxide Semiconductor (CMOS) systems, or other systems. CCD image sensors have been widely used in digital cameras and other applications. CMOS image sensors are also becoming very popular because they have low production costs, high yields, and small sizes. CMOS image sensors provide these advantages because they are manufactured using technology and equipment developed for fabricating semiconductor devices. CMOS image sensors, as well as CCD image sensors, are accordingly “packaged” to protect their delicate components and provide external electrical contacts.

FIG. 1 is a schematic side cross-sectional view of a conventional packaged microelectronic imager 1. The imager 1 includes a die 10, an interposer substrate 20 attached to the die 10, a housing 30 attached to the interposer substrate 20, and an optics unit 70 attached to the housing 30. The housing 30 has an opening 32 over the die 10 and a transparent cover 40 in the opening 32. The optics unit 70 can include a lens 74 and other optical elements to direct light through the opening 32 and toward the die 10.

The die 10 includes an image sensor 12 and a plurality of bond-pads 14 electrically coupled to the image sensor 12. The interposer substrate 20 is a dielectric member having a plurality of interior pads 22, a plurality of ball-pads 24, and a plurality of traces 26 electrically coupling the interior pads 22 to corresponding ball-pads 24. The ball-pads 24 are arranged in an array for surface mounting the imager 1 to a board or module of another device. The bond-pads 14 on the die 10 are electrically coupled to corresponding interior pads 22 on the interposer substrate 20 by a plurality of wire-bonds 28 to provide electrical pathways between the bond-pads 14 and the ball-pads 24.

One problem with conventional packaged microelectronic imagers is that they have relatively large footprints and occupy a significant amount of vertical space (i.e., high profiles). For example, the footprint of the imager 1 in FIG. 1 is the surface area of the bottom of the interposer substrate 20, which is significantly larger than the surface area of the die 10. Accordingly, the footprint of conventional packaged microelectronic imagers can be a limiting factor in the design and marketability of picture cell phones or PDAs because these devices are continually shrinking to be more portable. Therefore, there is a need to provide microelectronic imagers with smaller footprints and lower vertical profiles.

Another problem with conventional microelectronic imagers is the manufacturing costs for packaging the dies. For example, forming the wire-bonds on the imager shown in FIG. 1 is complex and expensive because it requires connecting an individual wire between each bond-pad on the die and a corresponding pad on the interposer substrate. In addition, it may not be feasible to form wire-bonds for the high-density, fine-pitch arrays of some high-performance devices. Therefore, there is a significant need to enhance the efficiency and reliability of packaging microelectronic imagers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic side cross-sectional view of a packaged microelectronic imager in accordance with the prior art.

FIGS. 2A-2E illustrate various stages in a method of forming a cover substrate for use in microelectronic imaging devices in accordance with one embodiment of the invention.

FIG. 2A is a schematic side cross-sectional view of the cover substrate after forming a plurality of apertures.

FIG. 2B is a schematic side cross-sectional view of the cover substrate after forming a first conductive layer.

FIG. 2C is a schematic side cross-sectional view of the cover substrate after removing a portion of the first conductive layer.

FIG. 2D is a schematic side cross-sectional view of the cover substrate after forming a second conductive layer on the first conductive layer.

FIG. 2E is a schematic side cross-sectional view of the cover substrate after forming a plurality of interconnects in the apertures.

FIGS. 3A-3C illustrate various stages in a method of forming a microelectronic imaging device in accordance with one embodiment of the invention.

FIG. 3A is a schematic isometric cross-sectional view of a microfeature workpiece and the cover substrate of FIG. 2E.

FIG. 3B is a schematic side cross-sectional view of the microfeature workpiece after attaching the cover substrate.

FIG. 3C is a schematic side cross-sectional view of an individual microelectronic imaging device after singulation.

FIG. 4 is a schematic side cross-sectional view of a plurality of microelectronic imaging devices in accordance with another embodiment of the invention.

FIG. 5 is a schematic side cross-sectional view of a plurality of microelectronic imaging devices in accordance with another embodiment of the invention.

FIG. 6 is a schematic side cross-sectional view of a plurality of microelectronic imaging devices in accordance with another embodiment of the invention.

FIG. 7A is a schematic side cross-sectional view of a plurality of microelectronic imaging devices in accordance with another embodiment of the invention.

FIG. 7B is a schematic side cross-sectional view of an individual microelectronic imaging device of FIG. 7A after singulation.

FIG. 8 is a schematic side cross-sectional view of a plurality of microelectronic imaging devices in accordance with another embodiment of the invention.

DETAILED DESCRIPTION

A. Overview

The following disclosure describes several embodiments of microelectronic imaging devices and methods of packaging microelectronic imaging devices. Specific details of several embodiments of the invention are described below with reference to CMOS imagers to provide a thorough understanding of these embodiments, but other embodiments can be CCD imagers or other types of imaging devices. Several details describing well-known structures often associated with microelectronic devices are not set forth in the following description to avoid unnecessarily obscuring the description of the disclosed embodiments. Additionally, several other embodiments of the invention can have different configurations and/or components than those described in this section. As such, a person of ordinary skill in the art will accordingly understand that the invention may have other embodiments with additional elements or without several of the elements shown and described below with reference to FIGS. 2A-8.

Several aspects of the invention are directed to a plurality of microelectronic imaging devices formed at the wafer level. In one embodiment, the microelectronic imaging devices include a microfeature workpiece having a plurality of microelectronic dies. The individual dies include an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The microelectronic imaging devices further include a cover substrate over the image sensors of the dies. The cover substrate is transmissive to radiation for the image sensors and has a plurality of electrically conductive interconnects electrically coupled to corresponding bond-pads on the dies. In one aspect of this embodiment, the interconnects extend through the cover substrate. Alternatively, the interconnects can extend along the surface of the cover substrate that faces the image sensors. Individual interconnects can be electrically connected to a pair of bond-pads of adjacent dies to couple the cover substrate to the workpiece, or the individual interconnects can be electrically coupled to corresponding individual bond-pads. For example, an interconnect can be directly connected to a bond-pad, or an interconnect can be indirectly connected to a bond-pad via a solder ball or other conductive element.

Another aspect of the invention is directed to individual microelectronic imaging devices. In one embodiment, a microelectronic imaging device includes a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The imaging device further includes a cover over the image sensor and a plurality of interconnects in and/or on the cover to provide external electrical contacts electrically connected to the bond-pads of the die. In one aspect of this embodiment, the interconnects wrap around corresponding ends of the cover. Alternatively, the interconnects can extend through the cover and be aligned with the corresponding bond-pads. In another aspect of this embodiment, the microelectronic imaging device further includes a substrate having an opening and an optics unit disposed at least partially within the opening. The cover is disposed between the substrate and the microelectronic die, and the optics unit is aligned with the image sensor on the die.

Another aspect of the invention is directed to methods of packaging microelectronic imaging devices. In one embodiment, a method includes providing a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit. The method further includes providing a cover having a first surface, a second surface opposite the first surface, and a plurality of interconnects extending from the first surface to the second surface. The method further includes coupling the cover to the microelectronic die with the cover over the image sensor and with the interconnects electrically coupled to corresponding bond-pads.

B. Embodiments of Methods of Forming Cover Substrates

FIGS. 2A-2E illustrate various stages in a method of forming a cover substrate for use in microelectronic imaging devices in accordance with one embodiment of the invention. FIG. 2A, more specifically, is a schematic side cross-sectional view of a cover substrate 140 for covering a plurality of image sensor dies. As such, the cover substrate 140 can be glass, quartz, or other suitable materials transmissive to a desired spectrum of radiation. In embodiments directed toward imaging radiation in the visible spectrum, the cover substrate 140 can also have films that filter ultraviolet, infrared radiation, or other undesirable spectrums of radiation. The cover substrate 140, for example, can be formed from a material and/or have a coating that filters IR or near IR spectrums.

In the illustrated embodiment, the cover substrate 140 includes a first surface 142, a second surface 144 opposite the first surface 142, and a plurality of apertures 146 extending from the first surface 142 to the second surface 144. The apertures 146 can be arranged in arrays, with individual arrays corresponding to individual arrays of bond-pads on a microelectronic die. More specifically, the apertures 146 can be arranged so that each aperture 146 is aligned with a bond-pad on a die when the cover substrate 140 is placed over the dies in proper alignment, as described in greater detail below. The apertures 146 can be formed in the cover substrate 140 by laser drilling, etching, and/or other suitable processes. Although the cover substrate 140 illustrated in FIG. 2A has apertures 146 extending completely through the substrate 140, other embodiments of cover substrates in accordance with the invention may not include apertures 146 that extend through the substrates.

FIG. 2B is a schematic side cross-sectional view of the cover substrate 140 after forming a first conductive layer 150 on the substrate 140. The first conductive layer 150 can be a seed layer deposited in the apertures 146 and across the first and second surfaces 142 and 144 of the cover substrate 140. The first conductive layer 150 can include TiNitride, TiCU, and/or other suitable materials, and the layer 150 be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes. In other embodiments, the first conductive layer 150 may not be deposited across the entire first and/or second surface 142 and/or 144.

FIG. 2C is a schematic side cross-sectional view of the cover substrate 140 after removing the portion of the first conductive layer 150 on the first and second surfaces 142 and 144. In this embodiment, the first conductive layer 150 in the apertures 146 is not removed. Portions of the first conductive layer 150 can be removed by etching, chemical-mechanical polishing, and/or other suitable processes. In additional embodiments, sections of the first conductive layer 150 on the first and/or second surface 142 and/or 144 may not be removed.

FIG. 2D is a schematic side cross-sectional view of the cover substrate 140 after forming a second conductive layer 152 on the first conductive layer 150 in the apertures 146. The second conductive layer 152 can include nickel, copper, and/or other suitable materials, and the layer 152 can be formed by electroless plating or other suitable methods. The second conductive layer 152 provides desired wetting characteristics so that the apertures 146 can be subsequently filled with a conductive material. Alternatively, the second conductive layer can fill the apertures 146 so that subsequent filling with the conductive material is unnecessary. In additional embodiments, the cover substrate 140 may not include the second conductive layer 152 if the first conductive layer 150 is compatible or otherwise provides the desired wetting characteristics for the conductive fill material.

FIG. 2E is a schematic side cross-sectional view of the cover substrate 140 after forming a plurality of interconnects 160 in the apertures 146. After the second layer 152 has been formed on the first conductive layer 150, a conductive fill material 154 can be deposited into the apertures 146 to fill the remaining void between the first surface 142 and the second surface 144. The conductive fill material 154 can include solder, conductive epoxy, conductive polymers, and/or other materials. The conductive fill material 154, the second conductive layer 152, and the first conductive layer 150 in each aperture 146 form individual interconnects 160 that extend from the first surface 142 to the second surface 144. The interconnects 160 are electrically conductive to transmit electrical signals through the cover substrate 140. For example, the cover substrate 140 can transmit an electrical signal from a microelectronic die to an external device, as described in greater detail below.

In the illustrated embodiment, the interconnects 160 include a first cap 156a projecting from the first surface 142 and a second cap 156b projecting from the second surface 144. The caps 156a-b provide external contacts to electrically couple the interconnects 160 to other devices. In additional embodiments, the interconnects 160 can have different configurations and/or be formed by other suitable processes. For example, the interconnects 160 may not include caps 156a-b projecting away from the cover substrate 140, and/or the interconnects 160 may not include all of the first conductive layer 150, the second conductive layer 152, and the conductive material 154. Moreover, the interconnects 160 may also extend at least partially along the first and/or second surface 142 and/or 144. Furthermore, as described below with reference to FIGS. 7A-7B, the interconnects 160 may not extend through the cover substrate 140 from the first surface 142 to the second surface 144, but rather the interconnects 160 can extend around the perimeter of a singulated portion of the cover substrate 140.

C. Embodiments of Microelectronic Imaging Devices

FIGS. 3A-3C illustrate various stages in a method of forming microelectronic imaging devices in accordance with one embodiment of the invention. FIG. 3A, more specifically, is a schematic isometric cross-sectional view of a microfeature workpiece 102 and the cover substrate 140 of FIG. 2E. The microfeature workpiece 102 includes a substrate 104 and a plurality of microelectronic dies 110 formed in and/or on the substrate 104. In the illustrated embodiment, the individual dies 110 include an integrated circuit 111 (shown schematically), an image sensor 112 operably coupled to the integrated circuit 111, and a plurality of bond-pads 114 electrically coupled to the integrated circuit 111. The image sensors 112 can be CMOS devices or CCDs for capturing pictures or other images in the visible spectrum. In other embodiments, the image sensors 112 can detect radiation in other spectrums (e.g., IR or UV ranges). The bond-pads 114 are arranged in arrays that correspond with the arrangement of interconnects 160 in corresponding arrays on the cover substrate 140. As such, each bond-pad 114 can be aligned with a corresponding interconnect 160, as described in detail below.

FIG. 3B is a schematic side cross-sectional view of the microfeature workpiece 102 after attaching the cover substrate 140. A plurality of conductive elements 130 are deposited onto the bond-pads 114 and/or the interconnects 160 to physically attach the cover substrate 140 to the microfeature workpiece 102. The conductive elements 130 can be solder balls or other conductive devices that electrically connect the interconnects 160 to corresponding bond-pads 114. Accordingly, the interconnects 160 provide external electrical contacts for the bond-pads 114 of the dies 110. In other embodiments, the cover substrate 140 can be attached to the microfeature workpiece 102 without the conductive elements 130. For example, the first caps 156a can be attached directly to the corresponding bond-pads 114.

In the illustrated embodiment, a partial underfill material 132 is deposited around the periphery of each image sensor 112. The underfill material 132 can be deposited between rows of bond-pads 114 of adjacent bond-pad arrays. The underfill material 132 flows between the bond-pads 114 and the conductive elements 130. The underfill material 132 enhances the integrity of the joint between the cover substrate 140 and the microelectronic dies 110 and protects the image sensors 112 from moisture, chemicals, and other contaminants. In other embodiments, such as those described below with reference to FIG. 4, the underfill material 132 may be deposited across the image sensors 112, or alternatively, the underfill material 132 may not be deposited between the microfeature workpiece 102 and the cover substrate 140.

In the illustrated embodiment, the interconnects 160 are aligned with the bond-pads 114 of the dies 110 when the cover substrate 140 is attached to the microfeature workpiece 102. As such, the interconnects 160 are positioned outboard the image sensors 112 so as not to obstruct radiation from passing through the cover substrate 140 toward the image sensors 112. After attachment, the microfeature workpiece 102 and the cover substrate 140 can be cut along lines ArAi to singulate individual microelectronic imaging devices 100. The microelectronic imaging devices 100 can pass through the reflow process to melt the conductive elements 130 and securely join the interconnects 160 to the bond-pads 114, and/or the underfill material 132 can be cured before and/or after singulation.

One feature of the illustrated embodiment is, that the microelectronic imaging devices 100 can be tested at the wafer level before the devices 100 are singulated. For example, a testing device can contact the second caps 156b of the interconnects 160 to simultaneously test all or at least many of the microelectronic imaging devices 100. Microelectronic imaging devices that do not function properly can be segregated and discarded after singulation. An advantage of this feature is that it is more efficient in terms of cost and time to test the microelectronic imaging devices 100 at the wafer level (i.e., before singulation) than to test each device 100 individually.

Another feature of the illustrated embodiment is that the cover substrate 140 is attached to the microfeature workpiece 102 before singulation. An advantage of this feature is that the image sensors 112 are covered by the cover substrate 140, and consequently protected from the debris and other material that are generated during the singulation process.

Another feature of the illustrated embodiment is that the interconnects 160 of the cover substrate 140 provide external electrical contacts for the individual microelectronic imaging devices 100. An advantage of this feature is that forming interconnects in the cover substrate 140 is less complex and exposes the imaging devices 100 to less heat than forming interconnects through the workpiece 102, from the bond-pads to the back side of the imaging devices.

FIG. 3C is a schematic side cross-sectional view of an individual microelectronic imaging device 100 after singulation. The singulated microelectronic imaging device 100 includes a die 110 and a cover 140a over the image sensor 112 of the die 110. The singulated microelectronic imaging device 100 can be mounted to a substrate 120, such as a circuit board, flex tape, or other suitable member, to redistribute electrical signals from the integrated circuit 111 of the die 110 to an external device. For example, in the illustrated embodiment, the substrate 120 includes a plurality of interior pads 122, a plurality of ball-pads 124, and a plurality of traces 126 electrically coupling the interior pads 122 to corresponding ball-pads 124. A plurality of conductive elements 131 physically attach the microelectronic imaging device 100 to the substrate 120 and form an electrical connection between the interconnects 160 and corresponding interior pads 122. Thus, the ball-pads 124 on the substrate 120 are electrically connected to the integrated circuit 111 of the die 110.

In the illustrated embodiment, the substrate 120 includes an opening 128 over the image sensor 112, and an optics unit 170 is disposed at least partially within the opening 128. The optics unit 170 is attached to the cover 140a and/or the substrate 120, and the optics unit 170 is aligned with the image sensor 112. The optics unit 170 can include a stand off 172 and an optic member 174 on the stand off 172 to transmit at least the desired spectrum of radiation to the image sensor 112. The optic member 174 can be a lens for focusing the light, a pinhole for reducing higher order refractions, and/or other optical structures for performing other functions. Suitable optics units and methods of attaching optics units are disclosed in U.S. patent application Ser. No. 10/723,363, entitled Packaged Microelectronic Imagers and Methods of Packaging Microelectronic Imagers, filed on Nov. 26, 2003, which is hereby incorporated by reference in its entirety. In additional embodiments, the microelectronic imaging device 100 may not be attached to the substrate 120 and/or optics unit 170, or the substrate 120 and/or optics unit 170 can be attached in a different arrangement.

An advantage of the embodiment illustrated in FIG. 3C is that placing the optics unit 170 in the opening 128 of the substrate 120 reduces the vertical profile or height of the device. More specifically, the vertical profile of the device 100 is the distance between the top of the optics unit 170 and the bottom of the die 110. In prior art devices, such as the device illustrated in FIG. 1, the vertical profile of the device is the distance between the top of the optics unit 70 and the bottom of the substrate 20 attached to the back side of the die 10. Thus, the vertical profile of the device illustrated in FIG. 3C is reduced by at least the thickness of the substrate 120 because the optics unit 170 is placed in the opening 128 of the substrate 120 instead of mounting the back side of the die 110 to the substrate 120.

Another feature of the illustrated embodiment is that the interconnects 160 electrically couple the bond-pads 114 to the interior pads 122 and therefore eliminate the need for wire-bonds. An advantage of this feature is that without wire-bonds, the footprint of the substrate 120 can be smaller because the interconnects 160 are coupled to the substrate 120 directly over the die 110. The reduced footprint allows the illustrated device to be used in smaller electronic devices. In prior art devices, such as the device illustrated in FIG. 1, the bond-pads 14 are wire-bonded to interior pads 22 outboard the die 10, which increases the footprint of the substrate 20.

D. Additional Embodiments of Microelectronic Imaging Devices

FIG. 4 is a schematic side cross-sectional view of a plurality of microelectronic imaging devices 200 in accordance with another embodiment of the invention. The microelectronic imaging devices 200 can be generally similar to the microelectronic imaging devices 100 described above with reference to FIGS. 2A-3C. For example, the microelectronic imaging devices 200 are formed at the wafer level by attaching a cover substrate 240 to the microfeature workpiece 102. The illustrated cover substrate 240 includes a first surface 242, a second surface 244 opposite the first surface 242, and a plurality of interconnects 260 extending from the first surface 242 to the second surface 244. The interconnects 260 include an electrically conductive material to provide external contacts for the bond-pads 114 of the microelectronic dies 110. The individual interconnects 260 include a first end 261 generally planar with the first surface 242 and a second end 262 generally planar with the second surface 244. The microelectronic imaging devices 200 further include a plurality of conductive elements 230 on corresponding second ends 262 to electrically connect the interconnects 260 to corresponding bond-pads 114. In other embodiments, the cover substrate 240 can include a plurality of ball-pads formed in and/or on the substrate 240 to connect the interconnects 260 to corresponding conductive elements 230.

In the illustrated embodiment, the cover substrate 240 further includes a plurality of recesses 243 in the first surface 242 over corresponding image sensors 112. The recesses 243 create a gap G between the cover substrate 240 and the image sensors 112. An underfill material 232 can be deposited in the gap G and across the microfeature workpiece 102 to substantially fill the void between the workpiece 102 and the cover substrate 240. The underfill material 232 is a transmissive material to permit light and/or other electromagnetic radiation to pass through the underfill material 232 and contact the image sensors 112. For example, the underfill material 232 can be an optical-grade material with a high transparency and a uniform mass density to allow maximum light transmission. The underfill material 232 can also be a highly pure material to minimize contamination and thereby reduce or eliminate the loss of images and/or light scattering. In other embodiments, the underfill material 232 may not be deposited in the gap G.

FIG. 5 is a schematic side cross-sectional view of a plurality of microelectronic imaging devices 300 in accordance with another embodiment of the invention. The microelectronic imaging devices 300 can be generally similar to the microelectronic imaging devices 100 described above with reference to FIGS. 2A-3C. For example, the microelectronic imaging devices 300 are formed at the wafer level by attaching a cover substrate 340 to the microfeature workpiece 102. The cover substrate 340 includes a first surface 342, a second surface 344 opposite the first surface 342, and a plurality of interconnects 360 extending from the first surface 342 to the second surface 344. The interconnects 360 have a first end 361 proximate to the first surface 342 and a second end 362 proximate to the second surface 344.

In the illustrated embodiment, the individual interconnects 360 have a width W sized to contact a pair of conductive elements 330 on adjacent dies 110. For example, a first end 361a of a first interconnect 360a can be coupled to a first conductive element 330a on a first bond-pad 114a of a first die 110a and a second conductive element 330b on a second bond-pad 114b of a second die 110b adjacent to the first die 110a. To singulate the microelectronic imaging devices 300, the microfeature workpiece 102, the cover substrate 340, and the interconnects 360 can be cut along lines A2-A2. Accordingly, each singulated microelectronic imaging device 300 includes a cover (i.e., a section of the cover substrate 340) with interconnects (i.e., sections of the interconnects 360) that extend along corresponding ends of the cover.

FIG. 6 is a schematic side cross-sectional view of a plurality of microelectronic imaging devices 400 in accordance with another embodiment of the invention. The microelectronic imaging devices 400 can be generally similar to the microelectronic imaging devices 300 described above with reference to FIG. 5. The microelectronic imaging devices 400, however, include a plurality of interconnects 460 that do not extend completely through a cover substrate 440. More specifically, the interconnects 460 have a first end 461 proximate to a first surface 442 of the cover substrate 440 and a second end 462 spaced apart from a second surface 444 of the substrate 440. After singulation, the individual microelectronic imaging devices 400 include portions of the interconnects 460, which provide external electrical contacts, or as described below with reference to FIGS. 7A and 7B, to which another interconnect can be attached.

FIG. 7A is a schematic side cross-sectional view of a plurality of microelectronic imaging devices 500 in accordance with another embodiment of the invention. The microelectronic imaging devices 500 can be generally similar to the microelectronic imaging devices 100 described above with reference to FIGS. 2A-3C. For example, the microelectronic imaging devices 500 are formed at the wafer level by attaching a cover substrate 540 to the microfeature workpiece 102. The illustrated cover substrate 540 includes a first surface 542, a second surface 544 opposite the first surface 542, and a plurality of interconnects 560 formed in and/or on the first surface 542. The individual interconnects 560 include end portions 561 aligned with corresponding bond-pads 114 and a second portion 562 between corresponding end portions 561. A plurality of conductive elements 530 attach the end portions 561 of the interconnects 560 to the bond-pads 114. In additional embodiments, the interconnects 560 can include a ball-pad to receive corresponding conductive elements 530. The illustrated microelectronic imaging devices 500 can be singulated by cutting the microfeature workpiece 102, the interconnects 560, and the cover substrate 540 along lines A₃-A₃.

FIG. 7B is a schematic side cross-sectional view of one of the microelectronic imaging devices 500 of FIG. 7A after singulation. After singulation, the microelectronic imaging device 500 includes a cover 540a with a plurality of ends 546 (two of which are shown as 546a-b). A plurality of second interconnects 560b can be formed on the cover 540a to provide external contacts for the bond-pads 114 of the die 110. The second interconnects 560b can be connected to corresponding first interconnects 560a and extend from the first surface 542 to the second surface 544 around corresponding ends 546 of the cover 540a. The second interconnects 560b can include conductive tape or other suitable electrically conductive material so that the first and second interconnects 560a-b form conductive lines that wrap around the cover 540a from corresponding conductive elements 530 to the second surface 544.

FIG. 8 is a schematic side cross-sectional view of a plurality of microelectronic imaging devices 600 in accordance with another embodiment of the invention. The microelectronic imaging devices 600 can be generally similar to the microelectronic imaging devices 500 described above with reference to FIG. 7A. The microelectronic imaging devices 600, however, do not include conductive elements coupling the interconnects 560 to the bond-pads 114, but rather the end portions 561 are attached to corresponding bond-pads 114.

From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. For example, the microelectronic imaging devices can have any combination of the features described above with reference to FIGS. 2A-8. Accordingly, the invention is not limited except as by the appended claims.

Claims

1. A method of packaging a plurality of microelectronic imaging devices, comprising: providing a microfeature workpiece including a plurality of microelectronic dies, the individual dies having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit;forming a plurality of interconnects in and/or on a cover substrate; andcoupling the cover substrate to the microfeature workpiece so that the cover substrate is disposed over the image sensors and each interconnect is electrically coupled to a corresponding pair of adjacent bond-pads.

2. The method of claim 1 wherein forming the interconnects comprises forming the interconnects through the cover substrate.

3. The method of claim 1 wherein forming the interconnects comprises: forming a plurality of apertures in the cover substrate; andplacing conductive material in the apertures.

4. The method of claim 1 wherein: the cover substrate includes a first surface and a second surface opposite the first surface;forming the interconnects comprises forming the interconnects on and/or in the first surface of the cover substrate with the interconnects extending in a direction generally parallel to the cover substrate; andcoupling the cover substrate to the microfeature workpiece comprises coupling the cover substrate with the first surface facing toward the image sensors and the interconnects extending outwardly away from corresponding image sensors.

5. The method of claim 1 wherein coupling the cover substrate to the microfeature workpiece comprises: forming a plurality of conductive elements on corresponding bond-pads; andattaching individual interconnects to corresponding pairs of adjacent conductive elements.

6. The method of claim 1 wherein coupling the cover substrate to the microfeature workpiece comprises superimposing the interconnects with the corresponding pairs of adjacent bond-pads.

7. The method of claim 1, further comprising forming a plurality of recesses in the cover substrate; wherein coupling the cover substrate to the microfeature workpiece comprises positioning individual recesses over a corresponding image sensor.

8. A method of packaging a microelectronic imaging device, comprising: providing a microelectronic die having an integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit;providing a cover including a first surface, a second surface opposite the first surface, and a plurality of interconnects extending from the first surface to the second surface;coupling the cover to the microelectronic die, with the cover over the image sensor, and with the interconnects electrically coupled to corresponding bond-pads;attachinn the cover to a substrate having an opening and a plurality of pads, the pads being electrically coupled to corresponding interconnects, and the cover being disposed between the substrate and the microelectronic die; anddisposing an optics unit at least partially within the opening so that the optics unit is aligned with the image sensor.

9. The method of claim 8 wherein providing the cover comprises providing the cover with the interconnects extending through the cover.

10. The method of claim 8 wherein: the cover further includes a plurality of ends connecting the first surface to the second surface; andproviding the cover comprises providing the cover with the interconnects extending along corresponding ends.

11. The method of claim 8 wherein coupling the cover to the microelectronic die comprises: forming a plurality of conductive elements on corresponding bond-pads; andattaching the interconnects to corresponding conductive elements.

12. The method of claim 8 wherein coupling the cover to the microelectronic die comprises: forming a plurality of conductive elements on corresponding bond-pads; andattaching individual interconnects to corresponding pairs of adjacent conductive elements.

13. A method of packaging a microelectronic imaging device, comprising: providing a microelectronic die having a integrated circuit, an image sensor electrically coupled to the integrated circuit, and a plurality of bond-pads electrically coupled to the integrated circuit;coupling the microelectronic die to a cover having a plurality of interconnects, with the cover over the image sensor and the interconnects electrically coupled to corresponding bond-pads;attaching the cover to a substrate having an opening and a plurality of pads, the pads being electrically coupled to corresponding interconnects, and the cover being disposed between the substrate and the microelectronic die; anddisposing an optics unit at least partially within the opening so that the optics unit is aligned with the image sensor.

14. The method of claim 13 wherein coupling the die to the cover comprises coupling the die to the cover with the interconnects extending through the cover.

15. The method of claim 13 wherein: the cover includes a first surface, a second surface opposite the first surface, and a plurality of ends connecting the first surface to the second surface; andcoupling the die to the cover comprises coupling the die to the cover with the interconnects extending along corresponding ends of the cover.

16. The method of claim 13 wherein: the cover includes a first surface, a second surface opposite the first surface, and a plurality of ends connecting the first surface to the second surface; andcoupling the die to the cover comprises coupling the die to the cover with the first surface of the cover facing the image sensor and with the interconnects extending along the first surface of the cover toward the corresponding ends.

17. A method of testing a plurality of microelectronic imaging devices, comprising: providing a microfeature workpiece and a cover substrate coupled to the microfeature workpiece, the microfeature workpiece including a plurality of dies with an image sensor and a plurality of bond-pads electrically coupled to the image sensor;contacting a plurality conductive interconnects extending through the cover substrate with a testing device, the interconnects being arranged in arrays and each interconnect being electrically coupled to a corresponding pair of adjacent bond-pads of corresponding dies; andelectrically testing the corresponding dies by applying signals to the interconnects with the testing device.

18. The method of claim 4, further comprising singulating the microelectronic imaging devices by cutting the interconnects at a location between bond pads forming each pair of adjacent bond pads, such that each singulated microelectronic imaging device comprises interconnects that extend along corresponding ends of the cover substrate.

19. The method of claim 4, further comprising singulating the microelectronic imaging devices by cutting the interconnects at a location between bond pads forming each pair of adjacent bond pads, such that each singulated microelectronic imaging device comprises interconnects that provide external electrical contacts without extending fully through the cover substrate.

20. The method of claim 19, wherein the interconnects are first interconnects and the method further comprises forming a plurality of second interconnects connected to the first interconnects and extending from the first surface of the cover substrate to the second surface of the cover substrate around corresponding ends of the cover substrate.