Patent Application
20250096053
Integrated circuit (IC) devices (e.g., dies) can be coupled together in a multi-die IC package to integrate features or functionality and to facilitate connections to other components, such as package substrates. IC packages may include an embedded multi-die interconnect bridge (EMIB) for coupling two or more IC dies.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings.
Communicating large numbers of signals between two or more dies in a multi-die IC package is challenging due to the increasingly small size of such dies and increased use of stacking dies. As transistor density increases with each new silicon node, yielding large, monolithic dies has become increasingly difficult, leading to an industry push toward die disaggregation. Multi-die IC packaging typically requires increased die segregation, additional power delivery requirements, and stricter routing and alignment tolerances throughout the package. The greater number of embedded dies and smaller size of embedded dies (i.e., bridge dies, passives, etc.) vastly increases manufacturing complexity as well as routing complexity as power signals must be routed around embedded dies. Various ones of the embodiments disclosed herein may help reduce the cost and complexity associated with assembling multi-die IC packages relative to conventional approaches by incorporating double-sided embedded dies with through-silicon vias (TSVs) that enable power signals to be routed through the embedded dies.
To produce packages with embedded dies, the embedded dies may be placed into a cavity in a substrate and bonded to the substrate using solder bonds. For example, solder bonds may couple the TSVs in the embedded die to power connections in the underlying substrate. When solder bonds are used, an underfill dielectric material is deposited below the embedded die, in the gaps between the solder bumps. However, it can be challenging to flow the dielectric underneath the embedded die in the cavity. Variation in solder bump height and/or incomplete underfill can lead to structural inconsistencies, e.g., the embedded die being slightly tilted, rather than level. If the embedded die is not level, it can be challenging to properly align and mount dies over the embedded die. Furthermore, solder bonds have relatively high resistance compared to other bonding methods, such as direct bonding or hybrid bonding.
As described herein, a glass patch is included in a microelectronic assembly, below the embedded die. The glass patch may include through-glass vias (TGVs) to couple power connections in the substrate to power connections in the embedded die. The glass patch has openings formed therein for forming the TGVs. The glass patch may be bonded to the substrate, and a self-aligned etch may etch vias in an upper portion of the substrate to metal lines already formed in the substrate. The embedded die may be hybrid bonded to the glass patch, rather than using solder bonds. The glass patch provides lower-resistance connections to power delivery in the substrate. Furthermore, the glass patch provides increased stability for the embedded die and the dies mounted overtop of the embedded die, reducing alignment errors.
In some embodiments, in addition to the TGVs, one or more passive components may be embedded in the glass patch. The TGVs may be power vias that provide power to one or more dies in the multi-die package. Passive devices such as inductors or transformers can be used in power delivery applications, e.g., to change a voltage level, or to provide power at multiple different voltage levels. As another example, resistors and capacitors may be incorporated in the package to reduce electromagnetic interference (EMI) and/or suppress electrostatic discharge (ESD).
In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. The accompanying drawings are not necessarily drawn to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features. It is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using, e.g., images of suitable characterization tools such as scanning electron microscopy (SEM) images, transmission electron microscope (TEM) images, or non-contact profilometer. In such images of real structures, possible processing and/or surface defects could also be visible, e.g., surface roughness, curvature or profile deviation, pit or scratches, not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region(s), and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication and/or packaging.
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a “package” and an “IC package” are synonymous, as are a “die” and an “IC die.” The terms “top” and “bottom” may be used herein to explain various features of the drawings, but these terms are simply for ease of discussion, and do not imply a desired or required orientation. As used herein, the term “insulating” means “electrically insulating,” unless otherwise specified. Throughout the specification, and in the claims, the term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.” Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value (e.g., within +/−5 or 10% of a target value) based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.
When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. For convenience, the phrase “
The die 114-1 may include a bottom surface with first conductive contacts 122, an opposing top surface with second conductive contacts 124, and TSVs 125 coupling respective first and second conductive contacts 122, 124. In some embodiments, a pitch of the first conductive contacts 122 on the first die 114-1 maybe between 25 microns and 250 microns. As used herein, pitch is measured center-to-center (e.g., from a center of a conductive contact to a center of an adjacent conductive contact). In some embodiments, a pitch of the second conductive contacts 124 on the first die 114-1 maybe between 25 microns and 100 microns.
The dies 114-2, 114-3 may include a set of conductive contacts 122 on the bottom surface of the die (e.g., the surface facing towards an upper surface of the substrate 107). The dies 114-1, 114-2, and 114-3 may include other conductive pathways (e.g., including lines and vias) and/or to other circuitry (not shown) coupled to the respective conductive contacts (e.g., conductive contacts 122, 124) on the surfaces of the dies 114. As used herein, the terms “die,” “microelectronic component,” and similar variations may be used interchangeably. As used herein, the terms “interconnect component,” “bridge die,” and similar variations may be used interchangeably. The bridge die 114-1 may be electrically coupled to dies 114-2, 114-3 by die-to-die (DTD) interconnects 130. The DTD interconnects 130 are over the upper surface of the substrate 107. In particular, conductive contacts 124 on a top surface of the die 114-1 may be coupled to conductive contacts 122 on a bottom surface of dies 114-2, 114-3 by conductive vias 108B through the dielectric material 112B and DTD interconnects 130.
As used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components (e.g., part of a conductive interconnect); conductive contacts may be recessed in, flush with, or extending away (e.g., having a pillar shape) from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket, or portion of a conductive line or via). In a general sense, an “interconnect” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, facilitating communication of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, facilitating communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are comprised in the term “interconnect.” The nature of the interconnect being described is to be understood herein with reference to the signal medium associated therewith. Thus, when used with reference to an electronic device, such as an IC that operates using electrical signals, the term “interconnect” describes any element formed of an electrically conductive material for providing electrical connectivity to one or more elements associated with the IC or/and between various such elements. In such cases, the term “interconnect” may refer to both conductive traces (also sometimes referred to as “metal traces,” “lines,” “metal lines,” “wires,” “metal wires,” “trenches,” or “metal trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). Sometimes, electrically conductive traces and vias may be referred to as “conductive traces” and “conductive vias”, respectively, to highlight the fact that these elements include electrically conductive materials such as metals. Likewise, when used with reference to a device that operates on optical signals as well, such as a photonic IC (PIC), “interconnect” may also describe any element formed of a material that is optically conductive for providing optical connectivity to one or more elements associated with the PIC. In such cases, the term “interconnect” may refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fiber, optical splitters, optical combiners, optical couplers, and optical vias.
The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive pathways formed through the insulating material. In some embodiments, the insulating material of a die 114 may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide materials, glass reinforced epoxy matrix materials, or a low-k or ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymeric dielectrics, photo-imageable dielectrics, and/or benzocyclobutene-based polymers). In some embodiments, the insulating material of a die 114 may include a semiconductor material, such as silicon, germanium, or a III-V material (e.g., gallium nitride), and one or more additional materials. For example, an insulating material may include silicon oxide or silicon nitride. The conductive pathways in a die 114 may include conductive traces and/or conductive vias, and may connect any of the conductive contacts in the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on a same surface or on different surfaces of the die 114). Example structures that may be included in the dies 114 disclosed herein are discussed below with reference to
In some embodiments, the die 114 may include conductive pathways to route power, ground, and/or signals to/from other dies 114 included in the microelectronic assembly 100. For example, the die 114-1 may include TSVs 125, including a conductive material via, such as a metal via, isolated from the surrounding silicon or other semiconductor material by a barrier oxide), or other conductive pathways through which power, ground, and/or signals may be transmitted between a package substrate 102 and one or more dies 114 “on top” of the die 114-1 (e.g., in the embodiment of
The dielectric material 112 of the substrate 107 may be formed in layers (e.g., at least a first dielectric material layer 112A and a second dielectric material layer 112B). In some embodiments, the dielectric material 112 may include an organic material, such as an organic buildup film. In some embodiments, the dielectric material 112 may include a ceramic, an epoxy film having filler particles therein, glass, an inorganic material, or combinations of organic and inorganic materials, for example. In some embodiments, the conductive material 108 may include a metal (e.g., copper). In some embodiments, the substrate 107 may include layers of dielectric material 112/conductive material 108, with lines/traces/pads/contacts (e.g., 108A) of conductive material 108 in one layer electrically coupled to lines/traces/pads/contacts (e.g., 108A) of conductive material 108 in an adjacent layer by vias (e.g., 108B) of the conductive material 108 extending through the dielectric material 112. Conductive elements 108A may be referred to herein as “conductive lines,” “conductive traces,” “conductive pads,” or “conductive contacts.” A substrate 107 including such layers may be formed using a printed circuit board (PCB) fabrication technique, for example.
An individual layer of dielectric material 112 (e.g., a first dielectric material layer 112A) may include a cavity 119 and the bridge die 114-1 may be at least partially nested in the cavity 119. The bridge die 114-1 may be surrounded by (e.g., embedded in) a next individual layer of dielectric material 112 (e.g., a second dielectric material layer 112B. In some embodiments, a cavity 119 is tapered, narrowing towards a bottom surface of the cavity 119. A cavity 119 may be indicated by a seam between the dielectric material layer 112A and the dielectric material layer 112B. As shown in
The bridge die 114-1 is over a glass structure 116, also referred to as a glass patch. The glass structure 116 has an upper face that is coupled to the bridge die 114-1, and a lower face that is coupled to the substrate 107. The glass structure 116 is a layer of glass having a shape similar to the bridge die 114-1. For example, if the bridge die 114-1 has a length extending in the x-direction in the coordinate system shown, the glass structure 116 may have a length that is equal to or greater than (e.g., around 5% greater than, 10% greater than, or 20% greater than) the length of the bridge die 114-1. Similarly, if the bridge die 114-1 has a width extending in the y-direction in the coordinate system shown (e.g., into the drawing page), the glass structure 116 may have a width that is equal to or greater than (e.g., around 5% greater than, 10% greater than, or 20% greater than) the width of the bridge die 114-1. The glass structure 116 may have a height extending in the z-direction in the coordinate system shown that is in the range of 20-500 microns or a range therein, e.g., between 20 and 50 microns, or between 50 and 200 microns.
The glass structure 116 includes any glass material such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, alumino-borosilicate), soda-lime glass, soda-lime silica, borofloat glass, lead borate glass, photosensitive glass, non-photosensitive glass, or ceramic glass. In particular, the glass structure 116 may be bulk glass or a solid volume/layer of glass, as opposed to, e.g., materials that may include particles of glass, such as glass fiber reinforced polymers. Such glass materials are typically non-crystalline, often transparent, amorphous solids. In some embodiments, the glass structure 116 may be an amorphous solid glass layer. In some embodiments, the glass structure 116 may include silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass structure 116 may include a material, e.g., any of the materials described above, with a weight percentage of silicon being at least about 0.5%, e.g., between about 0.5% and 50%, between about 1% and 48%, or at least about 23%. For example, if the glass structure 116 is fused silica, the weight percentage of silicon may be about 47%. In some embodiments, the glass structure 116 may include at least 23% silicon and/or at least 26% oxygen by weight, and, in some further embodiments, the glass structure 116 may further include at least 5% aluminum by weight. In some embodiments, the glass structure 116 may include any of the materials described above and may further include one or more additives such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. In some embodiments, the glass structure 116 may be a layer of glass that does not include an organic adhesive or an organic material. In some embodiments, a cross-section of the glass structure 116 in an x-z plane, a y-z plane, and/or an x-y plane of the coordinate system may be substantially rectangular.
TGVs 117 extend through the glass structure 116. The TGVs 117 may include a conductive material, such as copper or another metal. The glass structure 116 may include TGV openings that are filled with a conductive material after the glass structure 116 is attached to the substrate 107. For example, openings for forming the TGVs 117 may be formed using a laser process, e.g., laser induced deep etching (LIDE), or a lithographic process, e.g., photolithography. Respective first conductive contacts 122 on the bottom surface of the bridge die 114-1 in the cavity 119 may be electrically coupled to respective TGVs 117 at the upper face of the glass structure 116. At the opposite face of the glass structure 116, the TGVs 117 are coupled to vias 118 through the dielectric material 112 below the glass structure 116. In the example of
In addition to the TGVs 117, in some embodiments, the glass structure 116 includes one or more passive devices. A passive device is a component that does not require an external power source to perform its intended function within an electronic circuit. Passive devices primarily manipulate electrical signals without adding or generating energy. The glass structure 116 may include passive components such as resistors, capacitors, inductors, filters, or transformers.
The substrate 107 may include N layers of conductive material 108, where N is an integer greater than or equal to one; in the accompanying drawings, the layers are labeled in descending order from the upper surface of the substrate 107 (e.g., layer N, layer N-1, layer N-2, etc.). In particular, as shown in
Although a particular number and arrangement of layers of dielectric material 112/conductive material 108 are shown in various ones of the accompanying figures, these particular numbers and arrangements are simply illustrative, and any desired number and arrangement of dielectric material 112/conductive material 108 may be used. Further, although a particular number of layers are shown in the substrate 107 (e.g., six layers), these layers may represent only a portion of the substrate 107, for example, fewer layers may be present, or further layers may be present (e.g., layers N-6, N-7, etc.). As shown in
The substrate 107 (e.g., further layers 111) may be coupled to a package substrate 102 by STPS interconnects 150. In particular, the top surface of the package substrate 102 may include a set of conductive contacts 146. Conductive contacts 144 on the bottom surface of the substrate 107 may be electrically and mechanically coupled to the conductive contacts 146 on the top surface of the package substrate 102 by the STPS interconnects 150. The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways to route power, ground, and signals through the dielectric material (e.g., including conductive traces and/or conductive vias, as shown). In some embodiments, the insulating material of the package substrate 102 may be a dielectric material, such as an organic dielectric material, a fire retardant grade 4 material (FR-4), BT resin, polyimide materials, glass reinforced epoxy matrix materials, organic dielectrics with inorganic fillers or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In particular, when the package substrate 102 is formed using standard PCB processes, the package substrate 102 may include FR-4, and the conductive pathways in the package substrate 102 may be formed by patterned sheets of copper separated by build-up layers of the FR-4. The conductive pathways in the package substrate 102 may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable. In some embodiments, the package substrate 102 may be formed using a lithographically defined via packaging process. In some embodiments, the package substrate 102 may be manufactured using standard organic package manufacturing processes, and thus the package substrate 102 may take the form of an organic package. In some embodiments, the package substrate 102 may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material, and creating conductive vias and lines by laser drilling and plating. In some embodiments, the package substrate 102 may be formed on a removable carrier using any suitable technique, such as a redistribution layer technique. Any method known in the art for fabrication of the package substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.
In some embodiments, the package substrate 102 may be a lower density medium and the die 114 may be a higher density medium or have an area with a higher density medium. As used herein, the term “lower density” and “higher density” are relative terms indicating that the conductive pathways (e.g., including conductive interconnects, conductive lines, and conductive vias) in a lower density medium are larger and/or have a greater pitch than the conductive pathways in a higher density medium. In some embodiments, a higher density medium may be manufactured using a modified semi-additive process or a semi-additive build-up process with advanced lithography (with small vertical interconnect features formed by advanced laser or lithography processes), while a lower density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using etch chemistry to remove areas of unwanted copper, and with coarse vertical interconnect features formed by a standard laser process). In other embodiments, the higher density medium may be manufactured using semiconductor fabrication process, such as a single damascene process or a dual damascene process. In some embodiments, additional dies may be disposed on the top surface of the dies 114-2, 114-3. In some embodiments, additional components may be disposed on the top surface of the dies 114-2, 114-3. Additional passive components, such as surface-mount resistors, capacitors, and/or inductors, may be disposed on the top surface or the bottom surface of the package substrate 102, or embedded in the package substrate 102.
The microelectronic assembly 100 of
The STPS interconnects 150 disclosed herein may take any suitable form. In some embodiments, a set of STPS interconnects 150 may include solder (e.g., solder bumps or balls that are subject to a thermal reflow to form the STPS interconnects 150), for example, as shown in
The DTD interconnects 130 disclosed herein may take any suitable form. The DTD interconnects 130 may have a finer pitch than the STPS interconnects 150 in a microelectronic assembly. In some embodiments, the dies 114 on either side of a set of DTD interconnects 130 may be unpackaged dies, and/or the DTD interconnects 130 may include small conductive bumps (e.g., copper bumps). The DTD interconnects 130 may have too fine a pitch to couple to the package substrate 102 directly (e.g., too fine to serve as DTS interconnects 140 or STPS interconnects 150). In some embodiments, a set of DTD interconnects 130 may include solder. In some embodiments, a set of DTD interconnects 130 may include an anisotropic conductive material, such as any of the materials discussed above. In some embodiments, the DTD interconnects 130 may be used as data transfer lanes, while the STPS interconnects 150 may be used for power and ground lines, among others. In some embodiments, some or all of the DTD interconnects 130 in a microelectronic assembly 100 may be metal-to-metal interconnects (e.g., copper-to-copper interconnects, or plated interconnects). In such embodiments, the DTD interconnect 130 may be bonded together (e.g., under elevated pressure and/or temperature) without the use of intervening solder or an anisotropic conductive material. Any of the conductive contacts disclosed herein (e.g., the conductive contacts 122, 124, 144, and/or 146) may include bond pads, solder bumps, conductive posts, or any other suitable conductive contact, for example. In some embodiments, some or all of the DTD interconnects 130 and/or the DTS interconnects 140 in a microelectronic assembly 100 may be solder interconnects that include a solder with a higher melting point than a solder included in some or all of the STPS interconnects 150. For example, when the DTD interconnects 130 and the DTS interconnects 140 in a microelectronic assembly 100 are formed before the STPS interconnects 150 are formed, solder-based DTD interconnects 130 and DTS interconnects 140 may use a higher-temperature solder (e.g., with a melting point above 200 degrees Celsius), while the STPS interconnects 150 may use a lower-temperature solder (e.g., with a melting point below 200 degrees Celsius). In some embodiments, a higher-temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, a lower-temperature solder may include tin and bismuth (e.g., eutectic tin bismuth) or tin, silver, and bismuth. In some embodiments, a lower-temperature solder may include indium, indium and tin, or gallium.
In the microelectronic assemblies 100 disclosed herein, some or all of the DTS interconnects 140 and the STPS interconnects 150 may have a larger pitch than some or all of the DTD interconnects 130. DTD interconnects 130 may have a smaller pitch than STPS interconnects 150 due to the greater similarity of materials in the different dies 114 on either side of a set of DTD interconnects 130 than between the substrate 107 and the top level dies 114-2, 114-3 on either side of a set of DTS interconnects 140, and between the substrate 107 and the package substrate 102 on either side of a set of STPS interconnects 150. In particular, the differences in the material composition of a substrate 107 and a die 114 or a package substrate 102 may result in differential expansion and contraction due to heat generated during operation (as well as the heat applied during various manufacturing operations). To mitigate damage caused by this differential expansion and contraction (e.g., cracking, solder bridging, etc.), the DTS interconnects 140 and the STPS interconnects 150 may be formed larger and farther apart than DTD interconnects 130, which may experience less thermal stress due to the greater material similarity of the pair of dies 114 on either side of the DTD interconnects. In some embodiments, the DTS interconnects 140 disclosed herein may have a pitch between 25 microns and 250 microns. In some embodiments, the STPS interconnects 150 disclosed herein may have a pitch between 55 microns and 1000 microns, while the DTD interconnects 130 disclosed herein may have a pitch between 25 microns and 100 microns.
The microelectronic assembly 100 of
Although
Many of the elements of the microelectronic assembly 100 of
Any suitable techniques may be used to manufacture the microelectronic assembly 100 disclosed herein.
At 205, a dielectric layer (e.g., a layer of the dielectric material 112) is deposited on a substrate, e.g., a first portion of the substrate 107.
The preliminary substrate further includes a dielectric material 304, which may be the dielectric material 112, and patterned conductive material 306. In this example, the dielectric material 304 and conductive material 306 are on either side of the carrier 302. In other examples, the dielectric material 304 and/or conductive material 306 may only be on the upper side of the carrier 302. The patterned conductive material 306 in the dielectric material 304 on the upper side of the carrier 302 may include at least the N-5 and N-4 metal layers shown in
At 210, a glass structure is attached to the substrate.
At 215, via openings in the dielectric material under the glass structure are etched. The glass structure with the via openings acts as a mask for etching via openings in the dielectric material below the glass structure. This results in via openings that are precisely aligned with the glass structure; the via openings may also be referred to as self-aligned via openings, because the via openings are aligned to the layer above them (i.e., the glass structure).
At 220, a seed layer is deposited. The seed layer is a suitable material for growing regions of another material, e.g., copper or another conductive material. In general, a seed layer is a thin initial coating of a material (e.g., a metal) that acts as a nucleation site for a subsequent growth process. Various deposition techniques can be used to deposit the seed layer, including, e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.
At 225, a resist is deposited and patterned. For example, a photoresist is deposited over the seed layer 326, e.g., using spin coating. The photoresist is then patterned, which changes a physical property of a portion of the photoresist. For example, a patterned mask may be arranged over the photoresist, and some portions of the photoresist are exposed to patterned actinic radiation through the patterned mask. Some portions of the photoresist (either the exposed portions or the non-exposed portions, depending on the chemistry) can then be removed through a developing process to form openings in the photoresist layer.
At 230, a conductive material is formed in the patterned openings of the resist. For example, copper or another metal may be grown using an electroless deposition or electroplating process. The conductive material is deposited or plated over the seed material.
The conductive material 306 further forms the TGVs 332 that extend through the glass structure 308, from the top face of the glass structure 308 to the bottom face of the glass structure 308. In addition, the conductive material 306 forms the aligned vias 336 below the TGVs 332. The aligned vias 336 are formed in the dielectric material 304 to couple the TGVs 332 to traces below the glass structure 308, and the aligned vias 336 are aligned to the TGVs 332. Furthermore, in this example, a layer 338 of the conductive material 306 is formed over the top of the glass structure 308.
At 235, the resist and the exposed seed layer are removed. For example, the resist is removed through a first chemical process (e.g., a wet etch or a dry etch), and the portions of the seed layer that were under the resist are then removed through a second chemical process (e.g., a wet etch or a dry etch).
At 240, additional dielectric is filled between the vias and glass structure and the assembly is planarized. The deposition of additional dielectric layers may be performed using any of the methods described above. A top surface of the dielectric material 304 and the top surface of the glass structure 308, and in particular, the conductive region 338 formed over the glass structure 308, may be planarized using CMP or any other suitable process.
At 245, additional metal layers are built over the substrate. In particular, additional layers of dielectric may be formed over the substrate, and additional metal layers formed therein.
At 250, a cavity is etched in the dielectric material of the substrate, and in particular, in the at least a portion of the region of the substrate formed over the glass structure 308. The cavity may be formed using any suitable techniques, such as laser patterning techniques or lithography. The cavity may extend to a top surface of the glass structure 308.
At 255, a bridge die is bonded to the glass structure. A lower face of the bridge die may be bonded to the upper face of the glass structure using direct bonding or hybrid bonding. Direct bonding includes metal-to-metal bonding techniques, e.g., copper-to-copper bonding, or other techniques in which bonding contacts of opposing bonding interfaces are brought into contact first, then subject to heat and compression. Hybrid bonding includes techniques in which bonding dielectric of opposing bonding interfaces, possibly first subjected to prior surface activation, are brought into contact first, then subject to heat and sometimes compression, or techniques in which the bonding contacts and the bonding dielectric, possibly first subjected to prior surface activation, of opposing bonding interfaces are brought into contact substantially simultaneously, and the subject to heat and sometimes compression. Thus, hybrid bonding includes both metal-to-metal bonding at the bonding contacts as well as dielectric-to-dielectric bonding in regions between the contacts. The materials of opposing bonding dielectrics can be homogeneous (i.e., have substantially the same material composition) or non-homogeneous (i.e., have different material compositions).
At 260, additional metal layers are built, and dies are attached to the substrate. In particular, additional layers of dielectric may be formed over the substrate (including over the bridge die), and additional metal layers formed therein. Additional dies, such as the dies 114-2 and 114-3 described with respect to
In some embodiments, a layer of material, such as a decomposable polymer, is deposited over the glass patch, prior to cavity formation and bonding of the bridge die. This layer of material may protect the glass structure and TGVs during cavity formation.
As described above, in some embodiments, a glass patch, e.g., the glass structure 116 illustrated in
In this example, two contacts 714a and 714b are coupled to the passive component 712, and may be coupled to corresponding contacts on a bridge die. In other embodiments, more or fewer contacts may be included, e.g., based on the number of passive devices included in the passive component 712. The contacts 714a and 714b are in a dielectric layer 716. The dielectric layer 716 may be a layer between the glass structure 116 and the bridge die 114 that is fabricated as part of the substrate 107. Alternatively, the dielectric layer 716 may be part of the glass structure 710, e.g., the dielectric layer 716 may include glass, or a layer that is formed over the glass structure 710 during fabrication of the glass structure 710 and prior to attaching the glass structure 710 to a substrate (e.g., the substrate 107). The TGVs 718 also extend through the dielectric layer 716 (e.g., if the dielectric layer 716 is a glass layer and/or part of the glass structure 710), or are coupled to vias in the dielectric layer 716 (e.g., if the dielectric layer 716 is formed over the glass structure 710 in the substrate 107). While the contacts 714 are both illustrated as extending to an upper surface of the glass structure 710, in other embodiments, one or more contacts may extend downward from the passive component 712, e.g., to receive an input power from a contact in the substrate that is below the glass structure (when it is embedded in the substrate).
The inductor 722 may be formed by etching a portion of the glass structure 720 and filling the etched portion with the conductive material 306. In some embodiments, the conductive material 306 may be deposited after the glass structure 720 has been mounted to a substrate (e.g., the substrate 107), e.g., the conductive material 306 forming the inductor 722 may be deposited in the process 230 for filling the TGVs 728. In other embodiments, the conductive material 306 may be deposited in the glass structure 720 before the glass structure 720 is mounted in a substrate; in such embodiments, the conductive material 306 may be protected (e.g., by a mask or blocking material) during further processing of the substrate, as described with respect to
In this example, two contacts 724a and 724b are coupled to the inductor 722, and may be coupled to corresponding contacts on a bridge die. The contacts 724a and 724b are in a dielectric layer 726. The arrangement of the contacts 724 and dielectric layer 726 may be similar to the contacts 714 and dielectric layer 716 described with respect to
In this example, an upper dielectric layer 736a, which may be similar to the dielectric layer 716, is along a top of or over top of the glass structure 730, and a lower dielectric layer 736b is along the bottom of or below the base of the glass structure 730. Connections between inductor TGVs may be formed along or within the upper and lower dielectric layers 736. The contacts 734a and 734b are similar to the contacts 714 and 724.
The microelectronic assemblies 100 disclosed herein may be included in any suitable electronic component.
The IC device 1600 may include one or more device layers 1604 disposed on the die substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in
Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is to be a PMOS or a NMOS transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1602 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1602 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1602. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1620 may be formed within the die substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S/D regions 1620 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1602 may follow the ion-implantation process. In the latter process, the die substrate 1602 may first be etched to form recesses at the locations of the S/D regions 1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1620 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1620.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1640) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in
The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in
In some embodiments, the interconnect structures 1628 may include lines 1628a and/or vias 1628b filled with an electrically conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1602 upon which the device layer 1604 is formed. For example, the lines 1628a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in
A first interconnect layer 1606 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., the S/D contacts 1624) of the device layer 1604.
A second interconnect layer 1608 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual damascene process) in some embodiments.
A third interconnect layer 1610 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device layer 1604) may be thicker.
The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In
In some embodiments in which the IC device 1600 is a double-sided die (e.g., like the die 114-1), the IC device 1600 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1604. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1606-1610, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 1604 and additional conductive contacts (not shown) on the opposite side of the IC device 1600 from the conductive contacts 1636.
In other embodiments in which the IC device 1600 is a double-sided die (e.g., like the die 114-1), the IC device 1600 may include one or more TSVs through the die substrate 1602; these TSVs may make contact with the device layer(s) 1604, and may provide conductive pathways between the device layer(s) 1604 and additional conductive contacts (not shown) on the opposite side of the IC device 1600 from the conductive contacts 1636.
In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate. In some embodiments the circuit board 1702 may be, for example, a circuit board.
The IC device assembly 1700 illustrated in
The package-on-interposer structure 1736 may include an IC package 1720 coupled to an interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in
In some embodiments, the interposer 1704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to TSVs 1706. The interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.
The IC device assembly 1700 illustrated in
Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in
The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMLS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1812 may include multiple communication chips. For instance, a first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications, and a second communication chip 1812 may be dedicated to wired communications.
The electrical device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).
The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the electrical device 1800, as known in the art.
The electrical device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1800 may have any desired form factor, such as a computing device or a hand-held, portable or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server, or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an assembly including a substrate; a bridge component in the substrate, the bridge component including a first plurality of conductive contacts at a first face of the bridge component and a second plurality of conductive contacts at a second face of the bridge component, the second face opposite the first face; and a glass structure in the substrate, a face of the glass structure coupled to the second face of the bridge component.
Example 2 provides the assembly of example 1, where the glass structure has a plurality of conductive vias therein, where one of the conductive vias is coupled to one of the second plurality of conductive contacts.
Example 3 provides the assembly of example 2, the substrate including a layer below the glass structure, the layer including a conductive via therein, where the conductive via in the layer of the substrate is aligned with one of the plurality of conductive vias in the glass structure.
Example 4 provides the assembly of example 3, where the conductive via in the glass structure has a first width, the conductive via in the layer of the substrate has a second width, and the first width and the second width are within 2 microns of each other.
Example 5 provides the assembly of example 3 or 4, where a midline of the conductive via in the glass structure is within 0.2 micron of a midline of the conductive via in the layer of the substrate.
Example 6 provides the assembly of any of the preceding examples, where the face of the glass structure is coupled to the second face of the bridge component with direct metal-to-metal bonds.
Example 7 provides the assembly of any of the preceding examples, where the face of the glass structure has a first length, and the second face of the bridge component has a second length, the first length greater than the second length.
Example 8 provides the assembly of example 7, where the face of the glass structure has a first width, the first width extending in a direction perpendicular to the first length, and the second face of the bridge component has a second width, the first width greater than the second width.
Example 9 provides the assembly of example 7, further including an air gap in the substrate, the air gap over the glass structure and next to a lower portion of the bridge component.
Example 10 provides the assembly of any of the preceding examples, where the glass structure includes a glass material surrounding a plurality of through-glass vias, the glass material including at least 23% silicon by weight.
Example 11 provides the assembly of any of the preceding examples, where the glass structure includes a glass material surrounding a plurality of through-glass vias, the glass material including at least 26% oxygen by weight.
Example 12 provides the assembly of any of the preceding examples, where the glass structure includes a glass material surrounding a plurality of through-glass vias, the glass material including at least 23% silicon by weight and at least 26% oxygen by weight.
Example 13 provides the assembly of any of the preceding examples, where the glass structure includes a glass material surrounding a plurality of through-glass vias, the glass material including at least 5% aluminum by weight.
Example 14 provides the assembly of any of the preceding examples, where the glass structure does not include an organic adhesive or an organic material.
Example 15 provides the assembly of any of the preceding examples, where the glass structure includes an embedded passive component.
Example 16 provides the assembly of example 15, where the passive component is an inductor.
Example 17 provides the assembly of example 15, where the passive component is a capacitor.
Example 18 provides a microelectronic assembly, including a substrate; a bridge component in the substrate, the bridge component including a first plurality of conductive contacts at a first face of the bridge component and a second plurality of conductive contacts at a second face of the bridge component, the second face opposite the first face; a glass structure in the substrate, a face of the glass structure coupled to the second face of the bridge component; and a microelectronic component having a first face and an opposing second face, the first face of the microelectronic component is between the second face of the microelectronic component and the substrate, the microelectronic component includes conductive contacts at the first face of the microelectronic component, and a conductive contact of the microelectronic component is conductively coupled to one of the first plurality of conductive contacts at the first face of the bridge component.
Example 19 provides the microelectronic assembly of example 18, where a second conductive contact of the microelectronic component is conductively coupled to a conductive contact of the substrate at the face of the substrate.
Example 20 provides the microelectronic assembly of example 18 or 19, further including a second microelectronic component including a second conductive contact at a face of the second microelectronic component, the second conductive contact conductively coupled to a second one of the first plurality of conductive contacts at the first face of the bridge component.
Example 21 provides an assembly including a glass patch having a first face and a second face opposite the first face; a first die having a first face and a second face, the second face of the first die coupled to the first face of the glass patch; a second die having a face coupled to the first face of the first die; and a third die having a face coupled to the first face of the first die.
Example 22 provides the assembly of example 21, where the first face of the glass patch has a surface area at least as large as a surface area of the second face of the first die.
Example 23 provides the assembly of example 21 or 22, where the glass patch has a through-glass via (TGV) formed therein, the assembly further including a conductive via coupled to the TGV at the second face of the glass patch, the conductive via aligned to the TGV.
Example 24 provides an assembly including a substrate; a bridge component in the substrate, the bridge component including a first plurality of conductive contacts at a first face of the bridge component and a second plurality of conductive contacts at a second face of the bridge component, the second face opposite the first face; a glass structure in the substrate, a face of the glass structure coupled to the second face of the bridge component; and a passive component in the glass structure.
Example 25 provides the assembly of example 24, the passive component including an inductor.
Example 26 provides the assembly of example 24, the inductor including a magnetic material and a conductive material.
Example 27 provides the assembly of any of examples 24 through 26, the passive component coupled to a conductive contact, the conductive contact coupled to one of the second plurality of conductive contacts at the second face of the bridge component.
