Patent Application
20180040589
The subject matter of this application relates to microelectronic packages and assemblies in which a plurality of microelectronic packages are stacked with one another and electrically interconnected with a circuit panel.
Semiconductor dies or chips are flat bodies with contacts disposed on the front surface that are connected to the internal electrical circuitry of the chip itself. Semiconductor chips are typically packaged with substrates to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit, e.g., a circuit in an electronic product such as a computer, tablet, smartphone or other mobile device.
In order to save space certain conventional designs have stacked multiple microelectronic elements or semiconductor chips within a package. This allows the package to occupy a surface area on a substrate that is less than the total surface area of the chips in the stack. However, conventional stacked packages have disadvantages of complexity, cost, thickness and testability.
In spite of the above advances, there remains a need for improved stacked packages and especially stacked chip packages which incorporate multiple chips for certain types of memory, e.g., flash memory. There is a need for such packages and assemblies which are reliable, thin, testable and that are economical to manufacture.
Computing systems need to provide access to data and instructions from a memory storage array during execution of a program by a processor (e.g., microprocessor or other form of central processing unit (“CPU”)). Such systems typically include a processor which can function as a memory channel control element, or may include a processor having a memory channel control element incorporated thereon, or a stand-alone memory channel control element which communicates with the processor to store and retrieve data and/or instructions from microelectronic elements separate from the processor which have memory storage arrays thereon. The memory control element typically controls traffic, i.e., data, address, clock and command signals on a signaling bus between the memory storage array and the CPU. In some cases, instructions can be stored to the one or more memory storage arrays and retrieved from the one or more memory storage arrays for execution by the processor.
Traditionally, microelectronic elements are assembled together in microelectronic packages which are surface-mounted to a major surface of a circuit panel, wherein planes defined by major surfaces of the microelectronic elements, e.g., semiconductor chips, are oriented in parallel with the major surface of the circuit panel. However, in a microelectronic assembly 100 as seen, for example, in
Such non-parallel or orthogonal orientations permit a relatively large number of microelectronic elements to be accommodated within a given area of the major surface of the circuit panel, the microelectronic elements being electrically coupled with conductors on the circuit panel. However, increasing the number of microelectronic elements coupled to a signal bus can exacerbate loading on the signal bus when all other factors remain the same. A large number of microelectronic elements coupled to the same bus controlled by a single memory channel control element can cause adverse (multi-drop) loading effects to increase, among which may include any or all of the following: increased intersymbol interference, lowered signal amplitudes, increased rise time and increased fall time, and reduced eye width and reduced eye height. As a consequence, the speed at which signals can be transmitted in an assembly with increased loading tends to fall. The decrease in speed can be substantial, i.e., 50% or more of the speed in cases where loading on a signaling bus is increased by a factor or four or eight, for example.
In an embodiment of the invention provided herein, the increased loading effects can be mitigated by conditioning, e.g., amplifying signals on the signaling bus at points between the memory channel control element and the microelectronic elements. In one embodiment, amplification can be performed in the analog domain, which in some cases can permit a type of circuitry required to perform the conditioning to be relatively simple, and in some cases, relatively compact in terms of the external volume required by the conditioning circuitry. The conditioning circuitry, e.g., analog amplifying circuitry in accordance with such embodiment, can be referred to as a “redriver assembly” which includes a plurality of individual “redrivers”. A redriver typically contains no clock data recovery (CDR), and amplifies the signal magnitude without performing retiming functionality. Each such redriver is electrically coupled to a signaling path of a signaling bus at a point remote from the memory channel control element at a first side of the redriver, and at a second side of the redriver opposite the first side, the redriver is coupled to a signaling path to which a microelectronic element is coupled. In one example, some of the redrivers are each configured to amplify, in the analog domain, a signal received from the memory channel control element and output the amplified signal to a microelectronic element. In such example, others of the redrivers may each be configured to amplify, in the analog domain, a signal received from a microelectronic element and output the amplified signal to the memory channel control element.
In variations of any of the above-described microelectronic assemblies, the repeater assembly takes the form of a “retimer” assembly having a plurality of retimers thereon in the above-described embodiments, where each retimer of the retimer assembly takes the place of each redriver of the redriver assembly. A retimer usually contains CDR, and functions differently from a redriver, in that the retimer receives and regenerates the signal anew that is to be driven at the input of the retimer. The retimer can be considered a buffer or isolator device between a generator of a signal, e.g., the memory channel control element and a consumer of that signal, which in some cases can be the microelectronic element having a memory storage array thereon. As such, the retimer “isolates” the output from the input through retransmitting signals with newly generated amplitudes and phases. The redriver and the retimer are two types of repeaters that the repeater assembly may include.
In one embodiment disclosed, a microelectronic assembly includes a circuit panel having a plurality of first contacts at a major surface thereof. One or more microelectronic packages comprise a plurality of microelectronic elements, the one or more packages having terminals electrically coupled with the first contacts, wherein each package includes at least one microelectronic element having a face, and element contacts at the face which are electrically coupled with the plurality of terminals. A repeater assembly is configured to condition one or more signals received from a memory channel control element including one or more signals selected from: an address signal, a command signal, or a data signal, such that the plurality of the microelectronic elements are coupled to the at least one repeater assembly to receive the conditioned signals. Conditioning signals by the repeater assembly improves one or more of: signal strength or a signal-to-noise ratio of the signals at the respective inputs to the microelectronic elements, or at the inputs to the memory channel control element, or at both the inputs to the microelectronic elements and at the inputs to the memory channel control element. In one example, the repeater assembly may additionally be configured with terminating circuitry, such that signaling paths extending from the repeater assembly to microelectronic elements or microelectronic packages of the assembly which contain them have terminations appropriate for the signaling paths between the repeater assembly and the circuit panel. In this way, signal reflections along paths between the microelectronic elements and the memory channel control element can be addressed and reduced, thereby improving signal-to-noise ratio in the signals transmitted between the memory channel control element and the microelectronic elements. In any of these examples, other aspects of signal quality, such as rise time, fall time and eye width/height may be improved and intersymbol interference may be reduced.
Each package may include a single microelectronic element 112, or in the particular case seen in
As used in this disclosure with reference to a dielectric region or a dielectric structure of a component, e.g., circuit structure, interposer, microelectronic element, capacitor, voltage regulator, circuit panel, substrate, etc., a statement that an electrically conductive element is “at” a surface of the dielectric region or component indicates that, when the surface is not covered or assembled with any other element, the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to that surface of the dielectric region from outside the dielectric region or component. Thus, a terminal or other conductive element which is at a surface of a dielectric region may project from such surface; may be flush with such surface; or may be recessed relative to such surface in a hole or depression in the dielectric region.
Each microelectronic element 112 has a front surface 114 defining a respective plane 116-x of a plurality of planes 116-1, 116-2, etc. Each microelectronic element 112 may have a plurality of contacts 118 at a front surface thereof at or near a peripheral edge surface 120 of the chip, with a rear surface 122 opposite the front surface, and the interconnect edge surface 120 extending between the front and rear surfaces. Commonly available flash memory semiconductor chips, such as the NAND and NOR type flash memory chips mentioned below, typically have their chip contacts disposed at the front surface near a single peripheral edge surface 120 of the semiconductor chip. Although the front surfaces of each of the chips in the package stack are shown all oriented in the same direction in
As best seen in
In one example, each of the microelectronic elements includes one or more memory storage arrays, which may include a particular memory type such as nonvolatile memory. Nonvolatile memory can be implemented in a variety of technologies some of which include memory cells that incorporate floating gates, such as, for example, flash memory, and others which include memory cells which operate based on magnetic polarities. Flash memory chips are currently in widespread use as solid state storage as an alternative to magnetic fixed disk drives for computing and mobile devices. Flash memory chips are also commonly used in portable and readily interchangeable memory drives and cards, such as Universal Serial Bus (USB) memory drives, and memory cards such as Secure Digital or SD cards, microSD cards (trademarks or registered trademarks of SD-3C), compact flash or CF card and the like. Flash memory chips typically have NAND or NOR type devices therein; NAND type devices are common. Other examples of microelectronic elements 112 include one or more of DRAM, microprocessor or controller chips or combinations thereof. Each semiconductor chip may be implemented in one of various semiconductor materials such as silicon, germanium, and gallium arsenide or one or more other Group III-V semiconductor compounds or Group II-VI semiconductor compounds, etc. The microelectronic elements 112 in one or more microelectronic packages 108 and in one or more “package stacks” 110 may be a combination of different chip functionalities as described above and may comprise a combination of various different semiconductor materials as described above. In one embodiment, a microelectronic element may have a greater number of active devices for providing memory storage array function than for any other function.
In one embodiment, each package 108 of the package stack 110 includes a dielectric element 130 having a major surface 132 which defines a plane 134. The dielectric element 130 may have one or multiple layers of dielectric material and one or multiple electrically conductive layers thereon. The dielectric element 130 can be formed of various materials, which may or may not include a polymeric component, and may or may not include an inorganic component. Alternatively, the substrate may be wholly or essentially polymeric or may be wholly or essentially inorganic. In various non-limiting examples, the dielectric element can be formed of a composite material such as glass-reinforced epoxy, e.g., FR-4, or glass or ceramic material.
A plurality of electrically conductive package contacts 124, 126 are disposed at an interconnect region 136 of the dielectric element 130 adjacent an interconnect edge 138 of the dielectric element 130. In one example seen in
Element contacts 118 at front surfaces 114 of each microelectronic element of the package 108 are electrically coupled with the package contacts 124, 126 such as through leads 128 which may include, for example, wire bonds coupled to the microelectronic elements 112 arranged in an offset or staggered arrangement such as seen in
Each package contact 124, 126 may extend to the interconnect edge 138 of the package 108 in an interconnect region 136 which may extend from a peripheral edge or “remote surface” of the respective package 108. In some cases, a dielectric region or insulating encapsulant region 140 may contact the element contacts 118 at the front surface of each microelectronic element 112 and may overlie a portion of the major surface 132 of the dielectric element 130. In one example, as seen in
As mentioned above, all package interconnects of a package typically are available for connection at an interconnect region adjacent the same interconnect edge 138 of the package. As further seen in
In particular examples, the electrically conductive material 127 may be conductive masses, conductive pillars, stud bumps or other suitable electrically conductive material may be used to electrically connect each of the package contacts 124, 126 with a corresponding panel contact 162. Here, the conductive material 127 can be in form of electrically conductive bumps such as masses of solder, tin, indium or eutectic material, or drops or droplets of electrically conductive polymer material or electrically conductive ink on surfaces of the panel contacts 162 and contacting the corresponding package contacts 124, 126. In one example, the electrically conductive material 127 may be applied to the panel contacts 162, the package contacts 124, 126, or both the package contacts and the panel contacts through a transfer mold of solder bumps, balls or features, or application of solder balls, for example, or may alternatively be deposited on the substrate contacts by plating or depositing a metal or other conductive material. Alternatively, the electrically conductive material 127 can be applied by depositing one of the above-mentioned electrically conductive polymer or electrically conductive ink or any other electrically conductive materials. In one example, the electrically conductive material may be as disclosed in the incorporated U.S. Pat. No. 8,178,978.
In one example, the circuit panel can be a motherboard. In another example, the circuit panel 160 can be a daughter board, module board or other board or circuit panel configured for electrical connection within a system which includes the microelectronic package stack 110 and circuit panel. The panel contacts 162 can be configured for surface mounting to another component which can be a card, tray, motherboard, etc., such as via a land grid array (LGA), ball grid array (BGA), or other technique. As in the case of the dielectric element 130, the circuit panel 160 may include a dielectric element or other substrate which may have one or multiple layers of dielectric material and one or multiple electrically conductive layers thereon. The circuit panel 160 can be formed of various materials, which may or may not include a polymeric component, and may or may not include an inorganic component. Alternatively, the circuit panel may be wholly or essentially polymeric or may be wholly or essentially inorganic. In various non-limiting examples, the support element can be formed of a composite material such as glass-reinforced epoxy, e.g., FR-4, a semiconductor material, e.g., Si or GaAs, or glass or ceramic material.
In a variation of the microelectronic assembly seen in
Referring now to
Memory channel control element 250 may only be capable of driving signals to a limited number of receivers thereof. In one example, the control element 250 may only be capable of driving signals to eight receivers of the signals. Thus, if the memory channel control element 250 were coupled directly to the microelectronic elements 112, the control element 250 might only be capable of driving signals to eight microelectronic elements 112. However, with the addition of the repeater assembly 260, each repeater of the repeater assembly 260 can be electrically coupled with the contacts of a plurality of microelectronic elements 112. Thus, in one example, each repeater of the repeater assembly can be electrically coupled in parallel with the contacts of two microelectronic elements 112 of the assembly, and in that case, increase the number of microelectronic elements 112 to which signals can be driven from the memory channel control element 250 by a factor of two, such that one memory channel control element 260 is capable of driving signals to sixteen microelectronic elements. In other examples, each repeater of the repeater assembly can be electrically coupled in parallel with the contacts of four microelectronic elements 112, and in such case, increase the number of microelectronic elements 112 to which signals can be driven from the memory channel control element 250 by a factor of four. In still other examples, each repeater of the repeater assembly can be electrically coupled in parallel with the contacts of eight or sixteen microelectronic elements 112, and in such case, increase the number of microelectronic elements 112 to which signals can be driven from the memory channel control element 250 by a factor of eight, or by a factor of sixteen. In such examples the microelectronic assembly with the memory channel control element 250 and repeater assembly thereon are configured to drive signals to 64 or 128 microelectronic elements, respectively.
In a particular implementation as seen in
With further reference to
In a particular variation of the microelectronic assembly 300 seen in
As seen in
As further seen in
In a variation thereof, as seen in
Referring now to
Referring now to
In another variation as seen in
As seen in
In further variations of any of the above-described microelectronic assemblies, another component may take the place of the repeater assembly, or may be added to the microelectronic assembly in each case. In particular examples, a temperature sensor or a Bluetooth controller can be provided in the assembly, such as can be used for remote monitoring of the microelectronic elements therein. In other examples, an error correction code (“ECC”) encoder/decoder element, or a passives element or “IPOC” (integrated passives on chip element) can be provided for capacitive decoupling of the microelectronic elements in the microelectronic assembly from the external system. In another example, a master-slave arrangement of microelectronic elements can be implemented having a master microelectronic element in place of the repeater assembly, and the slave microelectronic elements provided at the positions where the microelectronic elements are shown.
In another example, a “gearbox” or serializer-deserializer (“SERDES”) component could be provided in the place of the repeater assembly in any of the examples shown above. The modified microelectronic assembly in each case could be used in an example in which a traditional memory channel control element is coupled to a motherboard of the system and is configured to transmit parallel signals to a second SERDES associated with the motherboard. The serial output of the second SERDES, in turn, is coupled with inputs to one or more SERDES devices of the microelectronic assembly, which are then configured to deserialize the received serial signals and distribute them in parallel to the microelectronic elements or the microelectronic packages in the assembly.
Going out from each microelectronic assembly, the SERDES of each microelectronic assembly can be coupled to receive parallel signals from each microelectronic package or microelectronic element. The SERDES of each microelectronic assembly then is coupled to the second SERDES associated with the motherboard so as to transmit the serialized signals from the SERDES outputs from each microelectronic assembly to the second SERDES. The second SERDES, in turn, deserializes the received serial signals into parallel signals which then are output to the memory channel control element.
In a further variation, the SERDES associated with the motherboard could be integrated into the memory channel control element.
Although not specifically shown in the Figures or particularly described in the foregoing, elements in the various Figures and various described embodiments can be combined together in additional variations of the invention.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the various embodiments described herein. It is therefore to be understood that numerous modifications can be made to the illustrative embodiments and that other arrangements can be devised without departing from the spirit and scope of the embodiments as specifically provided or claimed herein.
