Patent Application
20180190761
The present application relates to semiconductor technology and, more particularly, to a semiconductor structure containing a metal-insulator-metal (MIM) capacitor structure that has enhanced capacitance, and a method of forming the same.
On-chip MIM capacitors are known in the art. The on-chip MIM capacitors are typically integrated with mixed signal circuits or radio frequency (RF) circuits and may serve as decoupling capacitors to provide improved voltage regulation and noise immunity for power distribution.
To ensure a minimal capacitance, a large chip area is usually used for the on-chip MIM capacitor which, in turn, adversely increases the chip size and thus the cost of the chip. Thus, there is a need for providing on-chip MIM capacitors that have enhanced capacitance without increasing the size of the chip or the cost of the chip.
It is one object of the invention to provide a three-dimensional (3D) MIM capacitor with increased capacitance.
According to one aspect of the disclosure, a metal-insulator-metal (MIM) capacitor is disclosed. The MIM capacitor includes a substrate having a first dielectric layer thereon and a bottom electrode embedded in the first dielectric layer. The bottom electrode includes a metal plate and a three-dimensional (3D) metal structure protruding from a top surface of the metal plate. A second dielectric layer surrounds the 3D metal structure. A capacitor dielectric layer covers the 3D metal structure and the second dielectric layer. A top electrode is disposed on the capacitor dielectric layer. The top electrode has fins that interdigitate with the 3D metal structure.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various drawings.
The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:
In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural changes may be made without departing from the scope of the present disclosure.
The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
The term “substrate” used herein includes any structure having an exposed surface onto which a layer is deposited according to the present invention, for example, to form the integrated circuit (IC) structure. The term “substrate” is understood to include semiconductor wafers. The term “substrate” is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon.
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According to one embodiment, the substrate 100 may comprise a main surface 100a. On or in the main surface 100a, for example, a plurality of semiconductor elements such as MOS transistors (not shown) may be fabricated. According to one embodiment, at least one dielectric layer 110 such as an inter-metal dielectric (IMD) layer is deposited on the main surface 100a. For example, the dielectric layer 110 may comprise silicon oxide, silicon nitride, silicon oxy-nitride, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), but is not limited thereto.
According to one embodiment, at least one damascened metal plate 112 is formed in the dielectric layer 110 within a capacitor forming region CR. Optionally, a damascened metal wire 114 may be formed in the dielectric layer 110 outside the capacitor forming region CR. According to one embodiment, the damascened metal plate 112 and the damascened metal wire 114 may be formed by using copper damascene processes known in the art. According to one embodiment, the damascened metal plate 112 and the damascened metal wire 114 may be formed in a first metal layer or M1.
For example, the damascened metal plate 112 may comprise a copper layer 120a and a diffusion barrier 122a surrounding the copper layer 120a. The diffusion barrier 122a, such as Ti/TiN, Ta/TaN or the like, may prevent copper from diffusing into the dielectric layer 110. Likewise, the damascened metal wire 114 may comprise a copper layer 120b and a diffusion barrier 122b surrounding the copper layer 120b.
Typically, during the copper damascene process, a chemical-mechanical polishing (CMP) may be performed to remove the excess copper from top surface 110a of the dielectric layer 110. Therefore, at this point, top surface 112a of the damascened metal plate 112 and top surface 114a of the damascened metal wire 114 may be flush with the top surface 110a of the dielectric layer 110.
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At this point, the 3D metal structure 140 protrudes from the top surface 112a of the damascened metal plate 112. According to one embodiment, the 3D metal structure 140 and the damascened metal plate 112 together constitute a bottom electrode 210 of a MIM capacitor.
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In one embodiment, the capacitor dielectric layer 220 may be a high-k material having a dielectric constant greater than silicon dioxide. Exemplary high-k dielectrics include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, SrTiOxNy, LaAlOxNy, Y2OxNy, SiON, SiNx, a silicate thereof, and an alloy thereof.
Subsequently, a top electrode 230 is formed on the capacitor dielectric layer 220 within the capacitor forming region CR. The top electrode 230 completely fills up the recesses 162, thereby forming fins 230a that interdigitate with the 3D metal structure 140. The top electrode 230 is capacitively coupled to the bottom electrode 210 through the capacitor dielectric layer 220.
The top electrode 230 may be formed by using a method that is similar to the process used to form the 3D metal structure 140 as previously mentioned. For example, a seed layer (not shown) may be deposited in a blanket manner, and then a photoresist layer is formed on the seed layer, followed by a self-alignment plating process. After removing the photoresist layer, the excess seed layer is removed.
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Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
