Patent Application
20230335423
Embodiments of the present disclosure relate generally to semiconductor processing, and more particularly to multi-chamber semiconductor processing systems with transfer robot temperature adjustment.
The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area.
While some integrated device manufacturers (IDMs) design and manufacture integrated circuits (IC) themselves, fabless semiconductor companies outsource semiconductor fabrication to semiconductor fabrication plants or foundries. Semiconductor fabrication consists of a series of processes in which a device structure is manufactured by applying a series of layers onto a substrate. This involves the deposition and removal of various dielectric, semiconductor, and metal layers. The areas of the layer that are to be deposited or removed are controlled through photolithography. Each deposition and removal process is generally followed by cleaning as well as inspection steps. Therefore, both IDMs and foundries rely on numerous semiconductor equipment and semiconductor fabrication materials, often provided by vendors. There is always a need for customizing or improving those semiconductor equipment and semiconductor fabrication materials, which results in more flexibility, reliability, and cost-effectiveness.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Some of the features described below can be replaced or eliminated and additional features can be added for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.
A multi-chamber semiconductor processing system is commonly used for semiconductor processing, which includes multiple processes such as physical vapor deposition (PVD), atomic layer deposition (ALD), and various kinds of chemical vapor deposition (CVD) (e.g., metal-organic chemical vapor deposition (MOCVD), atmospheric-pressure CVD (APCVD), low-pressure CVD (LPCVD), ultra-high-vacuum CVD (UHVCVD)). Each process corresponds to a chamber in the multi-chamber semiconductor processing system, and each chamber may have a different target temperature. If the actual temperature deviates from the target temperature, the grain size of the film formed may deviate from the target grain size. In addition, the properties of the film formed may be degraded.
Transfer robots are typically used in a multi-chamber semiconductor processing system to transfer the wafer from one chamber to another according to the process log. In some examples, one transfer robot is used. In other examples, two or more transfer robots are used. When the wafer is transferred by the transfer robot from a first chamber (having a first target temperature) to a second chamber (having a second target temperature higher than the first target temperature), the process to be conducted in the second chamber cannot begin until the temperature of the wafer ramps up precisely to the second target temperature. As a result, there is some delay time due to the temperature difference in different chambers. The delay time that may exist every time the wafer is transferred to a new chamber can collectively result in a loss in productivity of the multi-chamber semiconductor processing system. The loss in productivity becomes a more significant issue in situations like a global semiconductor shortage.
On the other hand, if the process to be conducted in the second chamber starts prematurely (i.e., before the temperature of the wafer reaches the second target temperature), the grain size of the film formed may deviate, and the properties of the film formed may be degraded, as explained above.
In accordance with some aspects of the disclosure, a multi-chamber semiconductor processing system and the operation thereof are provided. The multi-chamber semiconductor processing system includes multiple chambers, a transfer robot located in a transfer chamber, a temperature sensor mounted on the transfer robot, and a temperature adjustment unit mounted on the transfer robot. The transfer robot is configured to transfer the wafer among the chambers. The temperature sensor is configured to detect a transfer robot temperature. The temperature adjustment unit is configured to adjust the transfer robot temperature.
The temperature adjustment unit begins to adjust the transfer robot temperature 292 when the wafer is still going through a process in a first chamber, and the target temperature is the target temperature of a second chamber. When the wafer exits the first chamber, the temperature of the wafer begins to change (i.e., increase or decrease) as the transfer robot temperature changes toward the target temperature of the second chamber due to thermal conduction (because the wafer is placed on and in contact with the transfer robot). Therefore, by the time the transfer robot transfers the wafer to the second chamber, the transfer robot temperature and, therefore, the temperature of the wafer has reached the target temperature of the second chamber. Accordingly, the delay time due to the temperature difference in different chambers can be significantly reduced or completely avoided, thereby enhancing the productivity of the multi-chamber semiconductor processing system.
The multi-chamber semiconductor processing system 100 includes, among other things, a main frame 206, one or more load locks 204, multiple chambers 202a, 202b, 202c, and 202d (collectively, 202), wafer container loaders 234, wafer containers 246, a loading house 228, a control system 248. The main frame 206 is located at the center, and the one or more load locks 204 and the multiple chambers 202 are laterally spaced around and abutting the main frame 206. It should be understood that although two load locks 204 and four chambers 202 are illustrated in
The wafer container loaders 234 are configured to support wafer containers (sometimes referred to as “pods”) 246. The wafer containers 246 can each accommodate a batch of wafers 102. In one embodiment, the wafer containers 246 are standard mechanical interface (SMIF) pods. In another embodiment, the wafer containers are front opening unified pods (FOUPs). Wafer containers 246 and the wafers 102 therein can be transported among various semiconductor processing systems.
The loading housing 228 is located between the wafer container loaders 234 and the load locks 204. In the example shown in
The loading housing 228 defines a loading area 230 accommodating a loading robot 232 configured to transfer wafers 102 between the wafer container loaders 234 and the load locks 204. In the example shown in
Each of the load locks 204 are arranged in a load lock housing 212, abutting and mounted to a facet of the main frame 206. Each of the load locks 204 includes a corresponding load lock chamber configured to pass wafers 102 between environments on opposing sides of the load locks 204, while maintaining isolation between the environments. In some embodiments, the load lock chambers are individually sized to accommodate the same number of substrates as the chambers 202a-202d.
The main frame 206 includes a transfer chamber 216 central to the chambers 202a-202d and the load locks 204. The transfer chamber 216 accommodates a transfer robot 218 configured to transfer the wafer 102 among the chambers 202a-202d and the load locks 204, so as to facilitate loading and unloading of the wafer 102. During loading of the wafer 102, the wafer 102 is transferred from the load locks 204 to one or more of the chambers 202a-202d in a predetermined order according to the process log 192. Further, during unloading of the wafer 102, the wafer 102 is transferred from one of the chambers 202a-202d to the load locks 204. Although not shown in
In the example shown in
The control system 248 is electrically coupled with the chambers 202a-202d, the load locks 204, the loading robot 232, and the transfer robot 218. The control system 248 is configured to control chambers 202a-202d, the load locks 204, the loading robot 232, and the transfer robot 218.
Referring back to
Referring back to
As will be explained in detail below with reference to
The processing unit 256 is configured to execute codes or instructions stored in the memory 254 to cause the control system 248 to perform various functions disclosed herein. In one embodiment, the processing unit 256 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), a controller, and/or a suitable processing unit.
The memory 254 is configured to store the codes or instructions that are executed by the processing unit 256. In addition, the memory 254 also stores the process log 192. In various implementations, the memory 254 may include one or more of a solid-state memory, a magnetic tape, a removable computer diskette, a random-access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, an optical disk, and/or a suitable memory device.
The transfer module 250 is configured to control the transfer robot 218 and the loading robot 232 to transfer the wafer 102 among the load locks 204 and the chambers 202a-202d. The process module 252 is configured to control various processes carried out in the chambers 202a-202d. In one implementation, the process module 252 obtains the process log 192 stored in the memory 254 and sends control signals to semiconductor processing equipment corresponding to the chambers 202a-202d to operate them according to the process log 192.
The scheduling module 158 is configured to schedule and coordinate various operations of the multi-chamber semiconductor processing system 100. For instance, the scheduling module 158 can coordinate the timing of the process module 252, the temperature adjustment unit 194, and the transfer module 250. The timing coordination among the process module 252, the temperature adjustment unit 194, and the transfer module 250 will be described in detail below with reference to
The chambers 202a-202d can be various chambers corresponding to various semiconductor processing equipment. In one example, the chamber 202a is a degassing chamber, the chamber 202b is a physical vapor deposition (PVD) chamber, the chamber 202c is a chemical vapor deposition (CVD), and the chamber 202d is an atomic layer deposition (ALD) chamber. The degassing chamber is used to remove gaseous and/or liquid substances, such as moisture and oxygen, from the wafer 102 to prevent changes in material characteristics, which may cause deposition failure. It should be noted that the example above is not intended to be limiting, and the techniques disclosed herein are generally applicable to multi-chamber semiconductor processing system where different chambers have different target temperatures.
By way of illustration, a PVD chamber is described in greater detail.
In some embodiments, the PVD system 300 is a magnetron PVD system including a chamber body 312, which encloses a chamber (sometimes also referred to as a “processing region” or a “plasma zone”) 202. A wafer support 320 is disposed within the chamber body 312. The wafer support 320 has a wafer receiving surface 322 that receives and supports the wafer 102 during the PVD process, so that a surface of the wafer 102 is opposite to the front surfaces of 323 the one or more PVD targets 304 that are exposed to the chamber 202. The one or more PVD targets 304 are disposed on a lid 301. The wafer support 320 is electrically conductive and is coupled to ground (GND) so as to define an electrical field between the one or more PVD targets 304 and the wafer 102. In some embodiments, the wafer support 320 is composed of aluminum, stainless steel, or ceramic material. In some embodiments, the wafer support 320 includes an electrostatic chuck that includes a dielectric material.
A shield 330, also referred to as a “dark space shield,” is positioned inside the PVD chamber body 312 and proximate sidewalls 305 of the one or more PVD targets 304 to protect inner surfaces of the chamber body 312 and sidewalls 305 of the one or more PVD targets 304 from unintended deposition. The shield 330 is positioned very close to the target sidewall 305 to minimize re-sputtered material from being deposited thereon. The shield 330 has a plurality of apertures (not shown) defined therethrough for admitting a plasma-forming gas such as argon (Ar) from the exterior of the shield 330 into its interior.
A power supply 340 is electrically coupled to the backing plates 310 of the one or more PVD targets 304 through the lid 301. The backing plates 310 are attached to the target plates 311, which contain different source materials of the PVD targets 304. The power supply 340 is configured to negatively bias the one or more PVD targets 304 with respect to the chamber body 312 to excite a plasma-forming gas, for example, argon (Ar), into a plasma. In some embodiments, the power supply 340 is a direct current (DC) power supply source. In other embodiments, the power supply 340 is a radio frequency (RF) power supply source.
A magnet assembly 350 is disposed above the one or more PVD targets 304. The magnet assembly 350 is configured to project a magnetic field parallel to the front surfaces 323 of the one or more PVD targets 304 to trap electrons, thereby increasing the density of the plasma and increasing the sputtering rate. In some embodiments, the magnet assembly 350 is configured to scan about the back of the one or more PVD targets 304 to improve the uniformity of deposition. In some embodiments, the magnet assembly 350 includes a single magnet disposed above the one or more PVD targets 304. In some embodiments, the magnet assembly 350 includes an array of magnets. In some embodiments and as shown in
A gas source 360 is in fluidic combination with the chamber body 312 via a gas supply pipe 364. The gas source 360 is configured to supply a plasma-forming gas to the chamber 202 via the gas supply pipe 364. The plasm-forming gas is an inert gas and does not react with the materials in the one or more PVD targets 304. In some embodiments, the plasma-forming gas includes argon (Ar), xenon (Xe), neon (Ne), or helium (He), which is capable of energetically impinging upon and sputtering source material (and the dopant in some embodiments) from the one or more PVD targets 304. In some embodiments, the gas source 360 is also configured to supply a reactive gas into the PVD system 300. The reactive gas includes one or more of an oxygen-containing gas, a nitrogen-containing gas, a methane-containing gas, that is capable of reacting with the sputtering source material in the one or more PVD targets 304 to form a layer on the wafer 102.
A vacuum device 370 is in fluidic communication with the PVD system 300 via an exhaust pipe 374. The vacuum device 370 is used to create a vacuum environment in the PVD system 300 during the PVD process. In some embodiments, the PVD system 300 has a pressure in a range from about 1 mTorr to about 10 Torr. The spent process gases and byproducts are exhausted from the PVD system 300 through the exhaust pipe 374.
The temperature adjustment unit 194 is mounted on or attached to the bearing 226. In one embodiment, the temperature adjustment unit 194 includes a heater which can increase the temperature. In another embodiment, the temperature adjustment unit 194 includes a cooling mechanism which can decrease the temperature. In yet another embodiment, the temperature adjustment unit 194 includes both a heater and a cooling mechanism. The temperature adjustment unit 194 increases or decreases the temperature of the bearing 226. Since the bearing 226, the rods 220, and the holding member 224 are all made of metals having good thermal conduction (e.g., aluminum), the transfer robot temperature 292 (i.e., the temperature of the holding member 224) is increased or decreased quickly. As a result, the temperature of the wafer 102 is adjusted accordingly. It should be understood that both the temperature sensor 190r and the temperature adjustment unit 194 are schematic in
In the example shown in
Chamber A has a target temperature TA; chamber B has a target temperature TB; chamber B has a target temperature TC; and chamber B has a target temperature TD. On the other hand, the transfer robot temperature 292 has an initial temperature Tr0, which is typically the environment temperature of the transfer chamber 216 shown in
As explained above, the temperature of the wafer 102 begins to adjust after it has been transferred to a new chamber, in a conventional multi-chamber semiconductor processing system. As a result, there is some delay time due to the temperature difference in different chambers. The delay time that exists every time the wafer is transferred to a new chamber can collectively result in a loss in productivity.
In contrast, and as explained above, the temperature adjustment unit 194 shown in
In one implementation, the temperature adjustment unit 194 adjusts the transfer robot temperature 292 according to the temperature adjustment signal 294 shown in
For instance, the transfer robot temperature 292 begins to change prior to the moment t1, and the adjustment period Δt1 can be determined based on the difference in temperature (i.e., TB−Tr0) and the characteristics of the transfer robot 218 (such as thermal conductivity of the material). As such, some time (i.e., Δt1−tAB) is saved using the techniques disclosed herein because the transition period “AB” (i.e., tAB=t2−t1, as shown in
Likewise, the transfer robot temperature 292 begins to change prior to the moment t3, and the adjustment period Δt2 can be determined based on the difference in temperature (i.e., TC−TB) and the characteristics of the transfer robot 218 (such as thermal conductivity of the material). As such, some time (i.e., Δt2−tBC) is saved using the techniques disclosed herein because the transition period “BC” (i.e., tAB=t4−t3, as shown in
Likewise, the transfer robot temperature 292 begins to change prior to the moment t5, and the adjustment period Δt3 can be determined based on the difference in temperature (i.e., TC−TD) and the characteristics of the transfer robot 218 (such as thermal conductivity of the material). As such, some time (i.e., Δt3−tCD) is saved using the techniques disclosed herein because the transition period “CD” (i.e., tCD=t6−t5, as shown in
Thus, the total time saved (i.e., total reduction in time) can be determined by adding the time saved (i.e., reduction in time) every time the wafer 102 is transferred from one chamber to another chamber having a different target temperature. In the example shown in
Total Reduction in Time=Δt1+Δt2+Δt3−tAB−tBC−tCD.
Accordingly, the delay time due to the temperature difference in different chambers can be significantly reduced or completely avoided, thereby enhancing the productivity of the multi-chamber semiconductor processing system.
It should be understood that, in another embodiment, the transfer robot temperature 292 has an initial temperature Tr0, which is the target temperature of chamber A (i.e., TA shown in
The film 608 is deposited using the multi-chamber semiconductor system 100 shown in
At operation 702, a transfer robot (e.g., the transfer robot 218 shown in
At operation 706, a first temperature sensor (e.g., the temperature sensor 190r shown in
At operation 710, a temperature adjustment unit (e.g., the temperature adjustment unit 194 shown in
At operation 712, the transfer robot transfers the wafer from the first chamber to the second chamber. At operation 714, the second semiconductor process is performed on the wafer in the second chamber.
In accordance with some aspects of the disclosure, a multi-chamber semiconductor processing system is provided. The multi-chamber semiconductor processing system includes: a plurality of chambers, each of the plurality of chambers corresponding to a semiconductor process; a transfer chamber; a transfer robot in the transfer chamber and having a holding member capable of holding a wafer, the transfer robot configured to transfer the wafer among the plurality of chambers; a first temperature sensor mounted on the holding member and configured to detect a transfer robot temperature; and a temperature adjustment unit mounted on the transfer robot and configured to adjust the transfer robot temperature.
In accordance with some aspects of the disclosure, a method for operating a multi-chamber semiconductor processing system is provided. The method includes the following steps: transferring, by a transfer robot, a wafer to a first chamber corresponding to a first semiconductor process; performing, in the first chamber, the first semiconductor process on the wafer; detecting, by a first temperature sensor mounted on the transfer robot, a transfer robot temperature; obtaining a target temperature of a second chamber corresponding to a second semiconductor process; adjusting, by a temperature adjustment unit mounted on the transfer robot, the transfer robot temperature toward the target temperature of the second chamber, wherein the adjusting begins before the first semiconductor process is over; transferring, by the transfer robot, the wafer from the first chamber to the second chamber; and performing, in the second chamber, the second semiconductor process on the wafer.
In accordance with some aspects of the disclosure, a multi-chamber semiconductor processing system is provided. The multi-chamber semiconductor processing system includes: a first chamber corresponding to a first semiconductor process; a second chamber corresponding to a second semiconductor process; a transfer chamber; a transfer robot in the transfer chamber and having a holding member capable of holding a wafer, the transfer robot configured to transfer the wafer between the first chamber and the second chamber; a first temperature sensor mounted on the holding member and configured to detect a temperature of the holding member; a control system configured to generate a temperature adjustment signal based on a target temperature of the second chamber; and a temperature adjustment unit mounted on the transfer robot and configured to adjust the temperature of the holding member according to the temperature adjustment signal, wherein the temperature adjustment unit begins to adjust the temperature of the holding member before the first semiconductor process is over.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
