Multi-layered conductive metal oxide structures and methods for facilitating enhanced performance characteristics of two-terminal memory cells

Information

  • Patent Grant
  • 11289542
  • Patent Number
    11,289,542
  • Date Filed
    Thursday, December 10, 2020
    3 years ago
  • Date Issued
    Tuesday, March 29, 2022
    2 years ago
  • Inventors
  • Original Assignees
    • Hefei Reliance Memory Limited
  • Examiners
    • Bernstein; Allison
    Agents
    • Sheppard Mullin Richter & Hampton LLP
Abstract
A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.
Description
TECHNICAL FIELD

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to enhance cycling endurance, as well as the memory effect, of memory elements, such as implemented in third dimensional memory technology.


BACKGROUND OF THE INVENTION

Conventional memory architectures and technologies, such as those including dynamic random access memory (“DRAM”) cells and Flash memory cells, typically are not well-suited to resolve issues of manufacturing and operating resistance change-based memory cells. The above-described memory architectures, while functional for their specific technologies, fall short of being able to adequately address the issues of cycling endurance of resistance-based memory elements and the degradation due to repeated program-erase cycles. As the structures of conventional memory cells differ from resistance-based memory elements, there are different requirements and approaches to improve the reliability (e.g., cycling endurance) of two-terminal resistance-based memory elements.


In certain conventional approaches to forming resistance-based memory elements, materials providing mobile ions have been formed on multiple layers to form a reservoir of ions used in transport to another material for modifying the resistance of the memory cell. Typically, the multiple layers are formed with identical materials and compositions and cooperate to operate as an ionic conductor and an electronic insulator. While functional, there are certain performance deficiencies associated with this structure.



FIG. 1 depicts sub-optimal performance characteristics associated with a conventional multi-layered structure material operable as an ionic conductor and an electronic insulator. Diagram 100 depicts various magnitudes of current I through a memory cell over a number of program-erase cycles, the memory cell being formed with a material operable as an ionic conductor and an electronic insulator. As shown, the magnitudes of current I alternate between a first magnitude 110 associated with an erasing operation and a second magnitude 112 associated with a programming operation. Over a number of cycles 120, the conventional multi-layered structure has its performance characteristics degrade or other otherwise change. In this case, the current “drifts” lower in magnitudes over number of cycles 120 such that an average current magnitude 102 between magnitudes 110 and 112 decreases over a number of program-erase cycles. Typically, additional circuitry (e.g., sense amp circuitry) and resources are required to accommodate or filter out the current drift, especially when sensing a current representative of a data value, such as a read current generated by application of a read voltage during a read operation to a memory cell, for example. Further, the differences in magnitudes between first magnitudes 110 and second magnitudes 112 decrease during a number of cycles 122, which are subsequent in time to the number of cycles 120. In some cases, the phenomena depicted during number of cycles 120 can arise after, for example 10,000 program-erase cycles.


It would be desirable to provide improved systems, integrated circuits, and methods that minimize one or more of the drawbacks associated with conventional techniques for facilitating improved cycling endurance and memory effects for two-terminal resistance-based memory elements disposed in, for example, cross-point arrays or other memory structures suitable for two-terminal resistance-based memory elements.





BRIEF DESCRIPTION OF THE DRAWINGS

The invention and its various embodiments are more fully appreciated in connection with the following detailed description taken in conjunction with the accompanying drawings, in which:



FIG. 1 depicts sub-optimal performance characteristics associated with a conventional multi-layered structure material operable as an ionic conductor and an electronic insulator;



FIG. 2 depicts an example of a cross-sectional view of a portion of a memory cell including a memory element in accordance with various embodiments;



FIGS. 3A and 3B depict examples of enhanced performance characteristics for a memory cell such as the memory cell configuration depicted in FIG. 2, according to various embodiments;



FIG. 4 depicts an example of a cross-sectional view of a memory element, according to various embodiments;



FIGS. 5A to 5C depict examples of various multi-layer CMO structures having different compositions, according to various embodiments;



FIG. 6 is a diagram depicting an example of formation of an ion obstruction barrier for a two-terminal resistive memory element, according to various embodiments;



FIG. 7A depicts an example of a cross-sectional view for a configuration including a memory cell in accordance with various embodiments;



FIG. 7B depicts an example of a cross-sectional view of another configuration including a memory cell, according to various embodiments;



FIG. 8 depicts an example of components of a memory element and arrayed memory cells, according to various embodiments;



FIG. 9A depicts a cross-sectional view of an example of a memory element oriented at an angle with a substrate, according to various embodiments;



FIG. 9B depicts a cross-sectional view of another example of a memory element oriented at an angle with a substrate, according to various embodiments; and



FIG. 10 depicts a graph of one example of a non-linear I-V characteristic of a discrete two-terminal memory element, according to various embodiments.





Although the above-described drawings depict various examples of the invention, the invention is not limited by the depicted examples. It is to be understood that, in the drawings, like reference numerals designate like structural elements. Also, it is understood that the drawings are not necessarily to scale.


DETAILED DESCRIPTION

Various embodiments or examples may be implemented in numerous ways, including as a system, a process, an apparatus, or a series of program instructions on a computer readable medium such as a computer readable storage medium or a computer network where the program instructions are sent over optical, electronic, or wireless communication links. In general, operations of disclosed processes may be performed in an arbitrary order, unless otherwise provided in the claims.


A detailed description of one or more examples is provided below along with accompanying figures. The detailed description is provided in connection with such examples, but is not limited to any particular example. The scope is limited only by the claims, and numerous alternatives, modifications, and equivalents are encompassed. Numerous specific details are set forth in the following description in order to provide a thorough understanding. These details are provided as examples and the described techniques may be practiced according to the claims without some or all of the accompanying details. For clarity, technical material that is known in the technical fields related to the examples has not been described in detail to avoid unnecessarily obscuring the description.


In some examples, techniques such as those described herein enable emulation of multiple memory types for implementation on a single component such as a wafer, substrate, or die. U.S. patent application Ser. No. 11/095,026, filed Mar. 30, 2005, published as U.S. publication no. 2006/0171200, and entitled “Memory Using Mixed Valence Conductive Oxides,” already incorporated by reference herein, describes non-volatile third dimensional memory elements that may be arranged in a two-terminal, cross-point memory array. New memory structures are possible with the capability of this third dimensional memory array. The technology allows for the emulation of other memory technologies by duplicating the interface signals and protocols, while accessing the third dimensional memory array. The third dimensional memory array may emulate other types of memory (e.g., emulation of DRAM, SRAM, ROM, EEPROM, FLASH, NAND FLASH, and NOR FLASH), providing memory combinations within a single component.


Semiconductor memories and memory material may be fabricated using the described techniques to create a single-layer or multiple-layer three-terminal memory and a single-layer or multiple-layer two-terminal memory, such as a cross-point memory described in U.S. patent application Ser. No. 11/095,026 (incorporated above). Using materials including but not limited to silicon oxide (SiO2), platinum (Pt), titanium nitride (TiN), yttria-stabilized zirconia (YSZ), tungsten (W), conductive metal oxide (CMO), perovskites (e.g., PCMO), and others, a memory may be formed with at least one layer of continuous and memory material (e.g., unetched) sandwiched between two or more electrodes. As part of the formation of a memory cell, for example, a discrete bottom electrode of a memory cell may be formed by etching one or more layers of material. The etched layers may be filled with material and planarized. Above the bottom electrode, one or more layers of memory material may be deposited but not etched (i.e., continuous, unetched layers of memory material). Above the unetched layer(s) of memory material (e.g., the uppermost layer of continuous and unetched memory material), additional layers of material, including a material for a top electrode, and optionally a selection device (“SD”) such as a non-ohmic device (“NOD”), for example, may be deposited and etched to form an implantation mask that, when implanted using ion implantation techniques, creates an insulating layer of conductive metal oxide (“CMO”) (e.g., praseodymium calcium manganese oxide—PCMO) in regions of the CMO that are not covered by the implantation mask. The implantation mask may or may not include the NOD, that is, the NOD may be formed after the layers that comprise the implantation mask. The continuous and unetched layer(s) of CMO may include perovskite-based structures and materials (e.g., PCMO) that, when exposed to argon (Ar), xenon (Xe), titanium (Ti), zirconium (Zr), aluminum (Al), silicon (Si), oxygen (02), silicon and oxygen, or other types of ion implantation techniques and materials, creates regions of material that are electrically insulating and may be referred to as insulating metal oxide (“IMO”). Depending on the type of CMO material selected, its thickness, and processing conditions, the IMO regions can have an amorphous structure that is electrically insulating or a crystalline structure that is electrically insulating. The described techniques enables the formation of memories with small feature sizes and matrices of top and bottom electrodes that are electrically insulated from one another with a greater degree of fabrication reliability and decreased defect or degradation rates. The described fabrication techniques may be varied and are not limited to the examples provided.


In some embodiments, an IMO structure, such as an electrolytic tunnel barrier, and one or more mixed valence conductive oxide structures (e.g., one or more layers of a conductive oxide material) need not operate in a silicon substrate, and, therefore, can be fabricated above circuitry being used for other purposes. That is, the active circuitry portion can be fabricated front-end-of-the-line (“FEOL”) on a substrate (e.g., a Silicon (Si) wafer, Si die, or other semiconductor substrate) and one or more layers of two-terminal cross-point memory arrays that include the non-volatile memory elements can be fabricated back-end-of-the-line (“BEOL”) directly on top of the substrate and electrically coupled with the active circuitry in the FEOL layer using an inter-level interconnect structure, at least a portion of which, is also fabricated FEOL. Manufacturing process for forming FEOL circuitry on a semiconductor wafer followed by subsequent BEOL vertically memory fabrication above the FEOL circuitry is described in U.S. patent application Ser. No. 12/454,322, filed May 15, 2009, and titled “Device Fabrication”, already incorporated herein by reference. Further, a two-terminal memory element can be arranged as a cross-point such that one terminal is electrically coupled with an X-direction line (or an “X-line”) and the other terminal is electrically coupled with a Y-direction line (or a “Y-line”). A third dimensional memory can include multiple memory elements vertically stacked upon one another, sometimes sharing X-direction and Y-direction lines in a layer of memory, and sometimes having isolated lines. When a first write voltage, VW1, is applied across the memory element (e.g., by applying ½ VW1 to the X-direction line and ½ −VW1 to the Y-direction line), the memory element can switch to a low resistive state. When a second write voltage, VW2, is applied across the memory element (e.g., by applying ½ VW2 to the X-direction line and ½ −VW2 to the Y-direction line), the memory element can switch to a high resistive state. Memory elements using electrolytic tunnel barriers and mixed valence conductive oxides can have VW1 opposite in polarity from VW2.



FIG. 2 illustrates a portion of a memory cell including a memory element in accordance with various embodiments. As shown, a portion 200 of a memory cell 201 includes an electrode 209 (e.g., a top electrode), a memory element 205, and an electrode 208 (e.g., a bottom electrode). Memory element 205 includes, but is not limited to, a layer of insulating metal oxide (IMO) 202 formed on multiple layers of conductive metal oxide (CMO), which is depicted as including a layer of CMO Type 2 Material 204 formed on a layer of CMO Type 1 material 206. In this example, the materials in layer of CMO Type 2 Material 204 and layer of CMO Type 1 material 206 have different compositions. Layers of CMO provide mobile oxygen ions 207 for ion transport 225 when various write voltage potentials are applied to electrodes 208 and 209 (e.g., from an external source) and those potentials generate an electric field EW 227 within the layers 202, 204, and 206 during write operations. Here, mobile oxygen ions (e.g., O2) 207 will be denoted as O. Transport 225 of the mobile oxygen ions 207 is in a direction opposite that of the generated electric field EW 227. A magnitude and direction of the electric field EW 227 will depend on the magnitude and polarities of the write voltage potentials applied to electrodes 208 and 209.


Further, layer of CMO Type 2 Material 204 and a portion of layer of CMO Type 1 material 206 include an ion-implanted material. The ion-implanted material is disposed within the crystalline structures of the different compositions of layers 204 and 206 to form an ion obstruction barrier 210. Ion obstruction barrier 210 is configured to inhibit transport or diffusion of other mobile ions 203a and 203b (e.g., a cation or positively charged “+” ion) when a data operations voltage (e.g., a write voltage or a read voltage) is not being applied across electrodes 208 and 209, such that there is no electric field being generated that could cause transport of the other mobile ions 203a and 203b. Note, the other mobile ions 203a and 203b are not the mobile oxygen ions 207 and the mobile oxygen ions 207 are only transported 225 when a write voltage is applied across electrodes (208, 209) and electric field EW 227 is generated. Examples of other mobile ions 203a and 203b include metal ions and other like ions that can diffuse or otherwise transfer between IMO 202 and layers of CMO Type 2 204 and CMO Type 1 206. Note also, that mobile oxygen ions 207 are not transported 225 when a read voltage is applied across electrodes (208, 209). In some embodiments, memory element 205 constitutes a portion 201 of a two-terminal re-writeable non-volatile memory cell.


In view of the foregoing, the structures and/or functionalities of layers of CMO Type 2 204 and CMO Type 1 206 of different compositions can facilitate implementation of ion obstruction barrier 210 (and structures and/or functionalities thereof). In accordance with various embodiments, ion obstruction barrier 210 can provide for enhanced memory effect for re-writeable nonvolatile memory cells, enhanced cycling endurance over a number of write and erase cycles, and/or the stabilization of current magnitudes over the number of write and erase cycles. Examples of enhanced performance characteristics are depicted in FIGS. 3A and 3B.



FIG. 3A is a diagram 300 illustrating current magnitudes generated during program and erase cycles of a memory cell including portion 200 of a memory cell of FIG. 2, according to some embodiments. The current magnitudes range between a first magnitude 310 associated with an erase operation and a second magnitude 312 associated with a programming operation. Over a number of program-erase cycles 320, ion obstruction barrier 210 and/or the layers of CMO Type 2 204 and CMO Type 1 206 of different compositions facilitate stabilization of the current magnitudes, thereby reducing or eliminating current drift. In particular, ion obstruction barrier 210 provides for an average current magnitude 302 between magnitudes 310 and 312 that remains stable and is substantially the same over number of program-erase cycles 320. Stabilized current magnitudes obviate the necessity for additional circuitry (e.g., FEOL sense amp circuitry) and resources to accommodate current drift denoted by a current magnitude 304 that decreases over time as a function of the number of program-erase cycles 320. Also, the difference 301 between magnitudes 310 and 312 remains relatively constant from a first number of cycles 320 to a second number of cycles 322. According to some embodiments, the difference 301 represents a greater amount of current (or current density) available to flow through portion 200 of a memory cell of FIG. 2 over a number of cycles 324 that otherwise might not be available. A greater write or erase current facilitates increases in thickness in a tunnel oxide (not shown), which, in turn, enables miniaturization or scaled down dimensions of a memory cell.


Further, ion obstruction barrier 210 and/or the layers of CMO Type 2 204 and CMO Type 1 206 cooperate to enhance the number of program and erase cycles to extend over a first number of cycles 320 and a second number of cycles 322. For example, first number of cycles 320 can represent 10,000 cycles (10K), whereas a memory cell including portion 200 of the memory cell depicted in FIG. 2 can achieve a number of cycles 324 that is 100,000 cycles (100K). In some cases, number of cycles 324 can range from about 100,000 (100K) to about 1,000,000 cycles (1000K), or greater.



FIG. 3B is a diagram 350 illustrating an example of the on/off ratios for a memory cell including portion 200 of a memory cell of FIG. 2, according to some embodiments. As shown, ion obstruction barrier 210 and/or the layers of CMO Type 2 204 and CMO Type 1 206 of different compositions can establish an on/off ratio 352 of about two orders of magnitude (102). More preferably, an on/off ratio 355 of about three orders of magnitude (103) or greater 357 is desired. The on-off ratio is the ratio between the currents when a memory cell including portion 200 of FIG. 2 is switched on or switched off, thereby establishing a non-volatile memory effect. Another way of stating the on-off ratio is to divide a resistance value of a low resistance state (e.g., a high current erased state) by a resistance value of the highest resistant state (e.g., a low current programmed state). For the same magnitude of read voltage applied across the electrodes (208, 209) the read current will be low when the memory element 205 stores data in the programmed high resistance state and the read current will be higher when the memory element 205 stores data in the erased low resistance state. In that it is easier to measure or sense read current than it is to measure or sense resistance, on/off ratios based on current are typically used because the magnitude of the current is a function of the resistance value stored in the memory element 205. The memory effect of a memory cell including memory element 205 can increase to greater than about 10 to about 100 times than otherwise might be the case when either ion obstruction barrier 210 or the layers of CMO Type 2 204 and CMO 206 of different compositions, or both, are absent. According to some alternate embodiments, on/off ratio 352 can be greater than three orders of magnitude. In view of the above, ion obstruction barrier 210 and/or the layers of CMO Type 2 204 and CMO Type 1 206 of FIG. 2 can cooperate to enhance the reliability of memory cells that include memory element 205.


Returning back to FIG. 2, a grain orientation of the material of an electrode, such as electrode 208 can facilitate the crystalline structures of layer of CMO Type 1 material 206 and/or layer of CMO Type 2 Material 204, according to some embodiments. Electrodes 208 and 209 can be formed from an electrically conductive material, such as a metal (e.g., a noble metal or a combination of noble metals). In a specific example, electrodes 208 and 209 can be formed of platinum (Pt) and may be deposited to a thickness of, for example, from about 50 Angstroms to about 1250 Angstroms. In other embodiments, electrodes 208 and 209 can be formed from a conductive metal oxide (CMO), a doped CMO, or from a metal or metal alloy that has been completely or partially oxidized. Actual thicknesses for electrodes 208 and 209 will be application specific and are not limited to the examples set forth herein.


IMO material 202 can include a material to form a tunnel oxide-based structure or an electrolytic tunnel barrier. In various embodiments, the IMO 202 can include but is not limited to a material for implementing a tunnel barrier layer is also an electrolyte that is permeable to the mobile oxygen ions 207 at voltages for write operations. Suitable materials for IMO 202 include but are not limited to one or more of the following: high-k dielectric materials, rare earth oxides, rare earth metal oxides, yttria-stabilized zirconium (YSZ), zirconia (ZrOx), zirconium oxygen nitride (ZrOxNy), yttrium oxide (YOx), erbium oxide (ErOx), gadolinium oxide (GdOx), lanthanum aluminum oxide (LaAlOx), hafnium oxide (HfOx), aluminum oxide (AlOx), silicon oxide (SiOx), cerium oxide (CeOx), gadolinium doped cerium oxide (CeOx), titanium oxide (TiOx), tantalum oxide (TaOx), and equivalent materials. IMO material 202 can have a thickness of approximately 50 Angstroms or less. Actual IMO thickness will be application specific and can be a function of the material selected and voltage magnitudes chosen for data operations to memory cells (e.g., read voltages, write voltages, program and erase voltages) that facilitate electron tunneling.


CMO Type 1 material 206 and CMO Type 2 material 204 can include different compositions of conductive metal oxide (CMO) or other perovskite material that typically exhibits memory characteristics. CMOs can be formed from a variety of perovskite materials and may include a mixed valence conductive oxide having substantially mixed crystalline or polycrystalline perovskite structure. Perovskite materials, such as CMO, may include two or more metals being selected from a group of transition metals, alkaline earth metals and rare earth metals. Examples of other perovskite materials may include, but are not limited to, manganites, titanates (e.g., strontium titanate STO, reduced STO), zirconates (SZO:Cr, CNO:Cr, TaO:Cr), LSCO, and high Tc superconductors (e.g., YBCO). Other examples of perovskites include but are not limited to PrCaMnOx (PCMO), LaNiOx (LNO), SrRuOx (SRO), LaSrCrOx (LSCrO), LaCaMnOx (LCMO), LaSrCaMnOx (LSCMO), LaSrMnOx (LSMO), LaSrCoOx (LSCoO), and LaSrFeOx (LSFeO), where x is nominally 3 for perovskites (e.g., x≤3 for perovskites) or the one or more CMO layers can be a conductive binary metal oxide structure comprised of a conductive binary metal oxide having the form AXOY, where A represents a metal and O represents oxygen. The conductive binary oxide material may optionally be doped (e.g., with niobium Nb, fluorine F, and/or nitrogen N) to obtain the desired conductive properties for a CMO. Other suitable CMO materials are described in U.S. patent application Ser. No. 12/653,836, filed Dec. 18, 2009, and published as U.S. publication no. 2010/0157658, and titled “Conductive Metal Oxide Structures In Non-Volatile Re-Writable Memory Devices”, already incorporated herein by reference. Layers of CMO Type 1 material 206 and CMO Type 2 material 204 can include two or more layers of CMO materials, at least two of which comprise CMO material of different compositions. Regardless, a CMO layer adjacent to and in contact with IMO layer 202 is thinner than other CMO layers. For example, layer of CMO Type 2 material 204, which is adjacent layer of IMO 202, can be formed to have a thickness between about 10% and about 20% of the thickness of CMO Type 1 material 206, according to some embodiments.


According to various embodiments, memory element 205 is a resistive memory element configured to maintain a resistive state representative of a data stored therein. Stored data is retained in the absence of electrical power (i.e., is non-volatile). As used herein, the term “discrete memory element” can refer, at least in some examples, to a memory cell having a structure that includes no more than memory element 205, and electrodes 208 and 209. For example, a discrete memory element can be a gateless two-terminal device. Examples of a non-discrete memory cell and/or memory element include but are not limited to one or more transistors or diodes configured to implement a selection device (SD) such as a non-ohmic device (NOD) or the like. Typical variations include 1T1R, 2T1R, 1D1R, and 2D1R devices where one (1T) or two (2T) transistors or one (1D) or two (2D) diodes are included in the memory cell and electrically coupled with the memory element.


Memory element 205 can as a discrete memory element constitute a memory cell, according to at least some embodiments. In some examples, a programmed state is a high resistance state (e.g., a logic “0”), and an erased state is a low resistance state (e.g., a logic “1”), thereby establishing a magnitude of an access current that is relatively lower for the programmed state and is relatively higher for the erased state. When only two resistive states are stored, the memory cell can be referred to as a single level cell (SLC). A range of resistive states (e.g., two-bits as “00”, “01”, “10”, or “11”) can represent more than two memory states (i.e., multiple bits per memory cell can be stored as a multi-level cell—MLC).


Note that in alternate embodiments, other materials and layers can be disposed between those structures shown in FIG. 2. While the term “bottom electrode” can refer to an electrode that is formed closer to a substrate (not shown) than other electrodes, the description of structures and techniques relating to a bottom electrode can apply to a top electrode.



FIG. 4 illustrates a memory element in accordance with some embodiments. As shown, a memory element 400 includes, but is not limited to, including a layer of insulating metal oxide (IMO) 402 formed on multiple layers of conductive metal oxide (CMO), which is depicted as including a layer of CMO Type 2 Material 404 formed on a layer of CMO Type 1 material 406. Memory element 400 is formed on electrode 408. In this example, the materials in layer of CMO Type 2 Material 404 and layer of CMO Type 1 material 406 have different compositions. At least one of layer of CMO Type 1 material 406 and layer of CMO Type 2 Material 404 can include an atomic layer deposited (ALD) layer of material or a plasma enhanced atomic layer deposited (PEALD) layer of material. Here, deposition of one or more of the CMO layers may occur in whole or in part using ALD or PEALD. In other embodiments, one or more of the CMO layers may be deposited in whole or in part using a nano-deposition process. Note that the layers of CMO provide mobile oxygen ions 407 for ion transport when various electric fields are applied across electrodes 408 and 409 (e.g., from an external source as described in regard to FIG. 2). Further, layer of CMO Type 2 Material 404 and a portion of layer of CMO Type 1 material 406 include an ion-implanted material. The ion-implanted material is disposed within the crystalline structures of the different compositions of layers 404 and 406 to form an ion obstruction barrier.


CMO Type 1 material 406 can be formed from relatively large-sized grains in relatively crystalline structures, whereas CMO Type 2 material 404 can be formed from relatively fine-sized grains in relatively irregular crystalline structures. According to various embodiments, layer of CMO Type 1 material 406 is formed with grains 440b having an orientation 414 and a grain size 442. CMO Type 2 material 404 is deposited as a layer in which grains 440a adopt similar grain orientations 414 and grain dimensions or sizes 442 from layer of CMO Type 1 material 406 (e.g., grain size and grain orientation are replicated or mimicked in CMO Type 2 material 404). Here, replication of the grain size and/or grain orientation in CMO Type 2 material 404 may be identical to or substantially identical to the grain size and/or grain orientation in CMO Type 1 material 406. In some embodiments, CMO Type 2 material 404 may be formed first followed by CMO Type 1 material 406 being formed on layer 404. The replication of the grain size and/or grain orientation in CMO Type 1 material 406 may be identical to or substantially identical to the grain size and/or grain orientation in CMO Type 2 material 404 (see FIG. 9B) upon which layer 406 is formed. Therefore, replication is from layer 404 to layer 406. According to some embodiments, layer of CMO Type 1 material 406 is formed to have a thickness 420 from about 50 to about 250 Angstroms, and layer of CMO Type 2 material 404 is formed to have a thickness 422 from about 5 to about 25 Angstroms. As another example, layer of CMO Type 2 material 404 can be formed to have a thickness 422 from about 10 to about 20 Angstroms. IMO 402 has a thickness 432 that is approximately 50 Angstroms or less. For example, thickness 432 can be 27 Angstroms. Actual thicknesses for 420 and 422 will be application specific and are not limited to the examples set forth herein. Although IMO 402 is depicted not connected with CMO Type 2 material 404 for purposes of illustration, in actuality an upper surface 440t and a bottom surface 402b will be in direct contact with each other.


Although only one layer of IMO material 402 is depicted, the present invention is not limited to a single layer of IMO and additional IMO layers may be formed in contact with one another and having a combined thickness that is approximately 50 Angstroms or less. A memory element including multiple IMO layers (i.e., at least two IMO layers) their composition, and formation is described in U.S. patent application Ser. No. 13/250,772, filed Sep. 30, 2011, and titled “Memory Device Using Multiple Tunnel Oxide Layers”, already incorporated herein by reference.



FIGS. 5A to 5C illustrate various multi-layer CMO structures having different compositions, according to various embodiments. Layers of CMO Type 1 material 506 and CMO Type 2 material 504 include different compositions, such as different elements, different stoichiometries, and different concentrations of oxygen ions. FIG. 5A depicts a dual-layers CMO structure 500 whereby layers of CMO Type 1 material 506 and CMO Type 2 material 504 have different compositions due to implementations of different elements (e.g., Element 1 and Element 2). FIG. 5B depicts a dual-layers CMO structure 520 whereby layers of CMO Type 1 material 506 and CMO Type 2 material 504 have different compositions due to implementations of different stoichiometries (e.g., Stoichiometry 1 and Stoichiometry 2), whereas the compositions have identical elements. FIG. 5C depicts a dual-layers CMO structure 540 whereby layers of CMO Type 1 material 506 and CMO Type 2 material 504 have different compositions due to implementations of different concentrations or diffusion rates of mobile oxygen ions (e.g., O concentration 1 and O+ concentration 2), whereas the compositions have identical elements and identical stoichiometries.



FIG. 6 is a diagram 600 depicting formation of an ion obstruction barrier for a two-terminal resistive memory element, according to various embodiments. While not shown, an electrode can be formed upon which a layer of CMO Type 1 material 606 is formed. Layer of CMO Type 1 material 606 can serve as a reservoir for mobile oxygen ions 607. Layer of CMO Type 2 material 604 can be formed to have similar crystalline structures, including similar orientations and/or dimensions to layer of CMO Type 1 material 606. Next, a mask 609 can optionally be used to expose portions of layer of CMO Type 2 material 604 to the environs. One or more elements 601 can be implanted via ion implantation techniques at an implantation depth D through layer of CMO Type 2 material 604 to reach a portion of layer of CMO Type 1 material 606 to form an “active region” as ion obstruction barrier 610. Examples of elements 601 include argon and other suitable elements. Ion obstruction barrier 610 is configured to inhibit transport or diffusion of other mobile ions (not shown) between layer of CMO Type 1 material 606 and a layer of insulating metal oxide (IMO), which is not shown. The term active region, according to some embodiments, can refer to an ion obstruction barrier. Other mobile ions may refer to ions other than the mobile oxygen ions 607, such as metal ions, for example.



FIG. 7A illustrates a configuration including a memory cell in accordance with various embodiments. In configuration 700, a memory cell 701 includes a top electrode 702, a memory element 704, and a bottom electrode 706, which can be formed on an optional support layer 708. Support layer 708 can influence the structure and/or functionality of IMO material 718. In some embodiments, support layer 708 is configured to facilitate formation of IMO material 718 with a uniform thickness or a substantially uniform thickness. Support layer 708 can serve as a “template” (e.g., a growth template) to promote the formation of bottom electrode 706 in a manner that propagates the smoothness of a substantially planar upper surface 708t of support layer 708 to an upper surface 706t of bottom electrode 706, thereby providing for a smooth surface or a substantially smooth upper surface 706t of bottom electrode 706 to establish a relatively smooth interface between CMO 2 Material 720b and IMO material 718, or other layers of the memory element 704. Memory cell 701 also includes portions of array line 722 and array line 724 as terminals. Array line 722 and array line 724 may be the conductive array lines of a cross-point array with memory cell 701 positioned between a cross-point of its respective pair of conductive array lines (722, 724) and electrically in series with its respective pair of conductive array lines. In configuration 700, support layer 708 is made from an electrically conductive material such that a current I can flow thorough the memory cell 701 and memory element 704 during data operations (e.g., a read current) on the memory element 704 when appropriate voltage potentials (e.g., write voltages or read voltages) are applied to nodes 728 and 730. As such, memory cell 701 and memory element 704 can be two-terminal memory structures. Memory element 704 is shown to include, but is not limited to, structures 710a and 710b. Memory element structure 710a includes a first substructure including IMO material 718, upon which a second substructure including multiple layers of CMO materials 720a and 720b is formed. Memory element structure 710b includes a first substructure including multiple layers of CMO materials 720a and 720b, upon which a second substructure including IMO material 718 is formed. Memory element 704 can include different and/or additional structures. Multiple layers of CMO materials 720a and 720b in substructures 710a and 710b include ion obstruction barriers (not shown) as described above.



FIG. 7B illustrates another configuration including a memory cell in accordance with various embodiments. In configuration 750, a memory cell 701 includes a top electrode 702, a memory element 704, and a bottom electrode 706, a conductive structure 754 (e.g., an array line) which can be formed on an optional support layer 758. Support layer 758 can influence the structure and/or functionality of IMO material 718. In some embodiments, support layer 758 is configured to facilitate formation of IMO material 718 with a uniform thickness or a substantially uniform thickness. Support layer 758 can serve as a “template” (e.g., a growth template) to promote the formation of conductive structure 754 and subsequent layers formed above the conductive structure 754 in a manner that propagates the smoothness of a substantially planar upper surface 758t of support layer 708 to upper surfaces 754t and 706t of the conductive structure 754 and bottom electrode 706, respectively, thereby providing for a smooth surface or a substantially smooth upper surface 706t of bottom electrode 706 to establish a relatively smooth interface between CMO 2 Material 720b and IMO material 718, or other layers of memory element 704. Memory cell 701 also includes portions of array line 722 and array line 724 as terminals. Array line 722 and array line 724 may be the conductive array lines of a cross-point array with memory cell 701 positioned between a cross-point of its respective pair of conductive array lines (722, 724) and electrically in series with its respective pair of conductive array lines. In configuration 700, support layer 758 is made from an electrically non-conductive material. Here, a current I can flow thorough the memory cell 701 and memory element 704 during data operations (e.g., a read current) on the memory element 704 when appropriate voltage potentials (e.g., write voltages or read voltages) are applied to nodes 760 and 762. Unlike, configuration 700 of FIG. 7A, current I does not flow through support layer 758 because it is electrically non-conductive. As such, memory cell 701 and memory element 704 can be two-terminal memory structures. Memory element 704 is shown to include, but is not limited to, structures 710a and 710b. Memory element structure 710a includes a first substructure including IMO material 718, upon which a second substructure including multiple layers of CMO materials 720a and 720b is formed. Memory element structure 710b includes a first substructure including multiple layers of CMO materials 720a and 720b, upon which a second substructure including IMO material 718 is formed. Memory element 704 can include different and/or additional structures. Multiple layers of CMO materials 720a and 720b in substructures 710a and 710b include ion obstruction barriers (not shown) as described above.



FIG. 8 depicts an example of arrayed memory cells according to various embodiments. In this example, a memory cell 800 includes a memory element 802, which, in turn, includes dual-layered CMO material 870 including different compositions and IMO material 880. Memory cell 800 further includes two terminals 854 and 856. Terminals 854 and 856 can be electrically coupled with or can be formed as electrodes 812 and 816. The electrodes (812, 816) can be made from an electrically conductive material including but not limited to, platinum (Pt), gold (Au), silver (Ag), iridium (Ir), iridium oxide (IrOx), ruthenium (Ru), palladium (Pd), aluminum (Al), alloys of those materials, combinations of those materials, and the like. Optionally, memory cell 800 can include a support layer 818, upon which electrode 816, or some other layer is formed. As described above in regards to FIGS. 7A and 7B, the support layer 818 may or may not be electrically conductive.


In at least some embodiments, memory cell 800 can include optionally a selection device (SD) (e.g., a NOD) 814, which, in turn, can be formed on the memory element 802 (e.g., either above or below memory element 802). SD 814 can be a “metal-insulator-metal” (MIM) type structure that includes one or more layers of electronically insulating material that are in contact with one another and sandwiched between metal layers (e.g., electrodes), or SD 814 can be a non-linear device (e.g., one or more diodes or one or more transistors). U.S. Pat. No. 7,995,371, issued on Aug. 9, 2011, and titled “Threshold Device For A Memory Array and U.S. Pat. No. 7,884,349, issued on Feb. 8, 2011, and titled “Selection Device for Re-Writable Memory”, both of which are already incorporated herein by reference. Memory cell 800 can be formed between conductive array lines, such as array lines 892 and 894. Thus, memory cell 800 can be formed in an array with other memory cells, and the array can be a cross-point array 899 with groups of conductive array lines 892 and 894. For example, array line 892a can be electrically coupled with the electrode 812 of the memory cells 800 and/or may be in contact with a surface of the electrode 812. Array line 894a can be electrically coupled via support layer 818 with the electrode 816 of the memory cells 800 and/or may be in contact via support layer 818 with a surface of electrode 816.



FIG. 9A depicts an example of a memory element oriented at an angle with a substrate, according to various embodiments. Diagram 900 depicts a memory element 903 including a layer of insulating metal oxide (IMO) 902 formed on multiple layers of conductive metal oxide (CMO), which is depicted as including a layer of CMO Type 2 Material 904 formed on a layer of CMO Type 1 material 906. In this example, the materials in layer of CMO Type 2 Material 904 and layer of CMO Type 1 material 906 have different compositions. Layer of CMO Type 1 material 906 is formed on electrode 908. Further, multiple layers of CMO Type 1 material 906 and CMO Type 2 Material 904 include an ion obstruction barrier 910. In this example, memory element 903 is formed in a trench 901 with surfaces of layer of CMO Type 2 Material 904 and layer of IMO 902 being oriented at an angle 920 relative to substrate surface 922 (e.g., a FEOL silicon substrate with active circuitry). Structures (e.g., memory element 903) above an upper surface 922s can be formed BEOL above substrate 922. Other orientations are possible.



FIG. 9B depicts another example of a memory element oriented at an angle with a substrate, according to various embodiments. Diagram 950 depicts a memory element 953 including multiple layers of conductive metal oxide (CMO), which are depicted as including a layer of CMO Type 1 Material 906 formed on a layer of CMO Type 2 material 904, with the layer 904 formed on a layer of insulating metal oxide (IMO) 902. In this example, the materials in layer of CMO Type 2 Material 904 and layer of CMO Type 1 material 906 have different compositions. Layer of insulating metal oxide (IMO) 902 is formed on electrode 908. Further, multiple layers of CMO Type 1 material 906 and CMO Type 2 Material 904 include an ion obstruction barrier 910. In this example, memory element 953 is formed in a trench 951 with surfaces of layer of CMO Type 2 Material 904 and layer of IMO 902 being oriented at an angle 920 relative to substrate surface 922 (e.g., a FEOL silicon substrate with active circuitry). Structures (e.g., memory element 953) above an upper surface 922s can be formed BEOL above substrate 922. Other orientations are possible.


Trenches 901 and 951 of FIGS. 9A and 9B can be implemented in a vertical cross-point array configuration as described in U.S. patent application Ser. No. 13/210,292, Filed Aug. 15, 2011, and titled “Vertical Cross-Point Arrays For Ultra-High-Density Memory Applications”, already incorporated by reference herein. Electrode 908 may be a common electrode shared by at least one other memory element 903 (e.g., on a common word line—WL or common bit line—BL).



FIG. 10 graphically depicts one example of a non-linear I-V characteristic 1000 for a discrete re-writeable non-volatile two-terminal resistive memory element (e.g., 205, 704, 802, 903, 953) having integral selectivity due to its non-linear I-V characteristics and the non-linear I-V characteristic is maintained regardless of the value of the data stored in the memory cell, that is the I-V characteristic of the memory element does not change from non-linear to linear as a function of the resistive state stored in the memory element. Therefore, the non-linear I-V characteristic of the memory element is non-linear for all values of stored data (e.g., resistive states). Voltage V applied across the memory element is plotted on the Y-axis and current density J through the memory element is plotted on the X-axis. Here, current through the memory element is a non-linear function of the applied voltage across the memory element. Accordingly, when voltages for data operations (e.g., read and write voltages) are applied across the memory element, current flow through the memory element does not significantly increase until after a voltage magnitude of about 2.0V (e.g., at ≈0.2 A/cm2) is reached (e.g., a read voltage of about 2.0V across the memory element). An approximate doubling of the voltage magnitude to about 4.0V does not double the current flow and results in a current flow of ≈0.3 A/cm2. The graph depicted is only an example and actual non-linear I-V characteristics will be application dependent and will depend on factors including but not limited to an area of the memory element (e.g., area determines the current density J) and the thin-film materials used in the memory element, just to name a few. The area of the memory element will be application dependent. Here, the non-linear I-V characteristic of the discrete memory element applies to both positive and negative values of applied voltage as depicted by the non-linear I-V curves in the two quadrants of the non-linear I-V characteristic 1000. One advantage of a discrete re-writeable non-volatile two-terminal resistive memory element that has integral selectivity due to a non-linear I-V characteristic is that when the memory element is half-selected (e.g., one-half of the magnitude of a read voltage or a write voltage is applied across the memory element) during a data operation to a selected memory cell(s), the non-linear I-V characteristic is operative as an integral quasi-selection device and current flow through the memory element is reduced compared to a memory cell with a linear I-V characteristic. Therefore, a non-linear I-V characteristic can reduce data disturbs to the value of the resistive state stored in the memory element when the memory element is un-selected or is half-selected. In other embodiments, the memory element has a non-linear I-V characteristic for some values of the resistive state stored in the memory element and a linear I-V characteristic for other values of the resistive state stored in the memory element.


Thin-Film Deposition Techniques


Thin-film layers for the CMO, IMO, electrodes, or other layers for the memory element (ME) and selection device (SD) described herein can be formed using a variety of microelectronics thin-film layer deposition techniques used for nanometer and sub-nanometer device fabrication, examples of which include, but are not limited to, physical vapor deposition (PVD), sputtering, reactive sputtering, co-sputtering, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), nano-deposition, atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), gas cluster ion beam deposition (GCIB), combinations of those techniques, and the like, just to name a few. Further, some or all of the electrode structures can be formed using a plating process, such as electroless plating, for example.


For ALD or PEALD, a thin-film layer, such as an IMO layer and/or a CMO layer can be deposited in whole using ALD or PEALD, or can be deposited in part using ALD or PEALD and some other process, such as PVD or CVD can be used to in conjunction with the ALD or PEALD to deposit the IMO and/or CMO. Therefore, the CMO layer(s) can be deposited in whole or in part using ALD or PEALD and the IMO layers can be deposited in whole or in part using ALD or PEALD. Doping of one or more of the IMO layers and/or doping of the one or more layers of CMO can also be accomplished using the above deposition techniques or combination of those techniques. Doping can occur insitu as part of the deposition process (e.g., doping ceria oxide with gadolinium during the deposition of the ceria oxide).


In some embodiments, some or all of the IMO layers or one or more of the CMO layers are deposited insitu without a chamber break. That is, if there are three layers of IMO, than some or all of those three layers can be deposited insitu in the same deposition chamber. Similarly, if there are multiple layers of CMO, then some or all of those layers can be deposited insitu in the same deposition chamber. Variations in stoichiometry in general or as a function of layer thickness can also be accomplished using the above deposition techniques and the deposition can be accomplished insitu.


The various embodiments of the invention can be implemented in numerous ways, including as a system, a process, an apparatus, or a series of program instructions on a computer readable medium such as a computer readable storage medium or a computer network where the program instructions are sent over optical or electronic communication links. In general, the steps of disclosed processes can be performed in an arbitrary order, unless otherwise provided in the claims.


The foregoing description, for purposes of explanation, uses specific nomenclature to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that specific details are not required in order to practice the invention. In fact, this description should not be read to limit any feature or aspect of the present invention to any embodiment; rather features and aspects of one embodiment can readily be interchanged with other embodiments. Notably, not every benefit described herein need be realized by each embodiment of the present invention; rather any specific embodiment can provide one or more of the advantages discussed above. In the claims, elements and/or operations do not imply any particular order of operation, unless explicitly stated in the claims. It is intended that the following claims and their equivalents define the scope of the invention.

Claims
  • 1. A two-terminal re-writeable non-volatile memory element comprising: a first conductive metal oxide (CMO) layer including mobile oxygen ions;a second CMO layer in contact with the first CMO layer, wherein the first CMO layer has a different concentration of mobile oxygen ions from the second CMO layer; andan insulating metal oxide (IMO) layer in contact with the second CMO layer.
  • 2. The two-terminal re-writeable non-volatile memory element of claim 1, wherein the second CMO layer is configured to cooperate with the first CMO layer to form an ion obstruction barrier positioned in a portion of both the first CMO layer and the second CMO layer and to be operative to inhibit transport of other mobile ions when a voltage for data operations is not being applied across the memory element.
  • 3. The two-terminal re-writeable non-volatile memory element of claim 2, wherein at least portions of the first CMO layer and the second CMO layer comprise an ion-implanted material operative to form the ion obstruction barrier.
  • 4. The two-terminal re-writeable non-volatile memory element of claim 1, wherein the IMO layer is permeable to the mobile oxygen ions when a write voltage is applied across the memory element.
  • 5. The two-terminal re-writeable non-volatile memory element of claim 1, wherein the first CMO layer has a first thickness that is greater than a second thickness of the second CMO layer.
  • 6. The two-terminal re-writeable non-volatile memory element of claim 1, wherein the first CMO layer has a different composition than the second CMO layer.
  • 7. The two-terminal re-writeable non-volatile memory element of claim 6, wherein the first CMO layer and the second CMO layer have substantially similar grain size and grain orientation.
  • 8. The two-terminal re-writeable non-volatile memory element of claim 1, wherein the first CMO layer has different elements than the second CMO layer.
  • 9. The two-terminal re-writeable non-volatile memory element of claim 1, wherein the first CMO layer has substantially similar elements but substantially different stoichiometries than the second CMO layer.
  • 10. The two-terminal re-writeable non-volatile memory element of claim 1, wherein the first CMO layer and the second CMO layer reside in planes at an acute angle with a substrate.
  • 11. A two-terminal re-writeable non-volatile memory cell comprising: a first electrode;a first conductive metal oxide (CMO) layer including mobile oxygen ions in contact with the first electrode;a second CMO layer in contact with the first CMO layer, wherein the first CMO layer has a different composition from the second CMO layer and the first CMO layer and the second CMO layer have substantially similar grain size and grain orientation;an insulating metal oxide (IMO) layer in contact with the second CMO layer; anda second electrode in contact with the IMO layer.
  • 12. The two-terminal re-writeable non-volatile memory cell of claim 11, wherein the second CMO layer is configured to cooperate with the first CMO layer to form an ion obstruction barrier positioned in a portion of both the first CMO layer and the second CMO layer and to be operative to inhibit transport of other mobile ions when a voltage for data operations is not being applied across the first electrode and the second electrode.
  • 13. The two-terminal re-writeable non-volatile memory cell of claim 12, wherein at least portions of the first CMO layer and the second CMO layer comprise an ion-implanted material operative to form the ion obstruction barrier.
  • 14. The two-terminal re-writeable non-volatile memory cell of claim 11, wherein the IMO layer is permeable to the mobile oxygen ions when a write voltage is applied across the first electrode and the second electrode.
  • 15. The two-terminal re-writeable non-volatile memory element of claim 11, wherein the first CMO layer has a first thickness that is greater than a second thickness of the second CMO layer.
  • 16. The two-terminal re-writeable non-volatile memory element of claim 11, wherein the first CMO layer has different elements than the second CMO layer.
  • 17. The two-terminal re-writeable non-volatile memory element of claim 11, wherein the first CMO layer has substantially similar elements but substantially different stoichiometries than the second CMO layer.
  • 18. The two-terminal re-writeable non-volatile memory element of claim 11, wherein the first CMO layer and the second CMO layer reside in planes at an acute angle with a substrate.
  • 19. A two-terminal re-writeable non-volatile memory element comprising: a first conductive metal oxide (CMO) layer including mobile oxygen ions;a second CMO layer in contact with the first CMO layer, wherein the first CMO layer and the second CMO layer reside in planes at an acute angle with a substrate; andan insulating metal oxide (IMO) layer in contact with the second CMO layer.
CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims priority benefit to U.S. patent application Ser. No. 16/705,077, filed Dec. 5, 2019, which is a continuation and claims priority benefit to U.S. patent application Ser. No. 16/219,219, filed Dec. 13, 2018, which is a continuation and claims priority benefit to U.S. patent application Ser. No. 15/811,179, filed Nov. 13, 2017, now U.S. Pat. No. 10,186,553, which is a continuation of and claims priority benefit to U.S. patent application Ser. No. 15/338,857, filed Oct. 31, 2016, now U.S. Pat. No. 9,818,799, which is a continuation of and claims priority benefit to U.S. patent application Ser. No. 14/453,982, filed Aug. 7, 2014, now U.S. Pat. No. 9,484,533, which is a continuation of and claims priority benefit to U.S. patent application Ser. No. 13/250,923, filed Sep. 30, 2011. This application is related to U.S. patent application Ser. No. 11/095,026, filed Mar. 30, 2005, published as U.S. publication no. 2006/0171200, and entitled “Memory Using Mixed Valence Conductive Oxides;” U.S. patent application Ser. No. 12/653,836, filed Dec. 18, 2009, and published as U.S. publication no. 2010/0157658, and titled “Conductive Metal Oxide Structures In Non-Volatile Re-Writable Memory Devices;” U.S. Pat. No. 7,897,951, issued on Mar. 1, 2011, and titled “Continuous Plane Of Thin-Film Materials For A Two-Terminal Cross-Point Memory;” U.S. patent application Ser. No. 12/653,851, filed Dec. 18, 2009, and published as U.S. publication no. 2010/0159641, and titled “Memory Cell Formation Using Ion Implant Isolated Conductive Metal Oxide;” U.S. patent application Ser. No. 13/171,350, filed Jun. 28, 2011, and titled “Multilayer Cross-Point Memory Array Having Reduced Disturb Susceptibility;” U.S. patent application Ser. No. 13/210,342, filed Aug. 15, 2011, and titled “Structures And Methods For Facilitating Enhanced Cycling Endurance Of Memory Accesses To Re-Writable Non-Volatile Two-Terminal Memory Elements;” U.S. Pat. No. 7,995,371, issued on Aug. 9, 2011, and titled “Threshold Device For A Memory Array;” U.S. Pat. No. 7,884,349, issued on Feb. 8, 2011, and titled “Selection Device for Re-Writable Memory;” U.S. patent application Ser. No. 12/454,322, filed May 15, 2009, and titled “Device Fabrication;” U.S. patent application Ser. No. 13/250,772, filed Sep. 30, 2011, and titled “Memory Device Using Multiple Tunnel Oxide Layers;” and U.S. patent application Ser. No. 13/210,292, filed Aug. 15, 2011, and titled “Vertical Cross-Point Arrays For Ultra-High-Density Memory Applications.” All of the above-referenced applications, application publications, and issued patents are hereby incorporated by reference in their entirety for all purposes.

US Referenced Citations (475)
Number Name Date Kind
3886577 Buckley May 1975 A
4519032 Mendell May 1985 A
4830981 Baglee May 1989 A
4843059 Deslandes Jun 1989 A
5160987 Pricer Nov 1992 A
5296716 Ovshinsky Mar 1994 A
5469564 Junya Nov 1995 A
5479317 Ramesh Dec 1995 A
5483482 Kamada et al. Jan 1996 A
5536947 Klersy et al. Jul 1996 A
5572461 Gonzalez Nov 1996 A
5625587 Peng et al. Apr 1997 A
5719416 Yoshimori et al. Feb 1998 A
5739135 Biller et al. Apr 1998 A
5767115 Rosenblum et al. Jun 1998 A
5789320 Andricacos Aug 1998 A
5835396 Zhang Nov 1998 A
5852307 Aoyama Dec 1998 A
5883109 Gregg et al. Mar 1999 A
5894135 Yamamoto Apr 1999 A
5985757 Lee et al. Nov 1999 A
5991193 Gallagher et al. Nov 1999 A
6005810 Wu Dec 1999 A
6026042 Shirley et al. Feb 2000 A
6034882 Johnson et al. Mar 2000 A
6128214 Kuekes et al. Oct 2000 A
6130814 Sun Oct 2000 A
6140672 Arita et al. Oct 2000 A
6185121 O'Neill Feb 2001 B1
6185122 Johnson et al. Feb 2001 B1
6194454 Dow Feb 2001 B1
6204139 Liu et al. Mar 2001 B1
6236076 Arita et al. May 2001 B1
6256220 Kamp Jul 2001 B1
6259644 Tran et al. Jul 2001 B1
6326671 Nagano et al. Dec 2001 B1
6351406 Johnson et al. Feb 2002 B1
6370056 Chen Apr 2002 B1
6385074 Johnson et al. May 2002 B1
6407953 Cleeves Jun 2002 B1
6420215 Knall et al. Jul 2002 B1
6458621 Beck Oct 2002 B1
6459095 Heath et al. Oct 2002 B1
6473332 Ignatiev et al. Oct 2002 B1
6475812 Nickel Nov 2002 B2
6487106 Kozicki Nov 2002 B1
6504753 Scheuerlein et al. Jan 2003 B1
6515888 Johnson et al. Feb 2003 B2
6515904 Moore et al. Feb 2003 B2
6518156 Chen Feb 2003 B1
6522594 Scheuerlein Feb 2003 B1
6525953 Johnson Feb 2003 B1
6528365 Nagano et al. Mar 2003 B2
6531371 Hsu Mar 2003 B2
6534403 Cleeves Mar 2003 B2
6534784 Eliasson Mar 2003 B2
6545891 Tringali et al. Apr 2003 B1
6545898 Scheuerlein Apr 2003 B1
6563185 Moddel May 2003 B2
6569745 Hsu May 2003 B2
6580120 Haspeslagh Jun 2003 B2
6599796 Mei et al. Jul 2003 B2
6631085 Kleveland et al. Oct 2003 B2
6635603 Batlogg Oct 2003 B1
6642539 Ramesh et al. Nov 2003 B2
6656785 Chiang Dec 2003 B2
6657888 Doudin Dec 2003 B1
6693821 Hsu et al. Feb 2004 B2
6731528 Hush May 2004 B2
6741495 Kunikiyo May 2004 B2
6753561 Rinerson Jun 2004 B1
6756649 Moddel Jun 2004 B2
6759249 Zhuang et al. Jul 2004 B2
6762071 Eliasson Jul 2004 B2
6765245 Bansal Jul 2004 B2
6674054 Zhang et al. Aug 2004 B2
6777248 Nabatame et al. Aug 2004 B1
6778420 Parkinson Aug 2004 B2
6781166 Lieber Aug 2004 B2
6784517 Kleveland Aug 2004 B2
6788576 Roizin Sep 2004 B2
6798685 Rinerson Sep 2004 B2
6807088 Tsuchida Oct 2004 B2
6816410 Kleveland et al. Nov 2004 B2
6822903 Scheuerlein et al. Nov 2004 B2
6825058 Hsu Nov 2004 B2
6825489 Kozicki Nov 2004 B2
6831313 Uchiyama Dec 2004 B2
6834013 Fan Dec 2004 B2
6836421 Rinerson et al. Dec 2004 B2
6839269 Iwata et al. Jan 2005 B2
6841833 Hsu Jan 2005 B2
6849564 Hsu Feb 2005 B2
6850455 Rinerson et al. Feb 2005 B2
6855647 Beck Feb 2005 B2
6856536 Rinerson Feb 2005 B2
6859382 Rinerson et al. Feb 2005 B2
6870755 Rinerson Mar 2005 B2
6875651 Hsu Apr 2005 B2
6882553 Nejad et al. Apr 2005 B2
6884812 Glombick et al. Apr 2005 B2
6903361 Gilton Jun 2005 B2
6917539 Rinerson et al. Jul 2005 B2
6927430 Hsu Aug 2005 B2
6937505 Morikawa Aug 2005 B2
6939724 Zhuang Sep 2005 B2
6940113 Hsu et al. Sep 2005 B2
6940744 Rinerson et al. Sep 2005 B2
6965137 Kinney Nov 2005 B2
6970375 Rinerson et al. Nov 2005 B2
6970391 Watanabe et al. Nov 2005 B2
6972238 Hsu Dec 2005 B2
6972427 Roehr Dec 2005 B2
6985378 Kozicki Jan 2006 B2
6990008 Bednorz Jan 2006 B2
6998698 Inoue Feb 2006 B2
6999339 Tuttle et al. Feb 2006 B2
7001846 Hsu Feb 2006 B2
7002197 Perner Feb 2006 B2
7005717 Eisenbeiser Feb 2006 B2
7009909 Rinerson et al. Mar 2006 B2
7020006 Chevallier et al. Mar 2006 B2
7022572 Scheuerlein et al. Apr 2006 B2
7023743 Nejad et al. Apr 2006 B2
7026693 Shimizu Apr 2006 B2
7029924 Hsu Apr 2006 B2
7042066 Hsu May 2006 B2
7046550 Reohr et al. May 2006 B1
7057914 Rinerson et al. Jun 2006 B2
7060586 Li Jun 2006 B2
7067862 Rinerson Jun 2006 B2
7068533 Ferrant Jun 2006 B2
7075817 Rinerson et al. Jul 2006 B2
7079442 Rinerson et al. Jul 2006 B2
7082052 Rinerson Jul 2006 B2
7098043 Zhuang Aug 2006 B2
7105852 Moddel Sep 2006 B2
7106639 Taussig et al. Sep 2006 B2
7141481 Hsu et al. Nov 2006 B2
7148533 Hsu Dec 2006 B2
7149107 Rinerson et al. Dec 2006 B2
7173275 Estes Feb 2007 B2
7177181 Scheuerlein Feb 2007 B1
7180772 Rinerson Feb 2007 B2
7205238 Pan Apr 2007 B2
7212432 Ferrant May 2007 B2
7218984 Bayat May 2007 B1
7227774 Tuttle et al. Jun 2007 B2
7227775 Rinerson et al. Jun 2007 B2
7235454 Kim Jun 2007 B2
7256415 Furukawa et al. Aug 2007 B2
7256429 Hsu et al. Aug 2007 B2
7257458 Markle Aug 2007 B1
7259076 Hsu Aug 2007 B2
7271063 Chung-Zen Sep 2007 B2
7272067 Huang Sep 2007 B1
7283403 Johnson Oct 2007 B2
7292957 Schell Nov 2007 B1
7306988 Avanzino Dec 2007 B1
7319053 Subramanian Jan 2008 B2
7326979 Rinerson et al. Feb 2008 B2
7327600 Norman Feb 2008 B2
7327753 Raissinia et al. Feb 2008 B2
7335575 Hsu Feb 2008 B2
7337149 Blouin Feb 2008 B2
7339811 Nejad et al. Mar 2008 B2
7359226 Schwerin Apr 2008 B2
7372753 Rinerson et al. May 2008 B1
7379364 Siau et al. May 2008 B2
7381981 Aitken Jun 2008 B2
7388276 Estes Jun 2008 B2
7394679 Rinerson et al. Jul 2008 B2
7394680 Toda et al. Jul 2008 B2
7400006 Rinerson Jul 2008 B1
7405960 Cho et al. Jul 2008 B2
7408212 Luan Aug 2008 B1
7411811 Inoue Aug 2008 B2
7417271 Genrikh et al. Aug 2008 B2
7433222 Hosoi Oct 2008 B2
7443711 Stewart et al. Oct 2008 B1
7446010 Li Nov 2008 B2
7457147 Rinerson et al. Nov 2008 B2
7459716 Toda Dec 2008 B2
7460385 Gruber Dec 2008 B2
7462857 Arai Dec 2008 B2
7463546 Fasoli et al. Dec 2008 B2
7464621 Mathis et al. Dec 2008 B2
7498600 Cho et al. Mar 2009 B2
7505344 Scheuerlein Mar 2009 B2
7508695 Sugita Mar 2009 B2
7514271 Gaidis Apr 2009 B2
7526743 Arp Apr 2009 B2
7535035 Baek May 2009 B2
7538338 Rinerson et al. May 2009 B2
7554873 Lee Jun 2009 B2
7558099 Morimoto Jul 2009 B2
7569459 Karg Aug 2009 B2
7573753 Atwood et al. Aug 2009 B2
7577022 Muraoka Aug 2009 B2
7593284 Norman Sep 2009 B2
7606086 Inoue Oct 2009 B2
7608467 Wu et al. Oct 2009 B2
7633108 Li Dec 2009 B2
7633790 Rinerson et al. Dec 2009 B2
7639521 Baek et al. Dec 2009 B2
7643344 Choi Jan 2010 B2
7649788 Norman Jan 2010 B2
7652501 Norman Jan 2010 B2
7652502 Norman Jan 2010 B2
7701791 Rinerson et al. Apr 2010 B2
7706177 Petti Apr 2010 B2
7715244 Norman May 2010 B2
7715250 Norman May 2010 B2
7719876 Chevallier et al. May 2010 B2
7733685 Scheuerlein et al. Jun 2010 B2
7742323 Rinerson et al. Jun 2010 B2
7764160 Kawano Jul 2010 B2
7778061 Robinett Aug 2010 B2
7782650 Bertin et al. Aug 2010 B2
7796416 Ishihara Sep 2010 B2
7796451 Norman Sep 2010 B2
7807517 Kim Oct 2010 B2
7813210 Norman Oct 2010 B2
7818523 Norman Oct 2010 B2
7822913 Norman Oct 2010 B2
7824982 Forbes Nov 2010 B2
7832090 Bornstein Nov 2010 B1
7842991 Cho et al. Nov 2010 B2
7877541 Norman Jan 2011 B2
7884349 Rinerson et al. Feb 2011 B2
7889539 Rinerson et al. Feb 2011 B2
7889571 Norman Feb 2011 B2
7897951 Rinerson Mar 2011 B2
7898841 Chevallier et al. Mar 2011 B2
7902861 Coenen Mar 2011 B2
7902862 How Mar 2011 B2
7902863 Tetzlaff Mar 2011 B1
7902866 Patterson Mar 2011 B1
7902867 Mouttet Mar 2011 B2
7902868 Norman Mar 2011 B2
7902869 Carter Mar 2011 B1
7910913 Choi Mar 2011 B2
7920408 Azuma Apr 2011 B2
7924608 Campbell Apr 2011 B2
7929345 Issaq Apr 2011 B2
7932548 Nagashima Apr 2011 B2
7935953 Ahn May 2011 B2
7955871 Wu et al. Jun 2011 B2
7961494 Scheuerlein Jun 2011 B2
7982504 Robinett Jul 2011 B1
7983065 Samachisa Jul 2011 B2
7985963 Rinerson et al. Jul 2011 B2
7990753 Matsuo Aug 2011 B2
7990754 Azuma Aug 2011 B2
7995371 Rinerson Aug 2011 B2
7999307 Kim Aug 2011 B2
8003511 Rinerson Aug 2011 B2
8031509 Schloss Oct 2011 B2
8040723 Sheu et al. Oct 2011 B2
8044456 Nagashima Oct 2011 B2
8050084 Bae et al. Nov 2011 B2
8062942 Rinerson et al. Nov 2011 B2
8064256 Norman Nov 2011 B2
8124968 Koo Feb 2012 B2
8134866 Bae et al. Mar 2012 B2
8139409 Chevallier et al. Mar 2012 B2
8159858 Siau Apr 2012 B2
8164937 Norman Apr 2012 B2
8164970 Norman Apr 2012 B2
8169053 Kim May 2012 B2
8187936 Alsmeier May 2012 B2
8198618 Mikawa Jun 2012 B2
8207613 Okukawa Jun 2012 B2
8208284 Schloss Jun 2012 B2
8237145 Kamata Aug 2012 B2
8264864 Meyer Sep 2012 B2
8270193 Siau et al. Sep 2012 B2
8317910 Cheung Nov 2012 B2
8363443 Chevallier et al. Jan 2013 B2
8390100 Bornstein Mar 2013 B2
8427868 Chevallier et al. Apr 2013 B2
8431919 Nansei Apr 2013 B2
8482958 Hayakawa et al. Jul 2013 B2
8559209 Siau Oct 2013 B2
8565003 Siau Oct 2013 B2
8638584 Chevallier et al. Jan 2014 B2
8654565 Chevallier et al. Feb 2014 B2
8664633 Park Mar 2014 B2
8675389 Chevallier et al. Mar 2014 B2
8854881 Chevallier et al. Oct 2014 B2
8891276 Siau et al. Nov 2014 B2
8937292 Bateman Jan 2015 B2
9129668 Chevallier et al. Sep 2015 B2
9159408 Chevallier et al. Oct 2015 B2
9384806 Chevallier et al. Jul 2016 B2
9564199 Luan et al. Feb 2017 B2
9570515 Chevallier et al. Feb 2017 B2
9806130 Chevallier et al. Oct 2017 B2
9818799 Wu et al. Nov 2017 B2
9870809 Chevallier et al. Jan 2018 B2
10186553 Wu et al. Jan 2019 B2
10210917 Chevallier et al. Feb 2019 B2
10650870 Chevallier et al. May 2020 B2
20010055838 Walker et al. Dec 2001 A1
20020061604 Sitaram May 2002 A1
20020114112 Nakashio Aug 2002 A1
20020168785 Paz de Araujo Nov 2002 A1
20030003674 Hsu et al. Jan 2003 A1
20030003675 Hsu Jan 2003 A1
20030043633 Forbes Mar 2003 A1
20030132456 Miyai Jul 2003 A1
20030137869 Kozicki Jul 2003 A1
20030148545 Zhuang et al. Aug 2003 A1
20030151959 Tringali Aug 2003 A1
20030156445 Zhuang et al. Aug 2003 A1
20040004237 Fox Jan 2004 A1
20040063274 Hsu Apr 2004 A1
20040100817 Subramanian May 2004 A1
20040109353 Matsuoka Jun 2004 A1
20040114413 Parkinson Jun 2004 A1
20040141369 Noguchi Jul 2004 A1
20040159828 Rinerson Aug 2004 A1
20040159867 Kinney et al. Aug 2004 A1
20040159868 Rinerson Aug 2004 A1
20040159869 Rinerson et al. Aug 2004 A1
20040161888 Rinerson Aug 2004 A1
20040170040 Rinerson et al. Sep 2004 A1
20040180507 Zhang et al. Sep 2004 A1
20050018516 Chevallier et al. Jan 2005 A1
20050040482 Suzuki Feb 2005 A1
20050083760 Subramanian Apr 2005 A1
20050111263 Rinerson May 2005 A1
20050135148 Chevallier Jun 2005 A1
20050151156 Wu Jul 2005 A1
20050174835 Rinerson et al. Aug 2005 A1
20050200785 Jones Sep 2005 A1
20050243595 Rinerson et al. Nov 2005 A1
20050269626 Forbes Dec 2005 A1
20060018149 Rinerson et al. Jan 2006 A1
20060023497 Kawazoe Feb 2006 A1
20060050598 Rinerson et al. Mar 2006 A1
20060054937 Lucovsky et al. Mar 2006 A1
20060125102 Wu Jun 2006 A1
20060131695 Kuekes et al. Jun 2006 A1
20060171200 Rinerson et al. Aug 2006 A1
20060245241 Rinerson et al. Nov 2006 A1
20060245243 Rinerson et al. Nov 2006 A1
20060252733 Jansen Nov 2006 A1
20060273301 Moddel Dec 2006 A1
20070018219 Lim Jan 2007 A1
20070027093 Ogawa et al. Feb 2007 A1
20070032404 Sweet et al. Feb 2007 A1
20070105390 Oh May 2007 A1
20070120110 Estes May 2007 A1
20070132049 Stipe Jun 2007 A1
20070155145 Hong Jul 2007 A1
20070166989 Fresco Jul 2007 A1
20070223282 Sarig Sep 2007 A1
20070252201 Kito Nov 2007 A1
20070253245 Ranjan et al. Nov 2007 A1
20070269683 Chen Nov 2007 A1
20080005459 Norman Jan 2008 A1
20080014750 Nagashima Jan 2008 A1
20080054317 Kim Mar 2008 A1
20080068875 Choi Mar 2008 A1
20080079029 Williams Apr 2008 A1
20080084727 Norman Apr 2008 A1
20080090337 Williams Apr 2008 A1
20080090401 Bratkovski et al. Apr 2008 A1
20080109775 Norman May 2008 A1
20080157127 Bertin et al. Jul 2008 A1
20080173975 Chen Jul 2008 A1
20080175032 Tanaka Jul 2008 A1
20080217600 Gidon Sep 2008 A1
20080237800 Chinthakindi Oct 2008 A1
20080247219 Choi Oct 2008 A1
20080265235 Kamigaichi Oct 2008 A1
20080272363 Mouli Nov 2008 A1
20080273363 Mouli Nov 2008 A1
20080278989 Lee et al. Nov 2008 A1
20080293196 Rinerson et al. Nov 2008 A1
20090016094 Rinerson Jan 2009 A1
20090020744 Mizukami Jan 2009 A1
20090026434 Malhotra Jan 2009 A1
20090026441 Cheung Jan 2009 A1
20090026442 Cheung Jan 2009 A1
20090027976 Rinerson et al. Jan 2009 A1
20090045390 Rinerson et al. Feb 2009 A1
20090101885 Seko Apr 2009 A1
20090122598 Toda May 2009 A1
20090146325 Liu Jun 2009 A1
20090154232 Norman Jun 2009 A1
20090164203 Norman Jun 2009 A1
20090164744 Norman Jun 2009 A1
20090172350 Norman Jul 2009 A1
20090179184 Liu Jul 2009 A1
20090196083 Norman Aug 2009 A1
20090198485 Norman Aug 2009 A1
20090213633 Rinerson Aug 2009 A1
20090225582 Schloss Sep 2009 A1
20090261314 Kim Oct 2009 A1
20090302315 Lee et al. Dec 2009 A1
20090303772 Rinerson Dec 2009 A1
20090303773 Rinerson Dec 2009 A1
20090316465 Jain Dec 2009 A1
20100044666 Baek et al. Feb 2010 A1
20100051896 Park Mar 2010 A1
20100067279 Choi Mar 2010 A1
20100073990 Siau et al. Mar 2010 A1
20100078759 Sekar et al. Apr 2010 A1
20100103724 Kim Apr 2010 A1
20100108975 Sun May 2010 A1
20100110758 Li May 2010 A1
20100110771 Choi May 2010 A1
20100115220 Lee et al. May 2010 A1
20100118589 Carter May 2010 A1
20100134239 Wu et al. Jun 2010 A1
20100155686 Bratkovski et al. Jun 2010 A1
20100155687 Reyes Jun 2010 A1
20100155722 Meyer Jun 2010 A1
20100155723 Bornstein et al. Jun 2010 A1
20100155953 Bornstein Jun 2010 A1
20100157647 Rinerson et al. Jun 2010 A1
20100157657 Rinerson et al. Jun 2010 A1
20100157658 Schloss et al. Jun 2010 A1
20100157670 Chevallier et al. Jun 2010 A1
20100157710 Lambertson Jun 2010 A1
20100159641 Rinerson et al. Jun 2010 A1
20100159688 Rinerson et al. Jun 2010 A1
20100161888 Eggleston Jun 2010 A1
20100161918 Norman Jun 2010 A1
20100187660 Tang Jul 2010 A1
20100195393 Eggleston Aug 2010 A1
20100202188 Rinerson et al. Aug 2010 A1
20100219392 Awaya Sep 2010 A1
20100232200 Shepard Sep 2010 A1
20100232240 Norman Sep 2010 A1
20100259960 Samachisa Oct 2010 A1
20100271885 Scheuerlein et al. Oct 2010 A1
20100278479 Bratkovski et al. Nov 2010 A1
20100290294 Siau Nov 2010 A1
20100323490 Sreenivasan Dec 2010 A1
20110006275 Roelofs et al. Jan 2011 A1
20110017977 Bratkovski et al. Jan 2011 A1
20110024710 Bratkovski et al. Feb 2011 A1
20110024716 Bratkovski et al. Feb 2011 A1
20110059576 Cho et al. Mar 2011 A1
20110063914 Mikajiri Mar 2011 A1
20110149634 Schloss et al. Jun 2011 A1
20110149636 Schloss et al. Jun 2011 A1
20110155990 Cheung Jun 2011 A1
20110182103 Smythe et al. Jul 2011 A1
20110186803 Rinerson et al. Aug 2011 A1
20110188281 Chevallier et al. Aug 2011 A1
20110188282 Chevallier et al. Aug 2011 A1
20110188283 Chevallier et al. Aug 2011 A1
20110188284 Chevallier et al. Aug 2011 A1
20110188289 Chevallier et al. Aug 2011 A1
20110204019 Bornstein Aug 2011 A1
20110220860 Kim Sep 2011 A1
20110266538 Lee Nov 2011 A1
20110297927 Ramaswamy et al. Dec 2011 A1
20120012897 Besser et al. Jan 2012 A1
20120033481 Rinerson et al. Feb 2012 A1
20120064691 Rinerson et al. Mar 2012 A1
20120087174 Rinerson Apr 2012 A1
20120091413 Nguyen Apr 2012 A1
20120147678 Norman Jun 2012 A1
20120211716 Meyer Aug 2012 A1
20120314468 Siau Dec 2012 A1
20130043452 Meyer Feb 2013 A1
20130043455 Bateman Feb 2013 A1
20130082228 Parrillo et al. Apr 2013 A1
20130082232 Wu Apr 2013 A1
20140140122 Siau May 2014 A1
Foreign Referenced Citations (10)
Number Date Country
1376598 Jan 2004 EP
1376598 Jun 2006 EP
2003-092387 Mar 2003 JP
2004-193595 Jul 2004 JP
2005-203733 Jul 2005 JP
0048196 Aug 2000 WO
33079463 Sep 2003 WO
2005117021 May 2004 WO
2006029228 Mar 2006 WO
07047880 Apr 2007 WO
Non-Patent Literature Citations (80)
Entry
U.S. Appl. No. 60/536,115, filed Jan. 12, 2004 in the name of Yong CHEN.
Casperson Brewer, Julie D., et al., “Determination of Energy Barrier Profiles for High-k Dielectric Materials Utilizing Bias-Dependent Internal Photoemission”, Applied Physics Letters, vol. 85, No. 18, Nov. 1, 2004, pp. 11334135.
Casperson, J. D., “Design and Characterization of Layered Tunnel Barriers for Nonvolatile Memory Applications”, PhD Thesis, Caltech, May 17, 2004, pp. 1-143.
Casperson, Julie D , et al., “Materials Issues for Layered Tunnel Barrier Structures”, Journal of Applied Physics, vol. 92, No. 1, Jul. 1, 2002, pp. 261-267.
HP Datasheet, “HP Pavilion dv7-7012nr Entertainment PC,” Product No. B2P31 UA#ABA, Ad Embargo date of Apr. 29, 2012, 2 pages.
Korotkov, Alexander, et al., “Resonant Fowler-Nordheim Tunneling Through Layered Tunnel Barriers and its Possible Applications”, Techn. Dig IDEM 1999, pp. 223-226.
Kurjanowicz, Wlodek, “Evaluating Embedded Non-Volatile Memory for 65nm and Beyond”, DesignCon 2008, Feb. 4, 2008, 23 pages.
Kwok, K. Ng, “Complete Guide to Semiconductor Devices”, 1995, McGraw-Hill Inc., pp. 11-40; pp. 56-62 pp. 84-91; pp. 337-349.
Likharev, Konstantin K., “Layered Tunnel Barriers for Nonvolatile Memory Devices”, Applied Physics Letters, vol. 73, No. 15, Oct. 12, 1998, pp. 2137-2139.
Luryi, S., et al., “Optimum Baritt Structure”, Solid-State Electronics, vol. 25, No. 9, Sep. 1982, pp. 943-945.
Mikolajick, T., et al., “Scaling of Nonvolatile Memories to Nanoscale Feature Sizes”, Materials Science-Poland, vol. 25, No. 1, 2007, pp. 33-43.
PCT International Preliminary Reporton Patentability dated Aug. 28, 2007 in PCT Application No. PCT/US2005/031913, 5 pages.
PCT International Search Report dated Feb. 14, 2006 in PCT Application No. PCT/US2005/031913, 4 pages.
PCT Written Opinion of the International Search Authority dated Sep. 3, 2004 in PCT Application No. PCT/2005/031913, 7 pages.
Peacock, P. W., et al., “Band Offsets and Schottky Barrier Heights of High Dielectric Constant Oxides”, Journal of Applied Physics, vol. 92, No. 8, Oct. 15, 2002, pp. 4712-4721.
Poltavets, Viktor V., “Outline of Research (a few examples)”, <http://www.poltavets.com/>, printed on Nov. 20, 2007, 4 pages.
Subias, Gloria, et al., “Mn Local Structure Effects in Charge-Ordered Mixed-Valence RE1-xCaxMnO3 (RE: La, Tb) Perovskites: A Review of the Experimental Situation”, 2002 J. Phys.: Condens. Matter, vol. 14, pp. 5017-5033, abstract only.
Tans, Sander J., et al., “Room-Temperature Transistor Based on a Single Carbon Nanotube”, Nature, vol. 393, May 7, 1998, pp. 49-52.
Yamauchi Hisao et al., “Control of Mixed Valence Stae to Yield Novel Functions in Double-Perovskite Iron-Copper Oxides”, Science Links Japan, Nippon Sheet Glass Foundation for Materials Science and Engineering Report, vol. 21, 2003, pp. 113-122, abstract only.
Beck, A. et al., “Reproducible switching effect in thin oxide films for memory applications,” Applied Physics Letters, vol. 77, No. 1, Jul. 3, 2000,139-141.
Liu, S.Q., et al., “Electric-pulse-induced reversible resistance change effect in magnetoresistivefilms”, Applied Physics Letters, vol. 76, No. 19, May 8, 2000, 2749-2651.
Liu, S.Q., et al., “A New Concept For Non-Volatile Memory: Electric-Pulse Induced Reversible Resistance Change Effect In Magnetoresistive Films”, Non-Volatile Memory Technology Symposium, Nov. 7, 2001, Space Vacuum Epitaxy Center, University of Houston, Houston TX, pp. 1-7.
Rossel, C. et al., “Electrical current distribution across a metal-insulator-metal structure during bistable switching,” Journal of Applied Physics, vol. 90, No. 6, Sep. 15, 2001, 2892-2898.
Natanabe, Y. et al., “Current-driven insulator-conductor transition and nonvolatile memory in chromium-doped SrTiO3 single crystals,” Applied Physics Letters, vol. 78, No. 23, Jun. 4, 2001, 3738-3740.
Zhuang, W.W. et al., “Novel colossal magnetoresislive thin film nonvolatile resistance random access memory (RRAM)”; IEDM Technical Digest, IEEE, Dec. 8, 2002, pp. 193-196.
A.Baikalov, et al., “Field-driven hysteretic and reversible resistive switch at the Ag-Pr0.7Ca0.3MnO3 interface” Applied Physics Letters, vol. 83, No. 5, Aug. 4, 2003, pp. 957-959.
A. Sawa, et al., “Hysteretic current-volyage characteristics and resisitance switching at a rectifying Ti/Pro.7Cao.3MnO3 interface” Applied Physics Letters, vol. 85, No. 18, Nov. 1, 2004, pp. 4073-4075.
David Oxley, “Memory Effects in Oxide Films” in Oxides and Oxide Films, vol. 6, pp. 251-325 (Chapter 4) (Ashok. K. Vijh ed., Marcel Drekker) (1981).
J.G. Simmons and R.R. Verderber, New Conduction and Reversible Memory Phenomena in Thin Insulating Films/ Proc. Roy. Soc. A., 301 (1967), pp. 77-102.
R.E. Thurstans and D.P. Oxley, “The Electroformed metal-insulator-metal structure: A comprehensive model,” J. Phys. D.: Appl. Phys 35 (2002), Apr. 2, 2002, pp. 802-809.
R. Oligschlaeger, R. Waser, R. Meyer, S. Karthiiuser, R. Dillmann, “Resistive switching and data reliability of epitaxial (Ba,Sr)TiO thin films,” Applied Physics Letters, 88 (2006), 042901.
S. Lai, T. Lowrey, “OUM—A 180 nm nonvolatile memory cell element technology for standalone and embedded applications,” IEEE International Electron Device Meeting, Technical Digest, 803 (2001).
J. Mizusaki J, Y. Yonemura, H. Kamata, K. Ohyama, N. Mori, H. Takai, H. Tagawa M. Dokiya, K. Naraya, T. Sasamoto, H. Inaba, T . Hashimoto, “Electronic conductivity, Seebeck coefficient, defect and electronic structure of nonstoichiometric La1.xSr1MnO3,” Solid State Ionics 132, 167 (2000).
Zhao Y. G.; Rajeswari M.; Srivastava R. C.; Biswas A.; Ogale S. B.; Kang D. J.; Prellier W.; Zhiyun Chen ; Greene R. L.; Venkatesan T., “Effect of oxygen content on the structural, transport, and magnetic properties of La1-deltaMn1-deltaO3 thin films,” Journal of Applied Physics, vol. 86, No. 11, Dec. 1999, pp. 6327-6330.
B.C.H. Steele, A. Heinzel, “Materials for Fuel-Cell-Technologies,” Nature 414, Nov. 2001, pp. 345-352.
A. RelJer, J.M. Thomas, D. A. Jefferson, M. K. Uppal, “Superstructures Formed by the Ordering of Vacancies in a Selective Oxidation Catalyst: Grossly Defective CaMnO3,” Proceedings of the Royal Society of London, vol. 394, No. 1807, Aug. 1984, pp. 223-241.
A. J. Millis, “Cooperative Jahn-Teller effect and electron-phonon coupling in La1-xAxMnO3,” Phys. Rev. B 53, 8434-8441 (1996).
Catapano, Ezetimibe: a selective inhibitor of cholesterol absorption, European Heart Journal Supplements 2001 (3, Supplemental E): E6-E10).
Knopp RH, Drug treatment of lipid disorders. New England J. Med. 1999; 341 (7): 498-511; electronic pp. 1-25.
Li, et al., “Discovery of Potent and Orally Active MTP Inhibitors as Potential Anti-Obesity Agents,” Bioorganic & Medicinal Chemistry Letters, Oxford, GB, vol. 16, No. 11, Jun. 1, 2006, pp. 3039-3042.
Looije, Norbert A., et al., “Disodium Ascorbyl Phytostanyl Phosphates (FM-VP4) Reduces Plasma Cholesterol Concentration, Body Weight and Abdominal Fat Gain Within a Dietary-Induced Obese Mouse Model,” Journal of Pharmacy & Pharmaceutical Sciences: A Publication of the Canadian Society for Pharmaceutical Sciences, vol. 8, No. 3, 2005, pp. 400-408.
Crowley et al., “16.4: 512Mb PROM with 8 Layers of Antifuse/Diode Cells,” 2003 IEEE ISSCC, First Edition, pp. 284-285, 493, Feb. 11, 2003.
EP Office Action dated Aug. 2, 2007 in EP 05794930. 7. 4 pages.
Lai et al., “OUM—A 180 nm Nanvolatile Memory Cell Element Technology For Stand Alone and Embedded Applications,” IEEE International Electron Device Meeting, Technical Digest, vol. 803, 2001.
Lee et al., “Near Edge X-ray Absorption Fine Structure Study of Pr0.65Ca0.35Mn03 Films,” Phys. Stat, sol (a) 196, No. 1, 2003, pp. 70-73.
Millis, A.J., “Cooperative Jahn-Teller Effect and Electron-Phonon Coupling in La-1-xAx.Mn03”, Phys. Rev. B 53 8434-8441 (1996). 8 pages.
Nian, Y.B., et al.,“ Evidence for an Oxygen Diffusion Model for the Electric Pulse Induced Resistance Change Effect in Oxides”, Texas Center for Advanced Materials, University of Houston (2006). 7 pages.
Reller et al., “Superstructres Formed by the Ordering of Vacancies in a Selective Oxidation Catalyst: Grossly Defective CaMn03,” Proceedings of the Royal Society of London, vol. 394, No. 1807, Aug. 1984, pp. 223-241.
Reller, A. et al.,“Superstructures Formed by the Ordering of Vacancies in a Selective Oxidation Catalyst: Grossly Defective CaMn03”, Printed in Great Britain, Department of Physical Chemistry, University of Cambridge, Lensfield Road, Cambridge, CB2 1EP, U.K., vol. 194. Aug. 8, 1984. 1 page.
Stetter. J.R., et al., “Sensors, Chemical Sensors, Electrochemical Sensors, and ECS”, Journal of Electrochemical Society, 150 (2), S11-S16 (2003).
Zhao, Y.G., et al., “Effect of Oxygen Content on the Structural, Transport, and Magnetic Properties of La 1-deltaMn 1-delta03 thin films,” Journal of Applied Physics, vol. 86, No. 11, Dec. 1999, pp. 6327-6330.
Zhuang, W.W. et al., “Novell Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory RRAM)”, IEDM Technical Digest, IEEE, Dec. 8, 2002, pp. 193-196.
Chemical Elements.com, “Periodic Table: Transition Metals”, 1996, downloaded0 Mar. 19, 2017 from http://www.chemicalelements.com/groups/transition.html. 2 pages.
Abelmann et al., “Self-Assembled Three-Dimensional Non-Volatile Memories”, Micromachines, vol. 1, pp. 1-18, Jan. 18, 2010.
Baek et al., “Realization of Vertical Resistive Memory (VRRAM) Using Cost Effective 3D Process”, IDEM 2011, 31, 8.1, pp. 737-740.
Chevallier et al., “A 0.13um 64Mb Multi-layered Conductive Metal-Oxide Memory”, ISSC 2010/Session 14/Non-Volatile Memory/ 14.3, pp. 260-261.
Dong et al., “Si/a-Si Core/Shell Nanowires as Nonvolatile Crossbar Switches”, Nano Letters 2008, vol. 8, No. 29, pp. 361-391.
Jang et al., “Vertical Cell Array Using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density 11 NAND Flash Memory”, 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 192-193.
Katsumata et al., “Pipe-Shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices”, 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 136-137.
Kim et al., “Novel Vertical-Stacked-Array-Transistor (VSAT) for Ultra-High-Density and Cost-Effective NANO Flash Memory Devices and SSD (Solid State Drive),” 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 186-187.
Kim et al., “Multi-Layered Vertical Gate NANO Flash Overcoming Stacking Limit for Terabit Density Storage”, 2009 VLSI Symposium on VLSI Technology Digest of Technical Papers, Jun. 16-18, 2009, pp. 188-189.
Krieger, Ju H., “Principle Operation of 3-D Memory Device based on Piezoacousto Properties of Ferroelectric Films”, In Tech, Dec. 2010, pp. 3-16.
Kwong et al., “Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications”, May 25, 2011, Journal of Nanotechnology, vol. 2012, Article ID 492121, 21 pages.
Lue et al., “A Highly Scalable 8-Layer 30 Vertical-Gate (VG) TFT NANO Flash Using Junction-Free Buried Channel BE-SONOS Device”, 2010 Symposium on VLSI Technology, Jun. 15-17, 2010, pp. 131-132.
Ou et al., “Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Memory”, Doctoral Dissertation, Stanford University, Mar. 2010, pp. 1-119.
Ou et al., “Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory”, IEEE Journal of Solid-State Circuits, vol. 46, No. 9, Sep. 2011.
Strachan et al., “The switching location of a bipolar memristor: chemical, thermal and structural mapping”, Nanotechnology 22 (2011) 254015, pp. 1-6.
Yoon et al., Vertical Cross-point Resistance Change Memory for Ultra-High Density Non-volatile Memory Applications, 2009 Symposium on VLSI Technology Digest of Technical Papers, pp. 26-27.
Zhang et al., “A 3D RRAM Using Stackable 1TXR Memory Cell for High Density Application”, IEEE Xplore, Feb. 5, 2010, pp. 917-920.
Extended European Search Report dated May 25, 2011, issued in related European Application No. 10182254.2 (5 pages).
First Office Action dated Jan. 6, 2014, issued in related Chinese Application No. 201210193421.1, with English machine translation (7 pages).
Notice of Reasons for Refusal dated Feb. 7, 2012, issued in related Japanese Application No. 2007-530487, with English machine translation (6 pages).
Final Notification of Reasons for Refusal dated Jan. 8, 2013, issued in related Japanese Application No. 2007-530487, with English machine translation (6 pages).
PCT International Search Report dated May 23, 2006, issued in related International Application No. PCT/US2005/031913 (3 pages).
PCT Written Opinion dated May 24, 2006, issued in related International Application No. PCT/US2005/031913 (7 pages).
PCT International Preliminary Report on Patentability dated Aug. 28, 2007, issued in related International Application No. PCT/US2005/031913 (5 pages).
Non-Final Office Action dated Mar. 7, 2018, issued in related U.S. Appl. No. 15/811,179 (8 pages).
Non-Final Office Action dated Apr. 5, 2017, issued in related U.S. Appl. No. 15/338,857 (9 pages).
Non-Final Office Action dated Sep. 14, 2015, issued in related U.S. Appl. No. 14/453,982 (8 pages).
Notice of Allowance dated Jul. 5, 2016, issued in related U.S. Appl. No. 14/453,982 (10 pages).
Related Publications (1)
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20210098534 A1 Apr 2021 US
Continuations (6)
Number Date Country
Parent 16705077 Dec 2019 US
Child 17117632 US
Parent 16219219 Dec 2018 US
Child 16705077 US
Parent 15811179 Nov 2017 US
Child 16219219 US
Parent 15338857 Oct 2016 US
Child 15811179 US
Parent 14453982 Aug 2014 US
Child 15338857 US
Parent 13250923 Sep 2011 US
Child 14453982 US