Patent Application
20240194672
Integrated circuit (IC) fabrication usually includes two stages. The first stage is referred to as the front end of line (FEOL). The second stage is referred to as the back end of line (BEOL). In the FEOL, individual components (e.g., transistor, capacitors, resistors, etc.) can be patterned in a wafer. In the BEOL, metal layers, vias, and insulating layers can be formed to get the individual components interconnected. The BEOL usually starts with forming the first metal layer on the wafer. The first metal layer is often called M0. More metal layers can be formed on top of M0, and these metal layers are often called M1, M2, and so on.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
The systems, methods, and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
Patterns of metal lines, insulators, or vias in IC devices are often generated through DSA of block copolymers. Phase separation during the DSA of a block copolymer can produce a DSA pattern that includes lamellar structures of polymers. Taking a block copolymer including polymer A and polymer B for example, the DSA of the block copolymer may form lamellar structures including polymer A and lamellar structures including polymer B. The two types of lamellar structures alternate. The center-to-center distance between two adjacent lamellar structures including the same polymer may define a pitch of the DSA pattern.
However, DSA of a block copolymer is limited to a single pitch pattern. The pitch of the DSA pattern is fixed, e.g., based upon the molecular weight of the block copolymer. Examples of pitches of DSA patterns may include, for example, 33 nanometers (nm), 34 nm, 36 nm, 38 nm, 39 nm, and so on. However, the fabrication of an IC device may require formation of a DSA pattern over an underlayer that has a multi-pitch pattern, meaning the underlayer has at least two different pitches. For instance, the layer may have conductive structures (e.g., contacts, metal lines, etc.) that have different dimensions, such as different lengths. The pitch of DSA pattern cannot match all the pitches of the underlayer.
Conventional fabrication technologies usually ensure that the pitch of DSA pattern matches one of the pitches of the underlayer and therefore, is different from other pitches of the underlayer. Given the multi-pitch pattern in the underlayer, the DSA pattern may be inevitably formed over an undesired area, such as the region that has a different pitch from the pitch of the DSA pattern. In a typical flow using these conventional technologies, tight pitches are patterned via DSA, while the loose pitches (such as wide gate, frame, etc.) are cleared off post-DSA using a separate mask. Additionally, another mask is needed to introduce the content back in the cleared off regions. Thus, the conventional technologies can require at least two new masks to clear off the non-compliant pitch regions and add back patterns within these regions. This would add lots of (e.g., over thirty) additional process steps. Thus, the conventional technologies fail to provide an efficient flow for multi-pitch patterning.
Embodiments of the present disclosure may improve on at least some of the challenges and issues described above by using a one-step flow for multi-pitch patterning. For patterning over an underlayer that includes a tight pitch region and a loose pitch region, the one-step flow in the present disclosure can integrate trench patterns of the loose pitch region within plug patterns of the tight pitch region. The integration may be based on the presence of an oxide structure over the loos pitch region, which can eliminate the use of a new mask and therefore, avoid additional process steps.
In various embodiments of the present disclosure, a block copolymer may be provided to a surface of an underlayer having a multi-pitch pattern. The underlayer may include a tight pitch region and a loose pitch region. The tight pitch region may include one or more first conductive structures. The loose pitch region may include one or more second conductive structures. A second conductive structure has a length greater than a first conductive structure. At least one first lamellar structure and at least one second lamellar structure may be formed over the tight pitch region and at least a portion of the loose pitch region through DSA of the block copolymer. The first lamellar structure includes a polymer in the block copolymer, the second lamellar structure includes another polymer in the block copolymer. The second lamellar structure(s) may be removed, e.g., through selective etch. One or more first lamellar structures (if any) that are over the loose pitch region may be removed, e.g., by using a cut mask. A hard mask is then formed. A first portion of the hard mask (e.g., carbon hard mask) may fill openings that are formed by removing one or more second lamellar structures over the tight pitch region. A second portion of the hard mask may be over the one or more first lamellar structures over the tight pitch region and over the first portion of the hard mask.
After the hard mask is formed, an oxide structure over the loose pitch region may be formed. Further, the hard mask can be removed, and one or more openings formed from removing the hard mask may be filled with a dielectric material, such as a nitride, so that a nitride structure can be formed over the first conductive structure. One or more dielectric materials may be provided to form a dielectric structure that at least partially surrounds the nitride structure. A plug may be placed at least partially over the dielectric structure. Another plug may be placed over the oxide structure. A trench over the tight pitch region and a trench over the loose pitch region can be formed based on the plugs. For instance, areas over the tight pitch region and the loose pitch region that are not covered by the plugs may be etched to form the trenches. The trenches may be filled with a dielectric material, such as a nitride, to form a first structure over the tight pitch region and a second structure over the loose pitch region. At least part of the first structure is over the first conductive structure. At least part of the second structure is over the second conductive structure. The second structure over the loose pitch region may be at least partially surrounded by an oxide, e.g., the portion of the oxide structure that is not removed. The oxide may constitute a guard ring of the second conductive structure.
Compared with conventional technologies that requires two hard masks during the fabrication process, the one-step flow requires one hard mask. Thus, the one-step flow has less additional process steps, such as collateral steps needed to add the second hard mask, collateral steps needed to remove the second hard mask, and so on. Thus, the present disclosure provides a more efficient flow for multi-pitch patterning.
It should be noted that, in some settings, the term “nanoribbon” has been used to describe an elongated semiconductor structure that has a substantially rectangular transverse cross-section (e.g., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term “nanowire” has been used to describe a similar structure but with a substantially circular or square transverse cross-sections. In the following, a single term “nanoribbon” is used to describe an elongated semiconductor structure independent of the shape of the transverse cross-section. Thus, as used herein, the term “nanoribbon” is used to cover elongated semiconductor structures that have substantially rectangular transverse cross-sections (possibly with rounded corners), elongated semiconductor structures that have substantially square transverse cross-sections (possibly with rounded corners), elongated semiconductor structures that have substantially circular or elliptical/oval transverse cross-sections, as well as elongated semiconductor structures that have any polygonal transverse cross-sections. A longitudinal axis of a structure refers to a line (e.g., an imaginary line) that runs down the center of the structure in a direction perpendicular to a transverse cross-section of the structure.
In the following, some descriptions may refer to a particular source or drain (S/D) region or contact being either a source region/contact or a drain region/contact. However, unless specified otherwise, which region/contact of a transistor or diode is considered to be a source region/contact and which region/contact is considered to be a drain region/contact is not important because, as is common in the field of FETs, designations of source and drain are often interchangeable. Therefore, descriptions of some illustrative embodiments of the source and drain regions/contacts provided herein are applicable to embodiments where the designation of source and drain regions/contacts may be reversed.
As used herein, the term “metal layer” may refer to a layer above a substrate that includes electrically conductive interconnect structures for providing electrical connectivity between different IC components. Metal layers described herein may also be referred to as “interconnect layers” to clearly indicate that these layers include electrically conductive interconnect structures which may, but do not have to be, metal.
The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. If used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, while the term “low-k dielectric” refers to a material having a lower k than silicon oxide. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−8% of a target value, e.g., within +/−5% of a target value or within +/−2% of a target value, based on the context of a particular value as described herein or as known in the art. Also, the term “or” refers to an inclusive “or” and not to an exclusive “or.”
The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).
The description may use the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,
In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of one or more multi-pitch patterns fabricated through one or more cross-linkable copolymers as described herein.
Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
Various one or more multi-pitch patterns fabricated through one or more cross-linkable copolymers as described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.
In the embodiments of
The support structure 115 may be any suitable structure, such as a substrate, a die, a wafer, or a chip, based on which the transistors 117 can be built. The support structure 115 may, e.g., be the wafer 2000 of
Although a few examples of materials from which the support structure 115 may be formed are described here, any material that may serve as a foundation upon which an IC may be built falls within the spirit and scope of the present disclosure. In various embodiments, the support structure 115 may include any such substrate, possibly with some layers and/or devices already formed thereon, not specifically shown in the present figures. As used herein, the term “support” does not necessarily mean that it provides mechanical support for the IC devices/structures (e.g., transistors, capacitors, interconnects, and so on) built thereon. For example, some other structure (e.g., a carrier substrate or a package substrate) may provide such mechanical support and the support structure 115 may provide material “support” in that, e.g., the IC devices/structures described herein are build based on the semiconductor materials of the support structure 115. However, in some embodiments, the support structure 115 may provide mechanical support.
A transistor 117 may be a field-effect transistor (FET), such as metal-oxide-semiconductor FET (MOSFET), tunnel FET (TFET), fin-based transistor (e.g., FinFET), nanoribbon-based transistor, nanowire-based transistor, gate-all-around (GAA) transistor, other types of FET, or a combination of both. The transistor 117A includes a semiconductor structure that includes a channel region 130A, a source region 143A, and a drain region 147A. The transistor 117A includes a semiconductor structure that includes a channel region 130B, a source region 143B, and a drain region 147B. The channel regions 130A and 130B are collectively referred to as “channel regions 130” or “channel region 130.” The source regions 143A and 143B are collectively referred to as “source regions 143” or “source region 143.” The drain regions 147A and 147B are collectively referred to as “drain regions 147” or “drain region 147.”
The semiconductor structure of each transistor 117 may be at least partially in the support structure 115. The support structure 115 may include a semiconductor material, from which at least a portion of the semiconductor structure is formed. The semiconductor structure of a transistor 117 (or a portion of the semiconductor structure, e.g., the channel region 130) may be a planar structure or a non-planar structure. A non-planar structure is a three-dimensional structure, such as fin, nanowire, or nanoribbon. A non-planar structure may have a longitudinal axis and a transvers cross-section perpendicular to the longitudinal axis. In some embodiments, a dimension of the non-planar structure along the longitudinal axis may be greater than dimensions along other directions, e.g., directions along axes perpendicular to the longitudinal axis.
Each channel region 130 includes a channel material. The channel material may be composed of semiconductor material systems including, for example, n-type or p-type materials systems. In some embodiments, the channel material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material may include a compound semiconductor with a first sub-lattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material may include a compound semiconductor with a first sub-lattice of at least one element from Group II of the periodic table (e.g., Zn, Cd, Hg), and a second sub-lattice of at least one element of Group IV of the periodic table (e.g., C, Si, Ge, Sn, Pb). In some embodiments, the channel material is an epitaxial semiconductor material deposited using an epitaxial deposition process. The epitaxial semiconductor material may have a polycrystalline structure with a grain size between about 2 nm and 100 nm, including all values and ranges therein.
For some example n-type transistor embodiments (i.e., for the embodiments where the transistor 117 is an NMOS (N-type metal-oxide-semiconductor) transistor or an n-type TFET), the channel material may advantageously include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGa1-xAs fin embodiments, In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In0.7Ga0.3As). In some embodiments with highest mobility, the channel material may be an intrinsic III-V material, i.e., a III-V semiconductor material not intentionally doped with any electrically active impurity. In alternate embodiments, a nominal impurity dopant level may be present within the channel material, for example to further fine-tune a threshold voltage Vt, or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel material 304 may be relatively low, for example below 1015 dopant atoms per cubic centimeter (cm-3), and advantageously below 1013 cm−3. These materials may be amorphous or polycrystalline, e.g., having a crystal grain size between 0.5 nanometers and 100 nanometers.
For some example p-type transistor embodiments (i.e., for the embodiments where the transistor 117 is a PMOS (P-type metal-oxide-semiconductor) transistor or a p-type TFET), the channel material may advantageously be a Group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material may have a Ge content between 0.6 and 0.9, and advantageously may be at least 0.7. In some embodiments with highest mobility, the channel material may be intrinsic III-V (or IV for P-type devices) material and not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the channel material, for example to further set a threshold voltage (Vt), or to provide HALO pocket implants, etc. Even for impurity-doped embodiments however, impurity dopant level within the channel portion is relatively low, for example below 1015 cm−3, and advantageously below 1013 cm−3. These materials may be amorphous or polycrystalline, e.g., having a crystal grain size between 0.5 nanometers and 100 nanometers.
In some embodiments, the channel material may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, aluminum zinc oxide, or tungsten oxide. In general, for a thin-film transistor (TFT), the channel material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, molybdenum disulfide, N- or P-type amorphous or polycrystalline silicon, monocrystalline silicon, germanium, indium arsenide, indium gallium arsenide, indium selenide, indium antimonide, zinc antimonide, antimony selenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, black phosphorus, zinc sulfide, indium sulfide, gallium sulfide, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, a thin-film channel material may be deposited at relatively low temperatures, which allows depositing the channel material within the thermal budgets imposed on back-end fabrication to avoid damaging other components, e.g., front end components such as logic devices.
As noted above, the channel material may include IGZO. IGZO-based devices have several desirable electrical and manufacturing properties. IGZO has high electron mobility compared to other semiconductors, e.g., in the range of 20-50 times than amorphous silicon. Furthermore, amorphous IGZO (a-IGZO) transistors are typically characterized by high band gaps, low-temperature process compatibility, and low fabrication cost relative to other semiconductors.
IGZO can be deposited as a uniform amorphous phase while retaining higher carrier mobility than oxide semiconductors such as zinc oxide. Different formulations of IGZO include different ratios of indium oxide, gallium oxide, and zinc oxide. One particular form of IGZO has the chemical formula InGaO3(ZnO)5. Another example form of IGZO has an indium:gallium:zinc ratio of 1:2:1. In various other examples, IGZO may have a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and/or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO can also contain tertiary dopants such as aluminum or nitrogen.
In each transistor 117, the source region 143 and the drain region 147 are connected to the channel region 130. The source region 143 and the drain region 147 each includes a semiconductor material with dopants. In some embodiments, the source region 143 and the drain region 147 have the same semiconductor material, which may be the same as the channel material of the channel region 130. A semiconductor material of the source region 143 or the drain region 147 may be a Group IV material, a compound of Group IV materials, a Group III/V material, a compound of Group III/V materials, a Group II/VI material, a compound of Group II/VI materials, or other semiconductor materials. Example Group II materials include zinc (Zn), cadmium (Cd), and so on. Example Group III materials include aluminum (Al), boron (B), indium (In), gallium (Ga), and so on. Example Group IV materials include silicon (Si), germanium (Ge), carbon (C), etc. Example Group V materials include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and so on. Example Group VI materials include sulfur (S), selenium (Se), tellurium (Te), oxygen (O), and so on. A compound of Group IV materials can be a binary compound, such as SiC, SiGe, and so on. A compound of Group III/V materials can be a binary, tertiary, or quaternary compound, such as GaN, InN, and so on. A compound of Group II/VI materials can be a binary, tertiary, or quaternary compounds, such as CdSe, CdS, CdTe, ZnO, ZnSe, ZnS, ZnTe, CdZnTe, CZT, HgCdTe, HgZnTe, and so on.
In some embodiments, the dopants in the source region 143 and the drain region 147 are the same type. In other embodiments, the dopants of the source region 143 and the drain region 147 may be different (e.g., opposite) types. In an example, the source region 143 has n-type dopants and the drain region 147 has p-type dopants. In another example, the source region 143 has p-type dopants and the drain region 147 has n-type dopants. Example n-type dopants include Te, S, As, tin (Sn), Si, Ga, Se, S, In, Al, Cd, chlorine (CI), iodine (I), fluorine (F), and so on. Example p-type dopants include beryllium (Be), Zn, magnesium (Mg), Sn, P, Te, lithium (Li), sodium (Na), Ga, Cd, and so on.
In some embodiments, the source region 143 and the drain region 147 may be highly doped, e.g., with dopant concentrations of about 1.1021 cm-3, in order to advantageously form Ohmic contacts with the respective S/D contacts (also sometimes interchangeably referred to as “S/D electrodes”), although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Irrespective of the exact doping levels, the source region 143 and the drain region 147 may be the regions having dopant concentration higher than in other regions, e.g., higher than a dopant concentration in the channel region 130, and, therefore, may be referred to as “highly doped” (HD) regions.
The channel region 130 may include one or more semiconductor materials with doping concentrations significantly smaller than those of the source region 143 and the drain region 147. For example, in some embodiments, the channel material of the channel region 130 may be an intrinsic (e.g., undoped) semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, nominal impurity dopant levels may be present within the channel material, for example to set a threshold voltage Vt, or to provide HALO pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the channel material is still significantly lower than the dopant level in the source region 143 and the drain region 147, for example below 1015 cm−3 or below 1013 cm−3. Depending on the context, the term “S/D terminal” may refer to a S/D region or a S/D contact or electrode of a transistor.
The transistor 117A also includes a source contact 142A over the source region 143A and a drain contact 146A over the drain region 147A. The transistor 117B also includes a source contact 142B over the source region 143B and a drain contact 146B over the drain region 147B. The source contacts 142A and 142B are collectively referred to as “source contacts 142” or “source contact 142.” The drain contacts 146A and 146B are collectively referred to as “drain contacts 146” or “drain contact 146.” The source contacts 142 and the drain contacts 146 are electrically conductive and may be coupled to source and drain terminals for receiving electrical signals. A source contact 142 or the drain contact 146 includes one or more electrically conductive materials, such as metals. Examples of metals in the source contacts 142 and the drain contacts 146 may include, but are not limited to, Ruthenium (Ru), copper (Cu), cobalt (Co), palladium (Pd), platinum (Pt), nickel (Ni), and so on.
Each transistor 117 also includes a gate that is over or wraps around at least a portion of the channel region 130. The gate of the transistor 117A includes a gate contact 135A. The gate of the transistor 117B includes a gate contact 135B. The gate contacts 135A and 135B are collectively referred to as “gate contacts 135” or “gate contact 135.” The gate contact 135A has a smaller length along the X axis than the gate contact 135B. In an example, the length of the gate contact 135A may be about half of the length of the gate contact 135B. In some embodiments, the source contacts 142 or drain contacts 146 may have the same or similar length along the X axis as the gate contact 135A. In other embodiments, the source contacts 142 or drain contacts 146 may have the same or similar length along the X axis as the gate contact 135B. In some embodiments, the source contacts 142 may have different lengths from each other. The drain contacts 146 may have different lengths from each other.
In each transistor 117, the gate contact 135 can be coupled to a gate terminal that controls gate voltages applied on the transistor 117. The gate contact 135 may include one or more gate electrode materials, where the choice of the gate electrode materials may depend on whether the transistor 117 is a p-type transistor or an n-type transistor. For a p-type transistor, gate electrode materials that may be used in different portions of the gate electrode may include, but are not limited to, Ru, Pd, Pt, Co, Ni, and conductive metal oxides (e.g., ruthenium oxide). For an n-type transistor, gate electrode materials that may be used in different portions of the gate electrode, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate contact 135 may include a stack of a plurality of gate electrode materials, where zero or more materials of the stack are workfunction (WF) materials and at least one material of the stack is a fill metal layer. Further materials/layers may be included next to the gate electrode for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer.
The gate of a transistor 117 may also include a gate insulator (not show in
As shown in
The metal lines 185 are insulated from each other by the electrical insulator 125. The electrical insulator 125 includes one or more electrically insulative materials. An electrically insulative material may be a dielectric material, hysteretic material, and so on. Example dielectric material includes oxide (e.g., Si based oxides, metal oxides, etc.), nitride (e.g., Si based nitride, etc.), low-k dielectric, high-k dielectric, and so on. Example hysteretic material include ferroelectric materials, antiferroelectric materials, and so on. The electrical insulator 125 may be referred to as ILD of the BEOL section 120.
The vias 150 can provide a conductive channel between the transistors 117 and the metal layer 180. Each via 150 has an end that is connected to a gate contact 135, source contact 142, or drain contact 146. The other end of the via 150 is connected to a metal line 180. Each via 150 is electrically conductive. A via 150 may include a metal, such as tungsten (W), molybdenum (Mo), ruthenium (Ru), copper (Cu), or other metals. Different vias 150 may include different materials. The vias 150 that are connected to gate contacts may be referred to as VCGs. The vias 150 that are connected to source contacts and drain contacts may be referred to as VCTs. For purpose of illustration,
The vias 150 or metal lines 185 may be formed through patterning over an underlayer that includes the gate contacts 135, source contacts 142, and drain contacts 146. As shown in
In the embodiments of
In some embodiments, the via 150 connected to the gate contact 135A may be formed by forming an opening in the insulative structure 163 and filling the opening with one or more conductive materials. Similarly, the via 150 connected to the gate contact 135B may be formed by forming an opening in the insulative structure 165 and filling the opening with one or more conductive materials. Even though the vias 150 connected to the gate contacts 135 are at least partially surrounded by the insulative structures 163 and 165, respectively and have smaller lengths than the gate contacts 135 along the X axis in
The electrical insulator 170 includes one or more electrically insulative materials. An electrically insulative material may be a dielectric material, hysteretic material, and so on. Example dielectric material includes oxide (e.g., Si based oxides, metal oxides, etc.), nitride (e.g., Si based nitride, etc.), low-k dielectric, high-k dielectric, and so on. Example hysteretic material include ferroelectric materials, antiferroelectric materials, and so on. In some embodiments, a portion of the electrical insulator 170 may include a first electrical insulator and a second electrical insulator with the second electrical insulator at least partially surrounding the first electrical insulator. An example of the first electrical insulator may be the insulative structure 626 in
The tight pitch region 210 include conductive structures 215 (individually referred to as “conductive structure 215”) and insulative structures 217 (individually referred to as “insulative structure 217”). The conductive structures 215 have longitudinal axes along the Z axis. Two adjacent conductive structures 215 are separated by an insulative structure 217. A pitch 213 of the conductive structures 215 is a length of a conductive structure 215 along the X axis. An example of the conductive structure 215 may be the gate contact 135A in
The loose pitch region 220 include conductive structures 225 (individually referred to as “conductive structure 225”) and insulative structures 227 (individually referred to as “insulative structure 227”). The conductive structures 225 have longitudinal axes along the Z axis. Two adjacent conductive structures 225 are separated by an insulative structure 227. In some embodiments, the loose pitch region 220 has a pitch 223, which is a length of a conductive structure 225 along the X axis. The pitch 223 is greater than the pitch 213 of the tight pitch region 210. An example of the conductive structure 225 may be the gate contact 135B in
The tight pitch region 230 include a conductive structure 235 and insulative structures 237 (individually referred to as “insulative structure 237”). The conductive structure 235 has a longitudinal axis along the Z axis. The conductive structure 235 is separated by a conductive structure 225 in the loose pitch region 220 by an insulative structure 227. For purpose of illustration,
An insulative structure 217, 227, or 237 may include a first insulative structure and a second insulative structure. The first insulative structure may be a layer of an electrical insulator that at least partially surrounds the second insulative structure. In some embodiments, the first insulative structure and the second insulative structure may include different insulators. In an example, the first insulative structure may include a nitride, such as silicon nitride, and the second insulative structure may include an oxide, such as silicon oxide.
Due to the differences in the pitches 213 and 223, the multi-pitch layer 200 has a multi-pitch pitch pattern, which causes challenges to pattern over the multi-pitch layer 200 through DSA of block copolymers, as DSA of block copolymer is usually limited to single pitch pattern. The single pitch pattern may be defined by an average molecular weight of the block copolymer. In an example, the average molecular weight block copolymer may be compatible with the pitch pattern of the tight pitch region 210 or 230 so that the conductive structure-insulative structure alternating pattern in the tight pitch region 210 or 230 may function as a guiding pattern for the DSA of the block copolymer. Lamellar structures formed through the self-assembly of the block copolymer can align with the conductive structure and insulative structures in the tight pitch regions 210 and 230.
However, given that the loose pitch region 220 has a different pitch pattern, the average molecular weight block copolymer is incompatible with the pitch pattern of the loose pitch region 220. Lamellar structures would fail to align with the conductive structure 225 or insulative structures 227 in the loose pitch region 220. This can result in undesired DSA single pitch, random fingerprint pattern, horizontal morphology, or some combination thereof over the loose pitch region 220. These undesired patterns formed over the loose pitch region 220 need to be removed, e.g., through cut mask.
As shown in
The loose pitch region 320 include a conductive structure 325 and insulative structures 327 (individually referred to as “insulative structure 327”). The conductive structure 325 is separated from a conductive structure 315 (i.e., the conductive structure 315 that is closest to the conductive structure 325) by an insulative structure 327 (i.e., the insulative structure 327 between the conductive structure 315 and the conductive structure 325). Even though
A layer 307 is formed over the multi-pitch layer 305. The layer 307 includes a diblock copolymer. The diblock copolymer may include two polymers: polymer A and polymer B. A molecule of the diblock copolymer may include a block of polymer A and a block of polymer B. A chain of the diblock copolymer has a repetitive pattern of blocks of polymer A alternating with blocks of polymer B. An individual block of polymer A includes predominantly a chain of covalently linked monomer A (e.g., A-A-A-A-A . . . ), whereas the block of polymer B includes predominantly a chain of covalently linked monomer B (e.g., B-B-B-B-B . . . ). The monomers A and B may represent any of the different types of monomers used in block copolymers known in the arts. Examples of the polymer A and polymer B include polyethylene, poly(methyl methacrylate), polystyrene, polyvinylchloride, polytetrafluorethylene, polydimethylsiloxane, some polyesters, some polyurethanes, acrylics, epoxies, P(t-Buytl Acrylate), polyacrylic acid, polyacrylamide, maleic anhydride polymers, polyethylene, polypropylene, polyacrylonitrile, polybutadiene, polyvinyl acetate, polyacetic acid, polybutyl acrylate, polylactic acid, polycaprolactone, poly(ethylene glycol), polyisoprene, and so on. In other embodiments, the polymer A or polymer B may be other polymers.
In some embodiments, the block of polymer A and the block of polymer B have different chemical properties. As one example, one of the blocks may be relatively more hydrophobic (e.g., water disliking) and the other may be relatively more hydrophilic (water liking). As another example, one of the blocks may be relatively more similar to oil and the other block may be relatively more similar to water. Such differences in chemical properties between the different blocks of polymers, whether a hydrophilic-hydrophobic difference or otherwise, may cause the diblock copolymer molecule to self-assemble. For example, the self-assembly may be based on microphase separation of the polymer blocks. Conceptually, this may be similar to the phase separation of oil and water which are generally immiscible. Similarly, differences in hydrophilicity between the polymer blocks (e.g., one block is relatively hydrophobic and the other block is relatively hydrophilic), may cause a roughly analogous microphase separation where the different polymer blocks try to separate from each other due to chemical dislike for the other.
However, because the polymer blocks are covalently bonded to one another, they cannot be completely separated on a macroscopic scale. Rather, polymer blocks of a given type may tend to segregate or conglomerate with polymer blocks of the same type of other molecules. Self-assembly of the diblock copolymer, whether based on hydrophobic-hydrophilic differences or otherwise, may be used to form extremely small periodic structures (e.g., precisely spaced nanoscale structures). In some embodiments, the diblock copolymer can be used to form lamellar structures based on which patterning of metal lines, vias, or other components of IC devices may be performed. The dimensions of the lamellar structures are dependent upon the molecular weight, the lengths of the polymer blocks, and so on.
In
The pitch of the DSA pattern may be the same or similar as the metal pitch of the tight pitch region 310 but is different from the metal pitch of the loose pitch region 320. Given the difference from the metal pitch of the loose pitch region 320, the DSA pattern cannot be formed over the whole loose pitch region 320. As shown in
The formation of the lamellar structures 335 and 337 may be facilitated by the alternating pattern of the conductive structures 315 and insulative structures 317. In some embodiments, the alternating pattern of the conductive structures 315 and insulative structures 317 may constitute a guiding pattern for the DSA of the diblock copolymer. For instance, polymer A in the diblock copolymer may have stronger chemical affinity with the material in the conductive structures 315 than the material in the insulative structures 317. Additionally or alternatively, polymer B in the diblock copolymer may have stronger chemical affinity with the material in the conductive structures 315 than the material in the insulative structures 317. As a result, the lamellar structures 335, which includes polymer A, are formed over the insulative structures 317, and the lamellar structures 335, which includes polymer B, are formed over the conductive structures 315.
In other embodiments, a guiding pattern may be formed over at least part of the multi-pitch layer 305 before the layer 307 is formed. The guiding pattern may include a surface treatment. For instance, polymers may be grated to the multi-pitch layer 305, e.g., by using end groups. Examples of the end groups include polyethylene, poly(methyl methacrylate), polystyrene, polyvinylchloride, polytetrafluorethylene, polydimethylsiloxane, some polyesters, some polyurethanes, acrylics, epoxies, P(t-Buytl Acrylate), polyacrylic acid, polyacrylamide, maleic anhydride polymers, polyethylene, polypropylene, polyacrylonitrile, polybutadiene, polyvinyl acetate, polyacetic acid, polybutyl acrylate, polylactic acid, polycaprolactone, poly(ethylene glycol), polyisoprene, and so on. Polymers may be grafted selectively to the top surfaces of the conductive structures 315 or the top surfaces of insulative structures 317. The surface treatment may change the chemical affinity of polymer A or polymer B with the conductive structures 315 or the insulative structures 317.
In some embodiments, polymer A and polymer B have different mechanical properties. For example, polymer A are more rigid than polymer B. Accordingly, the lamellar structures 335 are more rigid than the lamellar structures 337. In an embodiment, the lamellar structures 335 has a rigidity above a first threshold and the lamellar structures 337 has a rigidity below a second threshold that is lower than the first threshold. As polymer B is more flexible, the block of polymer B may be more easily stretched or compressed between the blocks of polymer A when the diblock copolymer forms the lamellar structures 335 and 337. In an embodiment, a block of polymer B folds onto itself during the self-assembly of the diblock copolymer molecule. The higher rigidity of the lamellar structures 335 helps ensure a uniform size of the lamellar structures 337 and consequently, help ensure a single pitch of the DSA pattern. Also, as the lamellar structures 337 is relatively flexible, the lamellar structures 337 can be removed through an etching process that does not or barely etch the lamellar structures 335.
In
In
A portion of the hard mask 410 fills the openings 339A and 339B. Another portion of the hard mask 410 is present over the lamellar structures 335. The hard mask material may be ashable, meaning the hard mask material can be removed through ashing. In some embodiments, the hard mask material may include carbon, such as amorphous carbon. Additionally or alternatively, the hard mask material may include other materials, such as hydrogen, one or more dopants (e.g., nitrogen, fluorine, boron, and silicon, etc.), and so on. The bonding structure of the hard mask material can vary from sp2 (graphite-like) or sp3 (diamond-like), or a combination of both, depending on the deposition conditions.
In
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As shown in
The loose pitch region 620 include a conductive structure 625 and insulative structures 627 (individually referred to as “insulative structure 627”). The conductive structure 625 is separated from a conductive structure 615 (i.e., the conductive structure 615 that is closest to the conductive structure 625) by an insulative structure 627 (i.e., the insulative structure 627 between the conductive structure 615 and the conductive structure 625). Even though
The conductive structure 625 may be embodiments of the conductive structure 325 in
Nitride structures 620A and 620B are over the conductive structures 615. The nitride structures 620A and 620B are separated by an opening over the insulative structure 617 between the conductive structures 615. Edges of the nitride structure 620A or 620B along the Z axis may be aligned with edges of the corresponding conductive structure 615 along the Z axis. The nitride structures 620A and 620B may be embodiments of the nitride structures 520A and 520B, respectively. An oxide structure 630 is over the loose pitch region 620. In some embodiments, the oxide structure 630 may contact the nitride structure 620B. The oxide structure 630 may be an embodiment of the oxide layer 430.
In
The insulative structure 645 at least partially surrounds the nitride structure 620B and the conductive structure 615 below the nitride structure 620B. A portion of the insulative structure 645 is over the oxide structure 630. In some embodiments, after the material in the insulative structure 618 is deposited, a portion of the material may be removed (e.g., through etch or polish) to form the insulative structure 640 or 645.
In
In
In
In
In some embodiments, further fabrication may be performed on the assembly 700 after the process in
As shown in
The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).
The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in
The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in
In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in
The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein and may include any of the embodiments of an IC device having one or more multi-pitch patterns. In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package. Importantly, even in such embodiments of an MCP implementation of the IC package 2200, one or more multi-pitch patterns may be provided in a single chip, in accordance with any of the embodiments described herein. The dies 2256 may include circuitry to perform any desired functionality. For example, one or more of the dies 2256 may be ESD protection dies, including one or more multi-pitch patterns as described herein, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), one or more of the dies 2256 may be memory dies (e.g., high bandwidth memory), etc. In some embodiments, any of the dies 2256 may include one or more multi-pitch patterns, e.g., metal lines as discussed above; in some embodiments, at least some of the dies 2256 may not include any Ill-N diodes with n-doped wells and capping layers.
The IC package 2200 illustrated in
In some embodiments, the circuit board 2302 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.
The IC device assembly 2300 illustrated in
The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may be or include, for example, a die (the die 2002 of
The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD protection devices, and memory devices. More complex devices such as further RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. In some embodiments, the IC devices implementing one or more multi-pitch patterns as described herein may also be implemented in/on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.
The IC device assembly 2300 illustrated in
such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any of the embodiments of the coupling components 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any of the embodiments of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured in accordance with any of the package-on-package structures known in the art.
A number of components are illustrated in
Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in
The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402. This memory may be used as cache memory and may include, e.g., eDRAM, and/or spin transfer torque magnetic random-access memory (STT-MRAM).
In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 2412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2412 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2412 may include multiple communication chips. For instance, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.
In various embodiments, IC devices as described herein may be particularly advantageous for use as part of ESD circuits protecting power amplifiers, low-noise amplifiers, filters (including arrays of filters and filter banks), switches, or other active components. In some embodiments, IC devices as described herein may be used in PMICs, e.g., as a rectifying diode for large currents. In some embodiments, IC devices as described herein may be used in audio devices and/or in various input/output devices.
The computing device 2400 may include battery/power circuitry 2414. The battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).
The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). The display device 2406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as discussed above). The audio output device 2408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). The GPS device 2416 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.
The computing device 2400 may include an other output device 2410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The computing device 2400 may include an other input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an IC device, including a first layer, including a first conductive structure, and a second conductive structure, where the second conductive structure is in parallel with the first conductive structure in a first direction, and a dimension of the second conductive structure in a second direction perpendicular to the first direction is greater than a dimension of the first conductive structure in the second direction; a second layer over the first layer, the second layer including a first structure over the first conductive structure, the first structure including a first dielectric material, a second structure over the second conductive structure, the second structure including the first dielectric material, and a third structure at least partially surrounding the second structure, the third structure including a second dielectric material that is different from the first dielectric material.
Example 2 provides the IC device according to example 1, where the second dielectric material includes silicon oxide.
Example 3 provides the IC device according to example 1 or 2, where the first dielectric material includes silicon nitride.
Example 4 provides the IC device according to any of the preceding examples, where the second structure is a guard ring of the second transistor.
Example 5 provides the IC device according to any of the preceding examples, where the first layer further includes an insulative structure between the first gate contact and the second gate contact, and a portion of the third structure is over the insulative structure.
Example 6 provides the IC device according to example 5, where the insulative structure includes a first electrical insulator and a second electrical insulator, the first electrical insulator surrounds the second electrical insulator at least partially, and a portion of the second structure is over a portion of the first electrical insulator.
Example 7 provides the IC device according to example 6, where the first electrical insulator includes the first dielectric material, or the second electrical insulator includes the second dielectric material.
Example 8 provides an IC device, including a transistor, including a channel region, and a gate contact over at least part of the channel region; a via over the gate contact, the via connected to the gate contact; a first structure over the gate contact, the first structure at least partially surrounding the via and including a first dielectric material that includes a nitride; and a second structure at least partially surrounding the first structure, the second structure including a second dielectric material that includes an oxide.
Example 9 provides the IC device according to example 8, further including an additional transistor including an additional channel region and an additional gate contact over at least part of the additional channel region, where the additional gate contact is in parallel with the gate contact in a first direction, a dimension of the gate contact in a second direction is greater than a dimension of the additional gate contact in the second direction, and the second direction is perpendicular to the first direction.
Example 10 provides the IC device according to example 9, further including a third structure over the additional gate contact, the third structure including the first dielectric material.
Example 11 provides the IC device according to example 10, further including an additional via connected to the additional gate contact, where the additional via is at least partially surrounded by the third structure.
Example 12 provides the IC device according to any one of examples 8-11, where the nitride includes silicon nitride, and the oxide includes silicon oxide.
Example 13 provides a method for forming an IC device, including forming a lamellar pattern over a first section of a layer through DSA of a block copolymer, the first section including a first conductive structure; forming a first structure over the first conductive structure based on the lamellar pattern, the first structure including a first dielectric material; forming a second structure over a second section of the layer, the second structure including a second dielectric material that is different from the first dielectric material, the second section including a second conductive structure; forming an insulative structure based on the lamellar pattern, the insulative structure at least partially surrounding the first structure; providing a first plug and a second plug, where at least a portion of the first plug is over at least a portion of the insulative structure, and the second plug is over the second structure; and forming a first opening in the first structure based on the first plug and forming a second opening in the second structure based on the second plug; and filling at least part of the first opening or the second opening with the first dielectric material.
Example 14 provides the method according to example 13, where the second conductive structure is in parallel with the first conductive structure in a first direction, a dimension of the second conductive structure in a second direction is greater than a dimension of the first conductive structure in the second direction, and the second direction is perpendicular to the first direction.
Example 15 provides the method according to example 14, where a dimension of the second opening in the second direction is greater than the dimension of the second conductive structure.
Example 16 provides the method according to any one of examples 13-15, where forming the lamellar pattern over the first section of the layer through the DSA of the block copolymer includes forming lamellar structures over the layer through the DSA of the block copolymer, where one or more lamellar structures are over the second section of the layer; and removing the one or more lamellar structures.
Example 17 provides the method according to any one of examples 13-16, where the lamellar pattern includes a lamellar structure, and the lamellar structure includes a polymer in the block copolymer.
Example 18 provides the method according to example 17, where forming the insulative structure based on the lamellar pattern includes forming an opening by removing the lamellar structure; providing a first electrical insulator into a first portion of the opening, the first electrical insulator at least partially surrounding the first structure; and providing a second electrical insulator into a second portion of the opening, where the insulative structure includes the first electrical insulator and the second electrical insulator.
Example 19 provides the method according to any one of examples 13-18, where forming the first opening in the first structure based on the first plug includes forming the first opening in a portion of the first structure, where the portion of the first structure is not over the first plug.
Example 20 provides the method according to any one of examples 13-19, where forming the second opening in the second structure based on the second plug includes forming the second opening in a portion of the second structure, where the portion of the second structure is not over the second plug.
Example 21 provides an IC package, including the IC device according to any one of examples 1-12; and a further IC component, coupled to the device.
Example 22 provides the IC package according to example 21, where the further IC component includes one of a package substrate, an interposer, or a further IC die.
Example 23 provides the IC package according to example 21 or 22, where the IC device according to any one of examples 1-12 may include, or be a part of, at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.
Example 24 provides an electronic device, including a carrier substrate; and one or more of the IC devices according to any one of examples 1-12 and the IC package according to any one of examples 21-23, coupled to the carrier substrate.
Example 25 provides the electronic device according to example 24, where the carrier substrate is a motherboard.
Example 26 provides the electronic device according to example 24, where the carrier substrate is a PCB.
Example 27 provides the electronic device according to any one of examples 24-26, where the electronic device is a wearable electronic device or handheld electronic device.
Example 28 provides the electronic device according to any one of examples 24-27, where the electronic device further includes one or more communication chips and an antenna.
Example 29 provides the electronic device according to any one of examples 24-28, where the electronic device is an RF transceiver.
Example 30 provides the electronic device according to any one of examples 24-28, where the electronic device is one of a switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communications device, e.g., of an RF transceiver.
Example 31 provides the electronic device according to any one of examples 24-30, where the electronic device is a computing device.
Example 32 provides the electronic device according to any one of examples 24-31, where the electronic device is included in a base station of a wireless communication system.
Example 33 provides the electronic device according to any one of examples 24-31, where the electronic device is included in a user equipment device of a wireless communication system.
Example 34 provides the method according to any one of examples 13-20, further including processes for forming the IC device according to any one of claims 1-12.
Example 35 provides the method according to any one of examples 13-20, further including processes for forming the IC package according to any one of the claims 21-23.
Example 36 provides the method according to any one of examples 13-20, further including processes for forming the electronic device according to any one of the claims 24-33.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
