Claims
- 1. A method of producing a multilayer wiring structure of a semiconductor device, comprising:a step of forming a first opening in a first insulating layer formed on a substrate and forming a lower plug in said first opening; a step of forming a wiring on said first insulating layer and said lower plug; and a step of forming a second insulating layer on said wiring, and forming, in said second insulating layer and said wiring, a second opening opposite to said first opening and with a depth of about ⅓ or more of the thickness of said wiring, and forming an upper plug in said second opening, at said lower plug forming step, a CMP or etching-back method being used such that the distance between top surface of said lower plug and top surface of said first insulating layer, is about ⅓ or less of the diameter of each of said upper and lower plugs.
Priority Claims (2)
Number |
Date |
Country |
Kind |
9-186140 |
Jul 1997 |
JP |
|
9-348965 |
Dec 1997 |
JP |
|
Parent Case Info
This application is a divisional of application Ser. No. 09/760,640 filed Jan. 17, 2001 now U.S. Pat. No. 6,580,176, which is a Divisional of application Ser. No. 09/113,370, filed Jul. 1, 1998, now U.S. Pat. No. 6,197,685.
US Referenced Citations (8)
Foreign Referenced Citations (6)
Number |
Date |
Country |
4-296041 |
Oct 1992 |
JP |
5-275428 |
Oct 1993 |
JP |
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May 1995 |
JP |
8-191104 |
Jul 1996 |
JP |
8-274101 |
Oct 1996 |
JP |
8-167609 |
Aug 1998 |
JP |
Non-Patent Literature Citations (2)
Entry |
“Impact of Test Structure Design on Electromigration Lifetime Measurements,” by Ting et al., Proc. of IEEE (1995), pp. 326-332. |
“Stress-induced Volding in Stacked Tungsten Via Structure,” by Domae et al., Proc. of IEEE, 98CH36173 36th Annual International Reliability Physics Symposium, Reno, Nevada (1998), pp. 318-323. |