Patent Application
20230253322
The present application relates to manufacturing of semiconductor integrated circuits. More particularly, it relates to a semiconductor structure for landing nano-TSV over buried power rail and method of manufacturing the same.
With the continuous pursuit for the reduction in size of semiconductor circuitry, it becomes increasingly difficult to physically align semiconductor devices in and/or at various integration levels. One such example includes the integration of buried power rails in a semiconductor substrate.
At current transistor node level, the critical dimension (CD) of buried power rail has become extremely small. In a process of forming nano through-silicon-via to land on the buried power rail, a bad or poor CD or overlay control may cause the nano through-silicon-via to be shorted to the substrate which normally directly surrounds the buried power rails.
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a substrate layer; and a buried power rail (BPR) embedded in the substrate layer, wherein the BPR is isolated from the substrate layer by an enlarged deep shallow-trench-isolation (STI) region. According to one embodiment, the enlarged deep STI region has a first width at near a top thereof and a second width at near a middle portion thereof, with the second width being larger than the first width.
In one embodiment, the semiconductor structure further includes a nano through-silicon via (nTSV), with a bottom portion of the nTSV contacting a bottom portion of the BPR, where the bottom portion of the nTSV is fully surrounded by the enlarged deep STI region.
In another embodiment, the nTSV is embedded in the substrate layer and sidewalls of the TSV are fully surrounded by and isolated from the substrate layer by the enlarged deep STI region.
Embodiments of present invention also provide a method of forming a semiconductor structure. In one embodiment, the method includes providing a semiconductor substrate; forming first recesses in the semiconductor substrate; deepening and laterally widening the first recesses to form enlarged deep STI regions; filling the enlarged deep STI regions with a dielectric material; and forming at least one buried power rail (BPR) inside the dielectric material in the enlarged deep STI regions.
In one embodiment, the method further includes flipping the semiconductor substrate upside down and forming a nano through-silicon via (nTSV) through at least a portion of the semiconductor substrate, wherein the nTSV contacts the at least one BPR.
In another embodiment, forming the nTSV further includes thinning down the semiconductor substrate to create a substrate layer and depositing an inter-level-dielectric (ILD) layer on top of the substrate layer.
In yet another embodiment, forming the nTSV further includes forming an nTSV opening through the ILD layer and the substrate layer to expose a bottom portion of the at least one BPR, via a patterning process, and filling the nTSV opening with one or more conductive materials to form the nTSV.
The present invention will be understood and appreciated more fully from the following detailed description of embodiments of present invention, taken in conjunction with accompanying drawings of which:
It will be appreciated that for simplicity and clarity purpose, elements shown in the drawings have not necessarily been drawn to scale. Further, and if applicable, in various functional block diagrams, two connected devices and/or elements may not necessarily be illustrated as being connected. In some other instances, grouping of certain elements in a functional block diagram may be solely for the purpose of description and may not necessarily imply that they are in a single physical entity or they are embodied in a single physical entity.
In the below detailed description and the accompanying drawings, it is to be understood that various layers, structures, and regions shown in the drawings are both demonstrative and schematic illustrations that are not drawn to scale. In addition, for the ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures may not be repeated for each of the drawings. It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present, such as 1% or less than the stated amount. Likewise, the terms “on”, “over”, or “on top of” that are used herein to describe a positional relationship between two layers or structures are intended to be broadly construed and should not be interpreted as precluding the presence of one or more intervening layers or structures.
The plurality of sets of fins may include multiple sets of fins and in this application a set of fins may include one or more fins. A set of fins may be created to make one type of field-effect-transistors (FETs) such as, for example, a p-type FET or an n-type FET. Hereinafter, a set of fins may be referred to a fin-set, and a set of fins that is created to make a p-type FET may be referred to as a PFET fin-set and a set of fins that is created to make an n-type FET may be referred to as an NFET fin-set.
As is illustrated in
Here, it is to be noted that other suitable dielectric materials, in addition to flowable oxide, may be used as well in forming the enlarged deep STI regions 510, 520, and 530. The dielectric material may be filled into the enlarged openings 410, 420, and 430, in spaces between the sidewalls of first recesses 330 previously covered by liners 340, and in spaces between and above first fin-set 210, second fin-set 220, third fin-set 230, and fourth fin-set 240. Embodiment then applies a chemical-mechanic-polishing (CMP) process to remove excessive dielectric material above the fins to polish down, for example, to the top of the fin hardmask.
More specifically, using lithographic patterning process, buried power rail trenches may be made inside enlarged deep STI regions 510, 520, and 530 and the trenches may be subsequently filled with one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), and/or copper (Cu) (with a thin adhesive metal liner, such as TiN), to form buried power rails 611, 621, and 631. According to embodiments of present invention, the trenches (for forming buried power rails) may be created entirely inside enlarged deep STI regions 510, 520, and 530 and there is no part of the trenches that open directly to semiconductor substrate 100. Thereafter, a dielectric liner such as, for example, a SiN liner may be optionally formed inside the trenches first before one or more conductive materials are used to fill up the openings to form buried power rails. For example, liners 612, 622, 632 may be formed lining the bottoms and sidewalls of the trenches and then metals, such as W, Co, Ru, and/or Cu with a thin adhesive metal liner such as TiN, may be used to fill the remaining trenches to form buried power rails 611, 621, and 631. However, since buried power rails 611, 621, and 631 are now surrounded by dielectric materials of enlarged deep STI regions 510, 520, and 530, liners 612, 622, and 632 may not be necessary. After the metal fill, the metals may be recessed, followed by dielectric overfill, planarization of the dielectric, and recess of the dielectric to reveal the active fins for further device fabrication.
According to one embodiment of present invention, at least a bottom portion and a lower portion of openings 1010 and 1020 may be created entirely inside enlarged deep STI regions 510 and 520. However, embodiments of present invention are not limited in this aspect and in one embodiment, as being described below in more details with reference to
Here it is to be noted that because at least a bottom portion of openings 1010 and 1020 are created entirely inside enlarged deep STI regions 510 and 520, a misalignment between, for example, BPR 621 and nTSV 1121 may cause a part 1123 of the bottom portion of nTSV 1121 to be exposed to enlarged deep STI region 520. Since enlarged deep STI region 520 is made of dielectric material such as flowable oxide, the misaligned part 1123 of the bottom portion of nTSV 1121 is still isolated from substrate layer 101.
Embodiments of present invention further include (1550) flipping the semiconductor substrate upside down and thinning down a thickness of the semiconductor substrate to create a substrate layer with the thinning process, in one embodiment, exposing the enlarged deep STI regions; (1560) creating nano through-silicon-via (nTSV) openings in the enlarged deep STI regions with at least a bottom portion of the openings being surrounded by the enlarged deep STI regions. This nTSV creation process may be made by first depositing an inter-level-dielectric (ILD) layer on top of the substrate layer, planarizing the ILD layer, and patterning the nTSV openings through a lithographic patterning and etching process. In one embodiment, sidewalls of the nTSV openings are not fully surrounded by the enlarged deep STI regions, and the embodiment may include (1570) lining the nTSV openings with a dielectric liner. Embodiments of present invention may further include (1580) metallizing the nTSV openings with conductive material to contact the buried power rails.
It is to be understood that the exemplary methods discussed herein for fabricating or manufacturing strained superlattice may be readily incorporated with other semiconductor processing flows, semiconductor devices, and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
Although exemplary embodiments have been described herein with reference to the accompanying figures, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made therein by one skilled in the art without departing from the scope of the appended claims.
It is to be understood that the various layers, structures, and/or regions described above are not necessarily drawn to scale. In addition, for ease of explanation one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given illustration or drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures.
Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be used to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
Terms such as “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present such as, by way of example only, 1% or less than the stated amount. Also, in the figures, the illustrated scale of one layer, structure, and/or region relative to another layer, structure, and/or region is not necessarily intended to represent actual scale.
Semiconductor devices and methods for forming same in accordance with the above-described techniques can be employed in various applications, hardware, and/or electronic systems, including but not limited to personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.
In some embodiments, the above-described techniques are used in connection with manufacture of semiconductor integrated circuit devices that illustratively include, by way of non-limiting example, CMOS devices, MOSFET devices, and/or FinFET devices, and/or other types of semiconductor integrated circuit devices that incorporate or otherwise utilize CMOS, MOSFET, and/or FinFET technology.
Accordingly, at least portions of one or more of the semiconductor structures described herein may be implemented in integrated circuits. The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip may be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip may then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product, such as a motherboard, or an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. Such changes, modification, and/or alternative embodiments may be made without departing from the spirit of present invention and are hereby all considered within the scope of present invention. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the spirit of the invention.
