Patent Application
20160148863
The present invention relates to multi-level wiring connecting semiconductor devices in an integrated circuit (IC), and more specifically, to stackable integrated circuits including through-substrate vias.
Through-substrate vias (TSVs) are implemented in a wide variety of multi-stack layered three-dimensional (3-D) integrated circuits, and provide vertical connections through one or more integrated circuit layers. Each layer consists of a substrate with circuit elements patterned therein, front end of line (FEOL) processing—and interconnect wiring constructed on the substrate surface—back end of line (BEOL) processing—that provides connections between the circuit elements. Referring to
As the dielectric layers are formed (i.e., stacked) during the BEOL process, however, the patterning of the metal layers 102-104 and vias 106 can be distorted after TSV insertion. For example, an inner side of the dielectric layer adjacent to a region reserved for the TSV 108 can realize a metal pattern distortion effect. Consequently, the distorted metal patterning can compromise the reliability and performance of the 3-D integrated circuit wiring 100.
According to at least one embodiment of the present invention, a 3-D integrated circuit wiring including a plurality of stacked dielectric levels formed on a substrate includes a plurality of non-contiguous dummy walls patterned in a corresponding dielectric level around a circuit wire keep out zone (KOZ). The non-contiguous dummy walls are formed in the circuit wire KOZ and have an outer side and an opposing inner side that extend along a first direction to define a length. A circuit wire segment is located at a first metal level and a second circuit wire segment is located at a second metal level different from the first metal level. The first and second metal levels are located adjacent the inner side of at least one non-contiguous dummy wall.
According to another embodiment, a method of forming a 3-D integrated circuit wiring comprises stacking a plurality of dielectric levels on a substrate to define a thickness of the 3-D integrated circuit wiring. The method further includes performing a back end of line (BEOL) process to pattern a metal level and via in at least one of the dielectric levels. The method further includes patterning a plurality of non-contiguous dummy wall elements at a respective metal level. The method further includes forming a through-substrate via (TSV) in an associated circuit wire keep out zone (KOZ).
Additional features are realized through the techniques of the present invention. Other embodiments are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the features, refer to the description and to the drawings.
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification.
The forgoing features are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
Various embodiments of the disclosure provide a 3-D integrated circuit wiring that includes one or more non-contiguous dummy wall elements that maintain the patterning of active metal layers and/or via elements during the BEOL fabrication process. The non-contiguous dummy wall elements are patterned in each layer at the same time as the active metal layers and/or via elements. Therefore the non-contiguous dummy wall elements may be formed at each layer of the 3-D integrated circuit wiring.
The non-contiguous dummy wall elements themselves are also formed from metal according to well-known BEOL processes and isolate the active metal layers from a keep out zone (KOZ). The KOZ defines a region at which to etch one or more dielectric layers to form a void extending vertically therethrough. The void is then subsequently filled with a conductive material such as a metal material, for example, to form a through-substrate via (TSV). Unlike conventional 3-D integrated circuit wiring that use continuous dummy structures to protect the active metal regions from moisture and debris that may be introduced after the active metal layers are completely formed, the non-contiguous dummy wall elements of the present invention preserve the patterns of the active metal layers and vias layer by layer during BEOL fabrication process but without intruding any extra mechanical stress to the nearby vias. In this manner, the distortion effect of the active metal layers and interconnects is prevented, especially at the sides of the active metal layers supported by the non-contiguous dummy wall elements.
With reference now to
The active metal layers define metal levels of the 3-D integrated circuit wiring 200. The metal levels include a first active metal layer 204 and a second active metal layer 206 disposed at a different layer than the first metal layer 204. Each of the metal layers 204-206 may be configured as one or more integrated circuit wire segments. According to an embodiment, the first metal layer 204 is located beneath the second metal layer 206. It should be appreciated that a multitude of metal layers may be included beyond what is illustrated in
The non-contiguous dummy wall elements 210 isolate the first metal layers 204, second metal layers 206, and via elements 208 from a dielectric KOZ 212. The dummy wall elements 210 extend along a first axis (e.g., X-axis) to define a length and a second axis (e.g., Y-axis) to define a width. Although
As described above, the dummy wall elements 210 are patterned from a metal material at the same time the metal layers 204-206 and via elements 208 are formed during the BEOL process. Various metal etching techniques are used to form the walls including, but not limited to, reactive ion etching. Unlike conventional contiguous metal walls used to protect the active regions from moisture and debris, the dummy wall elements 210 are non-contiguously disposed in the KOZ 212. That is, each individual dummy wall element 210 is separated from another thereby rending the dummy wall elements 210 as non-contiguous walls. Such non-contiguous elements have a certain degree of freedom for structural expansion during various fabrication thermal cycles and after fabrication thermal cycles.
According to an embodiment, layers of the dummy wall elements 210 are included with each layer metal layer 204-206. In this manner, each dummy wall element 210 also extends along the thickness of the 3-D integrated circuit wiring 200, i.e., a Z-axis (see
Although four groups of dummy wall elements 210 are illustrated, it is appreciated that other embodiments of the invention may include less or more dummy wall elements 210. For example, if metal layers 204 -206 are formed on only two sides of the KOZ 212, then only two dummy wall elements 210 may be patterned as opposed to surrounding the entire KOZ 212 with a single continuous wall. Accordingly, materials and fabrication processing steps may be reduced.
Turning now to
Turning to
Turning to
Turning now to
At operation 808, a second dielectric layer is formed on the first metal layer, and a second metal layer is patterned in the second dielectric layer. At operation 810, one or more second via elements are patterned in the second metal layer. At operation 812, a second layer of non-contiguous dummy wall elements are formed at the second metal layer. The second layer of non-contiguous dummy wall elements maintains the pattern of the second metal layer and the second vias. At operation 814, additional dielectric layers are stacked and patterned with metal layers, via elements, and non-contiguous dummy wall elements layer by layer as described above to form a desired thickness of the 3-D integrated circuit wiring. The non-contiguous dummy wall elements formed at each layer maintain the pattern of the metal layer and via elements as the 3-D integrated circuit wiring formed, e.g., stacked, during the BEOL process. At operation 816, an electrically conductive TSV is formed at the KOZ located adjacent the inner sides of the non-conductive dummy walls and is extended vertically through the 3-D integrated circuit wiring, and the method ends at operation 818. According to an embodiment, the TSV extends vertically through the thickness of the 3-D integrated circuit wiring and is formed adjacent to each non-contiguous dummy wall elements formed at each layer.
As described in detail above, various non-limiting embodiments of the invention include a 3-D integrated circuit wiring including non-contiguous dummy wall elements that preserve the patterns of the active metal layers and vias layer by layer during BEOL fabrication process. Further, the non-contiguous dummy wall elements that preserve the patterns of the active metal layers and vias layer without intruding any extra mechanical stress to the nearby vias. In this manner, the distortion effect of the active metal layers and interconnects is prevented, especially at the sides of the active metal layers supported by the non-contiguous dummy wall elements
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one more other features, integers, steps, operations, element components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the inventive teachings and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
The flow diagrams depicted herein are just one example. There may be many variations to this diagram or the operations described therein without departing from the spirit of the invention. For instance, the operations may be performed in a differing order or operations may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
While various embodiments have been described, it will be understood that those skilled in the art, both now and in the future, may make various modifications which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
