Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a method of manufacturing the nonvolatile semiconductor memory device.
Recently, in the field of NAND-type flash memories, attention has been focused on a laminated-type (three-dimensional) NAND-type flash memory as a device that can achieve high integration without being restricted by the limit of resolution of the lithography technology. This type of three-dimensional NAND-type flash memory includes a laminated body and a semiconductor layer. In the laminated body, a plurality of conductive films and interlayer insulating films are alternately laminated. The conductive film functions as word lines and selection gate lines. The semiconductor layer is formed to pass through these laminated films. This semiconductor layer functions as a body of a memory string. Between the semiconductor layer and the conductive film, a memory film that includes an electric charge accumulating film is formed.
In this three-dimensional NAND-type flash memory, the resistance of the contact for coupling a memory cell array and an external circuit tends to increase. Accordingly, it is required to reduce the resistance of this contact without increasing the occupation area.
A nonvolatile semiconductor memory device according to the embodiments described as follows includes a semiconductor substrate and a first semiconductor layer formed on a surface of the semiconductor substrate. A memory cell array includes a memory string formed to extend in a first direction vertical to the surface of the semiconductor substrate. The memory cell array is formed by coupling a plurality of memory cells in series. A contact extends in a direction vertical to the semiconductor substrate, and has one end coupled to the first semiconductor layer. The contact includes: a second semiconductor layer that is formed in the first semiconductor layer and has a higher impurity concentration than that of the first semiconductor layer; a silicide film that has one end coupled to the second semiconductor layer and extends in the first direction; and a metal film formed on an inner wall of the silicide film.
The following describes nonvolatile semiconductor memory devices according to embodiments in detail with reference to the accompanying drawings. Here, these embodiments are only examples, and are not described for the purpose of limiting the present invention. For example, in the following nonvolatile semiconductor memory devices, the memory string has the structure that extends in a straight line vertical to the substrate. The present invention is also applicable to a device that has a U shape by folding the memory string in the middle to the opposite side. The respective drawings of the nonvolatile semiconductor memory devices used in the following embodiments are schematically illustrated. The thickness, the width, the ratio, and similar parameter of the layer are different from actual parameters.
The following embodiments relate to a nonvolatile semiconductor memory device in a structure where a plurality of metal-oxide-nitride-oxide-semiconductor (MONOS) type memory cells (transistors) is disposed in a height direction. The MONOS type memory cell includes: a semiconductor film disposed in a columnar shape vertical to the substrate as a channel, and a gate electrode film disposed on the side surface of the semiconductor film via an electric charge accumulating layer. However, this is not also intended to limit the present invention. The present invention is applicable to the electric charge accumulating film of another type, for example, a semiconductor-oxide-nitride-oxide-semiconductor type (SONOS) memory cell or a floating-gate type memory cell.
The memory cell array 11 includes memory strings MS, drain-side selection transistors S1, and source-side selection transistors S2 on a semiconductor substrate (not illustrated in
As described later, the memory cell MC has the structure where a control gate electrode (word line) is disposed on the side surface of a columnar semiconductor film to be a channel via a memory film including an electric charge accumulating layer. The drain-side selection transistor and the source-side selection transistor each have the structure where a selection gate electrode (selection gate line) is disposed on the side surface of a columnar semiconductor film via a memory film including an electric charge accumulating layer. For simplification of the illustration,
The word line WL is coupled in common to the adjacent memory cells along the X direction (the word-line direction) in
Furthermore, the bit lines BL are disposed to extend in the Y direction (the bit-line direction) intersecting with the X direction (the word-line direction), and are collocated at a predetermined pitch in the X direction. The bit line BL is coupled to a plurality of the memory strings MS via the drain-side selection transistors Sl. Source lines SL, which are omitted in
The word-line driving circuit 12 is a circuit that controls the voltage to be applied to the word line WL. The source-side selection-gate-line driving circuit 13 is a circuit that controls the voltage to be applied to the source-side selection gate line SGS. The drain-side selection-gate-line driving circuit 14 is a circuit that controls the voltage to be applied to the drain-side selection gate line SGD. The sense amplifier 15 is a circuit for amplifying a signal (voltage) read out from a selected memory cell to the bit line BL.
A wiring portion 20 is a wiring portion for coupling the word lines WL and the selection gate lines SGD and SGS to the contacts. The word lines WL, the selection gate lines SGS and SGD have a structure processed in a staircase pattern such that the respective upper portions can independently be coupled to the contacts.
The following describes the detail of the structure of the memory cell array 11 with reference to
As illustrated in
The conductive film 22 can be formed of, for example, tungsten (W), tungsten nitride (WN), tungsten silicide (WSix), tantalum (Ta), tantalum nitride (TaN), tantalum silicide (TaSix), palladium silicide (PdSix), erbium silicide (ErSix), yttrium silicide (YSix), platinum silicide (PtSix), hafnium silicide (HfSix), nickel silicide (NiSix), cobalt silicide (CoSix), titanium silicide (TiSix), vanadium silicide (VSix), chrome silicide (CrSix), manganese silicide (MnSix), iron silicide (FeSix), ruthenium (Ru), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), vanadium (V), chrome (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), gold (Au), silver (Ag) or copper (Cu), or can be formed of a compound of these materials. The conductive film 22 may be formed of polysilicon with the addition of impurities.
In the peripheral area of the conductive film 22, a laminated film CF is formed. The laminated film CF includes a block insulating film 105, a block high-dielectric film 106, and a barrier metal 107. This point will be described later.
To pass through this laminated body of the interlayer insulating film 21 and the conductive film 22, semiconductor layers 23 having the longitudinal direction in the lamination direction (Z direction) are disposed at a predetermined pitch in the XY plane. Between: the semiconductor layer 23; and the conductive film 22 and the interlayer insulating film 21, a memory film 24 including an electric charge accumulating layer is formed. As described later, the memory film 24 can be formed by a laminated structure of: an electric charge accumulating film such as a silicon nitride film, and an oxide film such as a silicon oxide film. Depending on the accumulation amount of the electric charge to this electric charge accumulating film, the threshold voltage of the memory cell MC changes. The memory cell MC holds data corresponding to this threshold voltage.
The semiconductor layers 23 function as the channel regions (body) of the memory cell MC, the dummy cells DMC1 and DMC2, and the selection transistors S1 and S2 that are included in the NAND cell unit NU. These semiconductor layers 23 are coupled, on their upper ends, to the bit lines BL via contacts Cb. The bit lines BL having the longitudinal direction in the Y direction are collocated at a predetermined pitch along the X direction.
The lower end of the semiconductor layer 23 is coupled to a semiconductor layer 23′ (first semiconductor layer) formed on the surface of the semiconductor substrate SB. That is, the lower end of the semiconductor layer 23 is coupled to the source line SL via this semiconductor layer 23′ and a contact LI described later. The source lines SL are collocated to have the longitudinal direction in the Y direction, similarly to the bit lines BL.
Here, the laminated body of the interlayer insulating film 21 and the conductive film 22 in the memory cell array 11 are separated by blocks as the smallest unit of data erasure. At the boundary of the separation, a trench Tb is formed. In this trench Tb, an interlayer insulating film (not illustrated in
In the peripheral area of this semiconductor columnar portion 102, a tunnel insulating film 103 and an electric charge accumulating layer 104 are formed to surround this semiconductor columnar portion 102. The tunnel insulating film 103 is constituted of, for example, a silicon oxide film (SiOx), and functions as a tunnel insulating film of the memory cell MC or the dummy cell DMC. The electric charge accumulating layer 104 is constituted of, for example, a silicon nitride film (SiN), and has a function that traps electrons injected from the semiconductor columnar portion 102 via the tunnel insulating film 103 by a write operation. In this example, the tunnel insulating film 103 and the electric charge accumulating layer 104 are illustrated to be formed on the entire side surface of the semiconductor columnar portion 102. This, however, should not be construed in a limiting sense. The tunnel insulating film 103 and the electric charge accumulating layer 104 can be formed only on the side surface of the word line WL.
On the side surface of the electric charge accumulating layer 104, the above-described interlayer insulating film 21 and a tungsten electrode 108, which functions as the conductive film 22, are alternately laminated. However, in the peripheral area of the tungsten electrode 108, the block insulating film 105, the block high-dielectric film 106, and the barrier metal 107 are formed in this order from the outer side to surround the tungsten electrode 108. The block insulating film 105 can be formed of, for example, a silicon oxide film. In this example, the block insulating film 105 is formed to cover the peripheral area of the tungsten electrode 108. The block insulating film 105 can be formed on the entire side surface of the semiconductor columnar portion 102, similarly to the tunnel insulating film 103 and the electric charge accumulating layer 104.
Here, the materials of the tunnel insulating film 103 and the block insulating film 105 can employ, for example, Al2O3, Y2O3, La2O3, Gd2O3, Ce2O3, CeO2, Ta2O5, HfO2, ZrO2, TiO2, HfSiO, HfAlO, ZrSiO, ZrAlO, and AlSiO other than the silicon oxide film (SiOx).
The following describes the further detail of the structures of the memory cell array 11 and the wiring portion 20 with reference to
As illustrated in
As illustrated in
The above-described contact LI is implanted in the trench Tb, which divides the memory cell array 11 by blocks, via the interlayer insulating film 31. In the contact LI, the lower end is in contact with the semiconductor layer 23′ formed on the surface of the substrate SB while the upper end is coupled to the source line SL via upper-layer wiring. Here, in the example of
As illustrated in
The silicide film 33 is formed on the sidewall of the trench Tb via the interlayer insulating film 31, and is formed to have the longitudinal direction in the lamination direction. As described later, the silicide film 33 is formed by further depositing a metal film (such as nickel (Ni) and cobalt (Co)) on the silicon film formed on the sidewall of the interlayer insulating film 31 and by silicidizing this silicon film. The silicide film 33 has the film thickness (for example, approximately 20 nm to 30 nm) to the extent that the entire silicon layer can be silicidized by one silicidation process.
The barrier metal film 34 is formed along the inner wall of this silicide film 33. The barrier metal film 34 is formed by, for example, titanium nitride (TiN) or a laminated structure of titanium nitride and titanium. Further, the metal film 35 is formed on the inner wall of the trench Tb, that is, the silicide film 33 along the barrier metal film 34. The metal film 35 is constituted of, for example, metal such as tungsten (W). Thus, the contact LI according to this embodiment is formed of the multi-layer structure that includes the silicide film 33 in contact with the interlayer insulating film 31, the barrier metal film 34, and the metal film 35. The silicon layer is replaced by the silicide film 33. This allows reducing the resistance of the contact LI compared with the case where silicon is used as the material.
In the nonvolatile semiconductor memory device of the first embodiment, the barrier metal film 34 is formed on the silicide film 33. The barrier metal film 34 can employ a film of titanium nitride (TiN) alone. In this case, the production cost can be reduced.
Alternatively, the laminated film of titanium nitride (TiN) and titanium (Ti) can be used as the barrier metal film 34. In this case, titanium (Ti) is further silicidized on the silicide in the silicide film 33 to form titanium silicide, so as to ensure a dual silicide structure. This dual silicide structure reduces an excessive reaction of titanium silicide compared with the case where titanium is deposited on the silicon layer so as to form titanium silicide. Accordingly, a void is less likely to occur in the barrier metal film 34. This allows improving the yield of the contact LI. In the case where the laminated film of titanium nitride (TiN) and titanium (Ti) is used as the barrier metal film 34, the presence of titanium (Ti) allows reducing an increase in resistance of the silicide film 33 due to formation of a natural oxide film on silicide in the silicide film 33.
The following describes the structure of the wiring portion 20 with reference to
The following describes a method of manufacturing the portion of the contact LI in the nonvolatile semiconductor memory device 100 of the first embodiment with reference to
Firstly, as illustrated in
Subsequently, etching is performed to remove the interlayer insulating film 31 in the bottom portion of the trench Tb. Subsequently, as illustrated in
Subsequently, as illustrated in
Subsequently, as illustrated in
As described above, in the nonvolatile semiconductor memory device of the first embodiment, the contact LI is formed by the multi-layer structure of the silicide film 33, the barrier metal film 34, and the metal film 35. The silicon film is replaced by the silicide film 33. This allows reducing the resistance of the contact LI, thus reducing the power consumption. The small resistance of the contact LI allows decreasing the dimension of the contact LI in the lateral direction, thus being useful for downsizing the nonvolatile semiconductor memory device.
In this first embodiment, the silicon film in the contact LI is replaced by the silicide film 33 so as to form the barrier metal film 34 on this the silicide film 33. In this case, the barrier metal film 34 can be formed as, for example, a single-layer film of titanium nitride. This allows reducing the production cost compared with the case where the barrier metal film is formed to have the laminated structure of titanium nitride and titanium.
On the other hand, in the case where the barrier metal film 34 employs the laminated film of titanium nitride and titanium, this allows reducing an increase in resistance due to formation of the natural oxide film on the silicide film 33.
The following describes a nonvolatile semiconductor memory device 100 according to a second embodiment with reference to FIG. 14 to
The contact LI of this embodiment includes, similarly to the first embodiment, the semiconductor layer 32, the silicide film 33, the barrier metal film 34, and the metal film 35. However, the silicide film 33 of the second embodiment has a larger film thickness than that of the silicide film 33 of the first embodiment. On the lower side of the trench Tb, the silicide film 33 is formed to have a thickness to the extent of filling the trench Tb together with the interlayer insulating film 31. The silicide film 33 has a valley portion V only on the upper side of the silicide film 33. The barrier metal film 34 is formed along the inner wall of this valley portion V. Further, the metal film 35 faces the silicide film 33 via this barrier metal film 34. The metal film 35 is formed only in the valley portion V located in the upper portion of the trench Tb. This point is different from the first embodiment where the metal film 35 is formed to reach the lower side of the trench Tb.
In the case of the structure in this second embodiment, the film thickness of the silicide film 33 is increased. This allows decreasing the resistivity of the silicide film 33, thus reducing the resistance of the contact LI as a whole. This structure of the second embodiment can be obtained by using a metal that has a volume increased (expanded) after silicidation than the volume before silicidation and by repeatedly performing the silicidation process in the case where the silicide film 33 is formed.
The following describes a method of manufacturing the contact LI in the nonvolatile semiconductor memory device of this second embodiment with reference to
Firstly, similarly to the first embodiment (in
Subsequently, the silicidation process is performed to silicidize polysilicon in the polysilicon film 36. With the silicidation, polysilicon near the surface in the polysilicon film 36 is changed into the silicide film 33. In the polysilicon film 36, for example, polysilicon on the side close to the interlayer insulating film 31 is not silicidized and is left to be polysilicon.
Subsequently, as illustrated in
The second embodiment allows obtaining the same effects as those in the first embodiment. In addition, the second embodiment allows reducing the resistance of the contact LI compared with the first embodiment.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
This application is based on and claims the benefit of priority from prior U.S. prior provisional Patent Application No. 62/049,848, filed on Sep. 12, 2014, the entire contents of which are incorporated herein by reference.
Number | Date | Country | |
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62049848 | Sep 2014 | US |