Claims
- 1. A one time programmable structure in an integrated circuit comprising:
- a) a patterned first conductor having an overlying patterned first dielectric;
- b) a second dielectric adjacent the patterned sides of said first conductor and said first dielectric, said second dielectric being a thick dielectric spacer on a first patterned side of said first conductor and said first dielectric;
- c) a third dielectric layer blanketing said thick dielectric spacer, said first dielectric and a second patterned side of said first conductor and said first dielectric; and
- d) a patterned second conductor overlying said first conductor, said second conductor residing in intersecting angular fashion to said first conductor and said third dielectric being an interface therebetween.
- 2. The one time programmable structure of claim 1 wherein said structure is programmed by rupturing said third dielectric by applying a voltage potential between said first and said second conductors thereby producing an intercoupling pn junction therebetween.
- 3. The one time programmable structure of claim 1 wherein said integrated circuit comprises a memory device.
- 4. The integrated circuit of claim 3 wherein said memory device comprises a programmable read only memory.
- 5. The integrated circuit of claim 3 wherein said memory device comprises a programmable logic array.
- 6. The integrated circuit of claim 3 wherein said memory device comprises programmable array logic.
- 7. A process to fabricate a one time programmable structure on a starting substrate of an integrated circuit comprising:
- a) forming an isolative dielectric layer superjacent said substrate;
- b) placing a first conductive material superjacent said isolative dielectric layer;
- c) forming a first dielectric layer superjacent said first conductive material;
- d) patterning said first conductive material and said first dielectric layer thereby forming first conductive lines spaced apart in parallel rows, said conductive lines having first and second sides;
- e) forming a second dielectric layer superjacent and coextensive said first conductive lines and exposed portions of said isolative dielectric layer;
- f) patterning said second dielectric layer thereby forming a thick dielectric spacer superjacent said first side of each said first conductive lines;
- g) forming a third dielectric layer blanketing said thick dielectric spacer, said second side of said first conductive lines and said first dielectric;
- h) placing a second conductive material superjacent said third dielectric layer; and
- i) patterning second conductive material thereby forming second conductive lines spaced apart in parallel columns, said parallel columns overlying said first conductive lines in an intersecting angular fashion.
- 8. The process of claim 7 wherein said substrate comprises silicon.
- 9. The process of claim 7 wherein said isolative dielectric, said first dielectric and said third dielectric layers comprise oxide.
- 10. The process of claim 7 wherein said third dielectric layer comprises ozone.
- 11. The process of claim 7 wherein said third dielectric layer comprises ozone formed form a TEOS source gas.
- 12. The process of claim 7 wherein said second dielectric layer comprises oxide/nitride/oxide.
- 13. The process of claim 7 wherein said first and said second conductive materials comprise doped polysilicon.
- 14. The process of claim 7 wherein the vertical width of said first conductor is the limiting lithography resolution dimension of said process.
Parent Case Info
This is a divisional to U.S. patent application No. 07/760,026 filed Sept. 11, 1991, now U.S. Pat. No. 5,126,290.
US Referenced Citations (4)
Divisions (1)
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Number |
Date |
Country |
Parent |
760026 |
Sep 1991 |
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