Patent Application
20230068160
This application claims the priority benefit of Taiwan application serial no. 110131543, filed on August 25, 2021. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The invention relates to a substrate structure, and particularly relates to a package carrier and a package structure using the package carrier.
With the thinning of electronic devices, a current trend is to directly connect heterogeneous semiconductor components to reduce the use of intermediate substrates. Accordingly, not only the size of a semiconductor package may be reduced, but also an electrical path may be shortened to improve the calculation speed of the semiconductor package. However, how to directly connect the heterogeneous semiconductor components has become an urgent problem to be solved at present.
The invention is directed to a package carrier, which meets a current trend of lightweight, thinness, and compactness through heterogeneous integration characteristics.
The invention is also directed to a package structure, which adopts the aforementioned package carrier to achieve a thinner package thickness, a better heat dissipation effect and better structural reliability.
The invention provides a package carrier including a multi-layer circuit substrate and a silicon wafer. The multi-layer circuit substrate has a first opening and a second opening communicating with each other. A first diameter and a first depth of the first opening are respectively greater than a second diameter and a second depth of the second opening. The silicon wafer is embedded in the first opening of the multi-layer circuit substrate. The silicon wafer has an active surface and includes a connecting circuit layer. The connecting circuit layer is disposed on the active surface and electrically connected to the multi-layer circuit substrate. The second opening of the multi-layer circuit substrate exposes part of the connecting circuit layer.
In an embodiment of the invention, the multi-layer circuit substrate includes a core dielectric layer, a first patterned circuit layer, a second patterned circuit layer, a first dielectric layer, a third patterned circuit layer, a second dielectric layer, a fourth patterned circuit layer, at least one first conducting via, at least one second conducting via, at least one third conducting via, and at least one fourth conducting via. The core dielectric layer has an upper surface and a lower surface opposite to each other. The first patterned circuit layer is disposed on the upper surface of the core dielectric layer. The second patterned circuit layer is disposed on the lower surface of the core dielectric layer. The first dielectric layer is disposed on the upper surface of the core dielectric layer and covers the first patterned circuit layer. The third patterned circuit layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the lower surface of the core dielectric layer and covers the second patterned circuit layer. The fourth patterned circuit layer is disposed on the second dielectric layer. The first conducting via penetrates through the core dielectric layer and electrically connected to the first patterned circuit layer and the second patterned circuit layer. The second conducting via penetrates through the first dielectric layer and electrically connected to the third patterned circuit layer and the first patterned circuit layer. The third conducting via penetrates through the second dielectric layer and electrically connected to the fourth patterned circuit layer and the second patterned circuit layer. The fourth conducting via penetrates through the first dielectric layer and electrically connected to the third patterned circuit layer and the connecting circuit layer of the silicon wafer.
In an embodiment of the invention, the multi-layer circuit substrate further includes a first solder mask layer and a second solder mask layer. The first solder mask layer covers the first dielectric layer and the third patterned circuit layer. The first solder mask layer has a third opening and a plurality of first open pores. The third opening communicates with the second opening and the first opening, and a third diameter of the third opening is greater than or equal to the second diameter. The first open pores expose part of the third patterned circuit layer to define a plurality of first pads. The second solder mask layer covers the second dielectric layer and the fourth patterned circuit layer. The second solder mask layer has a plurality of second open pores, and the second open pores expose part of the fourth patterned circuit layer to define a plurality of second pads.
In an embodiment of the invention, the package carrier further includes a first surface treatment layer and a second surface treatment layer. The first surface treatment layer is disposed on the first pads. The second surface treatment layer is disposed on the second pads.
In an embodiment of the invention, the package carrier further includes an insulating material filled in the first opening of the multi-layer circuit substrate. The silicon wafer is fixed in the first opening through the insulating material.
The invention provides a package structure including a package carrier and at least one chip. The package carrier includes a multi-layer circuit substrate and a silicon wafer. The multi-layer circuit substrate has a first opening and a second opening communicating with each other. A first diameter and a first depth of the first opening are respectively greater than a second diameter and a second depth of the second opening. The silicon wafer is embedded in the first opening of the multi-layer circuit substrate. The silicon wafer has an active surface and includes a connecting circuit layer. The connecting circuit layer is disposed on the active surface and electrically connected to the multi-layer circuit substrate. The second opening of the multi-layer circuit substrate exposes part of the connecting circuit layer. The chip is disposed on the package carrier and is located in the second opening of the multi-layer circuit substrate, where the chip is electrically connected to the connecting circuit layer of the silicon wafer.
In an embodiment of the invention, the multi-layer circuit substrate includes a core dielectric layer, a first patterned circuit layer, a second patterned circuit layer, a first dielectric layer, a third patterned circuit layer, a second dielectric layer, a fourth patterned circuit layer, at least one first conducting via, at least one second conducting via, at least one third conducting via, and at least one fourth conducting via. The core dielectric layer has an upper surface and a lower surface opposite to each other. The first patterned circuit layer is disposed on the upper surface of the core dielectric layer. The second patterned circuit layer is disposed on the lower surface of the core dielectric layer. The first dielectric layer is disposed on the upper surface of the core dielectric layer and covers the first patterned circuit layer. The third patterned circuit layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the lower surface of the core dielectric layer and covers the second patterned circuit layer. The fourth patterned circuit layer is disposed on the second dielectric layer. The first conducting via penetrates through the core dielectric layer and electrically connected to the first patterned circuit layer and the second patterned circuit layer. The second conducting via penetrates through the first dielectric layer and electrically connected to the third patterned circuit layer and the first patterned circuit layer. The third conducting via penetrates through the second dielectric layer and electrically connected to the fourth patterned circuit layer and the second patterned circuit layer. The fourth conducting via penetrates through the first dielectric layer and electrically connected to the third patterned circuit layer and the connecting circuit layer of the silicon wafer.
In an embodiment of the invention, the multi-layer circuit substrate further includes a first solder mask layer and a second solder mask layer. The first solder mask layer covers the first dielectric layer and the third patterned circuit layer. The first solder mask layer has a third opening and a plurality of first open pores. The third opening communicates with the second opening and the first opening, and a third diameter of the third opening is greater than or equal to the second diameter. The first open pores expose part of the third patterned circuit layer to define a plurality of first pads. The second solder mask layer covers the second dielectric layer and the fourth patterned circuit layer. The second solder mask layer has a plurality of second open pores, and the second open pores expose part of the fourth patterned circuit layer to define a plurality of second pads.
In an embodiment of the invention, the package carrier further includes a first surface treatment layer and a second surface treatment layer. The first surface treatment layer is disposed on the first pads. The second surface treatment layer is disposed on the second pads.
In an embodiment of the invention, the package carrier further includes an insulating material filled in the first opening of the multi-layer circuit substrate. The silicon wafer is fixed in the first opening through the insulating material.
In an embodiment of the invention, the at least one chip includes a first chip and a second chip. The first chip is electrically connected to the connecting circuit layer of the silicon wafer in a flip-chip manner, and the second chip is electrically connected to the third patterned circuit layer in a wire bonding manner.
In an embodiment of the invention, the package structure further includes a package body and an optical fiber. The package body is disposed in the second opening of the multi-layer circuit substrate and is electrically connected to the connecting circuit layer of the silicon wafer. The package body and the chip are electrically connected through the connecting circuit layer. The optical fiber is disposed on the multi-layer circuit substrate, the optical fiber and the package body are located on the same side of the multi-layer circuit substrate, and the package body is electrically connected to the optical fiber.
In an embodiment of the invention, the chip includes a first chip and a second chip. The first chip and the second chip are respectively electrically connected to the connecting circuit layer of the silicon wafer in a flip-chip manner. The first chip and the second chip are electrically connected through the connecting circuit layer.
In summary, in the design of the package carrier of the invention, the silicon wafer is embedded in the first opening of the multi-layer circuit substrate, the second opening of the multi-layer circuit substrate exposes the connecting circuit layer of the silicon wafer, and the connecting circuit layer is electrically connected to the multi-layer circuit substrate. In this way, the package carrier of the invention may achieve an effect of heterogeneous integration and may meet the current trend of lightweight, thinness, and compactness. In addition, regarding the package structure using the package carrier of the invention, the chip is disposed in the second opening of the multi-layer circuit substrate and electrically connected to the connecting circuit layer of the silicon wafer, the silicon wafer may transmit signals through electric conduction, a material thereof has a heat dissipation effect, and a thermal expansion coefficient thereof is similar to that of the chip, so the package structure of the invention has both a thinner package thickness and a good heat dissipation effect as well as structural reliability.
To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
A first diameter W1 and a first depth D1 of the first opening H1 are respectively greater than a second diameter W2 and a second depth D2 of the second opening H2. The silicon wafer 120 is embedded in the first opening H1 of the multi-layer circuit substrate 110. The silicon wafer 120 has an active surface S and includes a connecting circuit layer 122. The connecting circuit layer 122 is disposed on the active surface S and is electrically connected to the multi=layer circuit substrate 110. The second opening H2 of the multi-layer circuit substrate 110 exposes part of the connecting circuit layer 122.
In detail, the multi-layer circuit substrate 110 of the embodiment includes a core dielectric layer 112, a first patterned circuit layer 111, a second patterned circuit layer 113, a first dielectric layer 114, and a third patterned circuit layer 115, a second dielectric layer 116, a fourth patterned circuit layer 117, at least one first conducting via T1, at least one second conducting via T2, at least one third conducting via T3, and at least one fourth conducting via T4. The core dielectric layer 112 has an upper surface S1 and a lower surface S2 opposite to each other. The first patterned circuit layer 111 is disposed on the upper surface Si of the core dielectric layer 112. The second patterned circuit layer 113 is disposed on the lower surface S2 of the core dielectric layer 112. The first dielectric layer 114 is disposed on the upper surface Si of the core dielectric layer 112 and covers the first patterned circuit layer 111. The third patterned circuit layer 115 is disposed on the first dielectric layer 114. The second dielectric layer 116 is disposed on the lower surface S2 of the core dielectric layer 112, and covers the second patterned circuit layer 113. The fourth patterned circuit layer 117 is disposed on the second dielectric layer 116. The first conducting via T1 penetrates through the core dielectric layer 112 and electrically connects the first patterned circuit layer 111 and the second patterned circuit layer 113. The second conducting via T2 penetrates through the first dielectric layer 114 and electrically connects the third patterned circuit layer 115 and the first patterned circuit layer 111. The third conducting via T3 penetrates through the second dielectric layer 116 and electrically connects the fourth patterned circuit layer 117 and the second patterned circuit layer 113. The fourth conducting via T4 penetrates through the first dielectric layer 114 and electrically connects the third patterned circuit layer 115 and the connecting circuit layer 122 of the silicon wafer 120. In brief, the multi-layer circuit substrate 110 of the embodiment is embodied as a four-layer circuit substrate, but it is only an example, and the invention is not limited to the four-layer circuit substrate.
In addition, the multi-layer circuit substrate 110 of the embodiment further includes a first solder mask layer 118 and a second solder mask layer 119. The first solder mask layer 118 covers the first dielectric layer 114 and the third patterned circuit layer 115. The first solder mask layer 118 has a third opening H3 and a plurality of first open pores A1. The third opening H3 communicates with the second opening H2 and the first opening H1, and a third diameter W3 of the third opening H3 is greater than the second diameter W2. The first open pores Al expose part of the third patterned circuit layer 115 to define a plurality of first pads P1. The second solder mask layer 119 covers the second dielectric layer 116 and the fourth patterned circuit layer 117. The second solder mask layer 119 has a plurality of second open pores A2, and the second open pores A2 expose part of the fourth patterned circuit layer 117 to define a plurality of second pads P2.
In order to prevent oxidation of the first pad P1 and the second pad P2, the package carrier 100a of the embodiment further includes a first surface treatment layer 130 and a second surface treatment layer 140. The first surface treatment layer 130 is disposed on the first pad P1, and the second surface treatment layer 140 is disposed on the second pad P2. The first surface treatment layer 130 and the second surface treatment layer 140 are, for example, respectively a nickel layer, a gold layer, a silver layer or a nickel-palladium-gold layer, but the invention is not limited thereto. The arrangement of the first surface treatment layer 130 and the second surface treatment layer 140 may not only avoid oxidation of the first pad P1 and the second pad P2 but may also make wires to be easily electrically connected with the first pad P1 and the second pad P2 in the subsequent electrical connection with the chip through wire bonding.
In addition, the package carrier 100a of the embodiment further includes an insulating material 150 filled in the first opening H1 of the multi-layer circuit substrate 110. The silicon wafer 120 is fixed in the first opening H1 through the insulating material 150, where the insulating material 150 is, for example, hole plugging resin. Namely, when the silicon wafer 120 is embedded in the first opening H1 of the multi-layer circuit substrate 110, there is a gap between the silicon wafer 120 and an inner wall of the first opening H1, and the insulating material 150 may be filled in the gap and located between the silicon wafer 120 and the first opening H1 to fix and position the silicon wafer 120. Preferably, a top view shape of the first opening H1 is a rounded rectangle.
Moreover, a thickness of the silicon wafer 120 of the embodiment is approximately equal to a thickness of the core dielectric layer 112 (i.e., the first depth D1). When the silicon wafer 120 is embedded in the first opening H1 of the multi-layer circuit substrate 110, preferably, the active surface S of the silicon wafer 120 is aligned with the upper surface Si of the core dielectric layer 112, and a bottom surface of the silicon wafer 120 is aligned with the lower surface S2, which may effectively reduce an overall package thickness of the subsequent chip package. Moreover, the second opening H2 of the multi-layer circuit substrate 110 only exposes part of the connecting circuit layer 122 of the silicon wafer 120, which means that part of the connecting circuit layer 122 is covered by the first dielectric layer 114, and the connecting circuit layer 122 exposed outside the first dielectric layer 114 may be directly electrically connected to an electronic element, subsequently.
In brief, since the silicon wafer 120 of this embodiment is embedded in the first opening H1 of the multi-layer circuit substrate 110, and the second opening H2 of the multi-layer circuit substrate 110 exposes the connecting circuit layer 122 of the silicon wafer 120, and the connecting circuit layer 122 is electrically connected to the third patterned circuit layer 115 of the multi-layer circuit substrate 110 through the fourth conducting via T4. In this way, the package carrier 100a of the embodiment may achieve the effect of heterogeneous integration and may meet the current trend of lightweight, thinness, and compactness.
It should be noticed that reference numbers of the components and part of contents of the aforementioned embodiment are also used in the following embodiment, where the same reference numbers denote the same or like components, and descriptions of the same technical contents are omitted. The aforementioned embodiment may be referred for descriptions of the omitted parts, and detailed descriptions thereof are not repeated in the following embodiment.
In brief, in the embodiment, the first chip 20, the chip 40, the package body 50, and the chip 70 are directly electrically connected to the connecting circuit layers 122, 122′ of the silicon wafers 120, 120′, where besides that the silicon wafers 120, 120′ may transmit signals through electric conduction, and materials thereof have a heat dissipation effect and thermal expansion coefficients thereof are similar to that of the chip. Therefore, the package structures 10a, 10b and 10c of the invention not only have a thinner package thickness, but also have a better heat dissipation effect and structural reliability.
In summary, in the design of the package carrier of the invention, the silicon wafer is embedded in the first opening of the multi-layer circuit substrate, the second opening of the multi-layer circuit substrate exposes the connecting circuit layer of the silicon wafer, and the connecting circuit layer is electrically connected to the multi-layer circuit substrate. In this way, the package carrier of the invention may achieve an effect of heterogeneous integration and may meet the current trend of lightweight, thinness, and compactness. In addition, regarding the package structure using the package carrier of the invention, the chip is disposed in the second opening of the multi-layer circuit substrate and electrically connected to the connecting circuit layer of the silicon wafer, the silicon wafer may transmit signals through electric conduction, a material thereof has a heat dissipation effect, and a thermal expansion coefficient thereof is similar to that of the chip, so the package structure of the invention has both a thinner package thickness and a good heat dissipation effect as well as structural reliability.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the invention covers modifications and variations provided they fall within the scope of the following claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 110131543 | Aug 2021 | TW | national |
