PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Abstract

A package structure and manufacturing method thereof. The package structure includes first package assembly and a second package assembly. The first package assembly includes a first dielectric layer, a first chip and a first conductive structure. The first chip is disposed in the first dielectric layer, and a first electrical connection surface of the first conductive structure is exposed on a first bonding surface of the first dielectric layer. The second package assembly includes a second dielectric layer, a second chip and a second conductive structure. The second chip is disposed in the second dielectric layer, and a second electrical connection surface of the second conductive structure is exposed on a second bonding surface of the second dielectric layer. The first bonding surface is directly bonded to the second bonding surface, and the first electrical connection surface is directly bonded to the second electrical connection surface.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

All related applications are incorporated by reference. The present application is based on, and claims priority from, Taiwan (International) application No. 112145984 filed on Nov. 28, 2023, the disclosure of which is hereby incorporated by reference herein in its entirety.

TECHNICAL FIELD

The disclosure relates to a package structure and a manufacturing method thereof.

BACKGROUND

In order to realize the signal transfer between two package assemblies, when the two package assemblies are bonded into a package structure, one or more bumps are usually used to electrically connect the contacts of the two package assemblies.

However, such electrical connection between contacts created by the bumps not only reduces the reliability of the package structure by causing warpage thereon, but also limits the density and performance of the package structure by enlarging the volume thereof. In addition, since there is a gap between the two package assemblies that are electrically connected via bumps, it is required to complete the bonding of the two package assemblies via a packaging process performed by filling additional molding compound in the gap between the two package assemblies.

SUMMARY

One embodiment of this disclosure provides a package structure including a first package assembly and a second package assembly. The first package assembly includes a first dielectric layer, a first chip and a first conductive structure. The first chip is disposed in the first dielectric layer, and a first electrical connection surface of the first conductive structure is exposed on a first bonding surface of the first dielectric layer. The second package assembly includes a second dielectric layer, a second chip and a second conductive structure. The second chip is disposed in the second dielectric layer, and a second electrical connection surface of the second conductive structure is exposed on a second bonding surface of the second dielectric layer. The first bonding surface of the first dielectric layer is directly bonded to the second bonding surface of the second dielectric layer, and the first electrical connection surface is directly bonded to the second electrical connection surface.

Another embodiment of this disclosure provides a manufacturing method of a package structure including providing a first package assembly and a second package assembly, wherein the first package assembly comprises a first dielectric layer, a first chip and a first conductive structure, the first chip is disposed in the first dielectric layer, a first electrical connection surface of the first conductive structure is exposed on a first bonding surface of the first dielectric layer, the second package assembly comprises a second dielectric layer, a second chip and a second conductive structure, the second chip is disposed in the second dielectric layer, and a second electrical connection surface of the second conductive structure is exposed on a second bonding surface of the second dielectric layer; and directly bonding the first bonding surface of the first dielectric layer to the second bonding surface of the second dielectric layer, and directly bonding the first electrical connection surface of the first conductive structure to the second electrical connection surface of the second conductive structure to form a package structure.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will become better understood from the detailed description given herein below and the accompanying drawings which are given by way of illustration only and thus are not intending to limit the present disclosure and wherein:

FIGS. 1 to 14 show a manufacturing method of a package structure according to a first embodiment of the disclosure;

FIG. 15 shows a manufacturing method of a package structure according to a second embodiment of the disclosure;

FIG. 16 is a cross-sectional view of a package structure according to a third embodiment of the disclosure;

FIG. 17 is a cross-sectional view of a package structure according to a fourth embodiment of the disclosure;

FIG. 18 is a cross-sectional view of a package structure according to a fifth embodiment of the disclosure;

FIG. 19 is a cross-sectional view of a package structure according to a sixth embodiment of the disclosure;

FIG. 20 is a cross-sectional view of a package structure according to a seventh embodiment of the disclosure; and

FIG. 21 is a cross-sectional view of a package structure according to an eighth embodiment of the disclosure.

DETAILED DESCRIPTION

In the following detailed description, for purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.

Please refer to FIGS. 1 to 14. FIGS. 1 to 14 show a manufacturing method of a package structure 10 according to a first embodiment of the disclosure.

As shown in FIG. 1, a first package assembly 100 and a second package assembly 200 are provided.

The first package assembly 100 includes a first dielectric layer 110, a first chip 120, a plurality of first conductive structures 130 and a capacitive structure 170. In this embodiment, the first dielectric layer 110 may include a molding compound 111, a first polymer layer 112 and a second polymer layer 113. The first polymer layer 112 and the second polymer layer 113 are disposed on two opposite sides of the molding compound 111, respectively. The first chip 120 is disposed in the molding compound 111, and is in, for example, a face-down form. The second polymer layer 113 has a first bonding surface 1130 facing away from the molding compound 111.

A plurality of first electrical connection surfaces 131 of the first conductive structure 130 are exposed on the first bonding surface 1130. That is, the first electrical connection surfaces 131 provide a plurality of contacts, respectively. In this embodiment, the first electrical connection surface 131 is flushed with the first bonding surface 1130. In other embodiments, the first conductive structure may have one first electrical connection surface.

In this embodiment, the first conductive structure 130 may include a first circuit layer 140, a second circuit layer 150 and a plurality of first conductive vias 160. The first circuit layer 140 is disposed in the first polymer layer 112. The first circuit layer 140 and the first polymer layer 112 may together be referred as a redistribution layer (RDL). The second circuit layer 150 is disposed in the second polymer layer 113. The second circuit layer 150 and the second polymer layer 113 may together be referred as a RDL. The first conductive vias 160 penetrate through the molding compound 111 and the second polymer layer 113, and electrically connect the first circuit layer 140 and the second circuit layer 150. The first electrical connection surfaces 131 are located on the second circuit layer 150 and the first conductive vias 160.

The capacitive structure 170 is disposed on the first polymer layer 112. The capacitive structure 170 is electrically connected to the first chip 120 via an electrical connection structure 175 disposed on the first polymer layer 112. In this embodiment, the capacitive structure 170 is entirely not overlapped with the first chip 120 along a stacking direction S of the molding compound 111, the first polymer layer 112 and the second polymer layer 113. Accordingly, the overall thickness (i.e., the thickness of the first package assembly 100 along the stacking direction S) of the first package assembly 100 is reduced.

In this embodiment, there may be solder balls 185 and a substrate 190 disposed on a side of the first package assembly 100. The solder balls 185 are electrically connected to the first circuit layer 140, so as to electrically connect the substrate 190 to the first circuit layer 140. In other embodiments, the solder balls 185 and the substrate 190 disposed on a side of the first package assembly may be omitted.

The second package assembly 200 includes a second dielectric layer 210, a plurality of second chips 220 and a second conductive structure 230. In this embodiment, the second dielectric layer 210 may include a molding compound 211, a third polymer layer 212 and a fourth polymer layer 213. The second chips 220 are disposed in the molding compound 211. The third polymer layer 212 and the fourth polymer layer 213 are disposed on two opposite sides of the molding compound 211, respectively. The second conductive structure 230 is, for example, a circuit layer. The second conductive structure 230 is disposed in the fourth polymer layer 213, and is disposed on the second chip 220. The fourth polymer layer 213 has a second bonding surface 2130 facing away from the molding compound 211. A plurality of second electrical connection surfaces 231 of the second conductive structure 230 are exposed on the second bonding surface 2130. That is, the second electrical connection surfaces 231 provide a plurality of contacts, respectively. In addition, in this embodiment, the second electrical connection surface 231 is flushed with the second bonding surface 2130. In other embodiments, the second package assembly may include one second chip. In other embodiments, the second conductive structure 230 may have one second electrical connection surface 231.

For example, as shown in FIGS. 2 to 8, a process for providing the first package assembly 100 may include following steps. As shown in FIG. 2, a substrate 20 is provided. The substrate 20 may be a glass carrier substrate, a metal substrate or a silicon substrate. In addition, a release layer 21 may be disposed on the substrate 20. Next, as shown in FIG. 3, an intermediate layer 22 is formed on the release layer 21, and a bottom RDL including the first circuit layer 140 and the first polymer layer 112 and the electrical connection structure 175 are formed on the intermediate layer 22. The intermediate layer 22 is, for example, a seed layer. Next, as shown in FIG. 4, the plurality of first conductive vias 160 are formed on the first circuit layer 140. Next, as shown in FIG. 5, the first chip 120 and the capacitive structure 170 are bonded to the bottom RDL. Next, as shown in FIG. 6, the molding compound 111 is formed on the bottom RDL, and a planarization is performed on the first chip 120 and the molding compound 111 by, for example, polishing. Next, as shown in FIG. 7, a top RDL including the second circuit layer 150 and the second polymer layer 113 is formed on the first chip 120 and the molding compound 111, and a planarization is performed on the second circuit layer 150 and the second polymer layer 113 by, for example, polishing. Next, as shown in FIGS. 7 and 8, the substrate 20, the release layer 21 and the intermediate layer 22 are removed to provide the first package assembly 100.

As shown in FIGS. 9 to 13, a process for providing the second package assembly 200 may include following steps. As shown in FIG. 9, a substrate 30 is provided. The substrate 30 may be a glass carrier substrate, a metal substrate or a silicon substrate. Further, a release layer 31 may be disposed on the substrate 30. Next, as shown in FIG. 10, an intermediate layer 32 is formed on the release layer 31, and the third polymer layer 212 is formed on the intermediate layer 32. The intermediate layer 32 is, for example, a seed layer. Next, as shown in FIG. 11, the second chip 220 is bonded to the third polymer layer 212, and the second conductive structure 230 is formed on the second chip 220. Next, as shown in FIG. 12, the molding compound 211 and the fourth polymer layer 213 are formed on the third polymer layer 212, and a planarization is performed on the fourth polymer layer 213 and the second conductive structure 230 by, for example, polishing. Next, as shown in FIGS. 12 and 13, the substrate 30, the release layer 31 and the intermediate layer 32 are removed to provide the second package assembly 200.

In this embodiment, the molding compounds 111 and 211, the first polymer layer 112, the second polymer layer 113, the third polymer layer 212 and the fourth polymer layer 213 may be made of the same material, such as Ajinomoto Build-Up Film (ABF) or Epoxy.

Next, as shown in FIG. 14, a bonding process is performed. The said bonding process includes directly bonding the first bonding surface 1130 of the first dielectric layer 110 to the second bonding surface 2130 of the second dielectric layer 210, and directly bonding the first electrical connection surfaces 131 of the first conductive structure 130 to the second electrical connection surfaces 231 of the second conductive structure 230, so as to form a package structure 10.

In the bonding process, the second polymer layer 113 and the fourth polymer layer 213 that do not totally cure are pressed under a temperature ranging from 90 degrees Celsius to 130 degrees Celsius. Next, the first bonding surface 1130 is directly bonded to the second bonding surface 2130 under a temperature ranging from 100 degrees Celsius to 250 degrees Celsius when the second polymer layer 113 and the fourth polymer layer 213 are melted. Next, the first electrical connection surfaces 131 of the first conductive structure 130 are directly bonded to the second electrical connection surfaces 231 of the second conductive structure 230 under a temperature ranging from 150 degrees Celsius to 400 degrees Celsius, so as to electrically connect the first conductive structure 130 to the second conductive structure 230. In FIG. 14, for the convenience of description, the boundary line between the first bonding surface 1130 and the second bonding surface 2130 and the boundary line between the first electrical connection surface 131 and the second electrical connection surface 231 are shown. In practical, the first bonding surface 1130 and the second bonding surface 2130 that are bonded may be integrally formed as a single piece without any boundary therebetween, and the first electrical connection surface 131 and the second electrical connection surface 231 that are bonded may be integrally formed as a single piece without any boundary therebetween.

The first bonding surface 1130 is directly bonded to the second bonding surface 2130, and the first electrical connection surfaces 131 are directly bonded to the second electrical connection surfaces 231. Thus, without any bump, the warpage is prevented from occurring on the first package assembly 100 and the second package assembly 200 and thus the reliability thereof is enhanced. Moreover, the volume of the package structure 10 is reduced so that the density and the performance of the package structure 10 is allowed to be improved.

Furthermore, since the first dielectric layer 110 and the second dielectric layer 210 are directly used as molding compound after the first bonding surface 1130 and the second bonding surface 2130 are bonded, the process of filling additional molding compound is allowed to be omitted. In this way, the manufacturing process of the package structure 10 is simplified.

Other embodiments are described below for illustrative purposes. The following embodiments use the reference numerals and a part of the contents of the above embodiments, the same reference numerals are used to denote the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the above embodiments, and details are not described in the following embodiments.

In this disclosure, the electrical connection surface is not limited to being flush with the bonding surface. Please refer to FIG. 15 that shows a manufacturing method of a package structure according to a second embodiment of the disclosure. The difference between the manufacturing method of a package structure of this embodiment and that of the first embodiment is in the relationship between the electrical connection surface and the bonding surface. In detail, in this embodiment, in the step of providing a first package assembly 100a and a second package assembly 200a, a plurality of first electrical connection surfaces 131a located on a second circuit layer 150a and a first conductive via 160a protrude from the first bonding surface 1130 along a direction away from the first chip 120, and a plurality of second electrical connection surfaces 231a of a second conductive structure 230a protrude from the second bonding surface 2130 along a direction away from the second chip 220. For example, a protruding length L1 of each first electrical connection surface 131a relative to the first bonding surface 1130 is smaller than 1.5 micrometers (μm), and a protruding length L2 of each second electrical connection surface 231a relative to the second bonding surface 2130 is smaller than 1.5 μm. In this embodiment, the first electrical connection surfaces 131a and the second electrical connection surfaces 231a are adjusted to respectively protrude from the first bonding surface 1130 and the second bonding surface 2130 according to the coefficients of thermal expansion of the second polymer layer 113 and the fourth polymer layer 213. In this way, after being bonded, the first electrical connection surfaces 131a, the second electrical connection surfaces 231a, the first bonding surface 1130 and the second bonding surface 2130 are allowed to be flush with one another without being uneven due to the coefficients of thermal expansion of the second polymer layer 113 and the fourth polymer layer 213.

Please refer to FIG. 16 that is a cross-sectional view of a package structure 10b according to a third embodiment of the disclosure. The difference between the package structure 10b of this embodiment and the package structure 10 of the first embodiment is in that a first package assembly 100b of the package structure 10b further includes a plurality of second conductive vias 183b. The second conductive vias 183b penetrate through the first chip 120, and electrically connect the first chip 120 and the second circuit layer 150b, thereby improving the efficiency for one or more signals to be transferred between the first chip 120 and the second circuit layer 150b.

The disclosure is not limited by the quantity and the position of the capacitive structure. Please refer to FIG. 17 that is a cross-sectional view of a package structure 10c according to a fourth embodiment of the disclosure. The difference between the package structure 10c of this embodiment and the package structure 10 of the first embodiment is in that a first package assembly 100c of the package structure 10c of this embodiment includes a plurality of capacitive structures 170c. The capacitive structures 170c are located between the first chip 120 and the first polymer layer 112. Furthermore, the capacitive structures 170c are electrically connected to the first chip 120 via a plurality of electrical connection structures 175c, respectively. Since the capacitive structures 170c are disposed between the first chip 120 and the first polymer layer 112, the efficiency for one or more signals to be transferred between the capacitive structure 170c and the first chip 120 is improved.

The disclosure is not limited by the configuration of the first chip. Please refer to FIG. 18 that is a cross-sectional view of a package structure 10d according to a fifth embodiment of the disclosure. The difference between the package structure 10d of this embodiment and the package structure 10 of the first embodiment is in the configuration of the first chip 120d. In this embodiment, the first chip 120d is in, for example, a face-up form. In addition, in this embodiment, the first chip 120d may be electrically connected to the second circuit layer 150d.

Please refer to FIG. 19 that is a cross-sectional view of a package structure 10e according to a sixth embodiment of the disclosure. The difference between the package structure 10e of this embodiment and the package structure 10 of the first embodiment is in that the package structure 10e of this embodiment further includes a third package assembly 300e, and the second package assembly 200e further includes structures for bonding the third package assembly 300e. In detail, in this embodiment, with respect to the second package assembly 200 of the first embodiment, the second package assembly 200e further includes a third conductive structure 240e and a plurality of conductive vias 260e. The third conductive structure 240e is, for example, a circuit layer, and is disposed in the third polymer layer 212. A plurality of third electrical connection surfaces 241e of the third conductive structure 240e are exposed on a third bonding surface 2120e of the third polymer layer 212 facing away from the second bonding surface 2130. The conductive vias 260e penetrate through the second dielectric layer 210, and electrically connect the second conductive structure 230 and the third conductive structure 240e.

The third package assembly 300e includes a third dielectric layer 310e, a third chip 320e, and a fourth conductive structure 330e. The third dielectric layer 310e includes a molding compound 311e and two polymer layers 312e and 313e. The third package assembly 300e and the second package assembly 200 in the first embodiment are similar in structure, and thus the repeated descriptions are omitted. A plurality of fourth electrical connection surfaces 331e of the fourth conductive structure 330e are exposed on a fourth bonding surface 3130e of the polymer layer 313e. The third bonding surface 2120e of the second dielectric layer 210 is directly bonded to the fourth bonding surface 3130e of the third dielectric layer 310e, and the third electrical connection surfaces 241e are directly bonded to the fourth electrical connection surfaces 331e.

The disclosure is not limited by the configuration of the first conductive via. Please refer to FIG. 20 that is a cross-sectional view of a package structure 10f according to a seventh embodiment of the disclosure. The difference between the package structure 10f of this embodiment and the package structure 10 of the first embodiment is in the configuration of the first conductive via 160f. In the first package assembly 100f of this embodiment, the first conductive vias 160f of a first conductive structure 130f penetrate through the molding compound 111 without penetrating through the first polymer layer 112 and the second polymer layer 113. In addition, the first conductive vias 160f electrically connect the first circuit layer 140 and a second circuit layer 150f.

The disclosure is not limited by the configuration of the first circuit layer. Please refer to FIG. 21 that is a cross-sectional view of a package structure 10g according to an eighth embodiment of the disclosure. The difference between the package structure 10g of this embodiment and the package structure 10f of the seventh embodiment is in the configuration of a first circuit layer 140g. In this embodiment, the first circuit layer 140g includes, for example, two circuit layers. Additionally, in this embodiment, an electrical connection structure 175g is located in the first polymer layer 112. The electrical connection structure 175g may be formed together with the first circuit layer 140g. The first circuit layer 140g, the electrical connection structure 175g and the first polymer layer 112 may together be referred as a RDL.

According to the package structure and the manufacturing method thereof disclosed by above embodiments, the first bonding surface is directly bonded to the second bonding surface, and the first electrical connection surfaces are directly bonded to the second electrical connection surfaces. Thus, without any bump, the warpage is prevented from occurring on the first package assembly and the second package assembly and thus the reliability thereof is enhanced. Moreover, the volume of the package structure is reduced so that the density and the performance of the package structure is allowed to be improved.

Furthermore, since the first dielectric layer and the second dielectric layer are directly used as molding compound after the first bonding surface and the second bonding surface are bonded, the process of filling additional molding compound is allowed to be omitted. In this way, the manufacturing process of the package structure is simplified.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.

Claims

1. A package structure, comprising: a first package assembly, comprising a first dielectric layer, a first chip and a first conductive structure, wherein the first chip is disposed in the first dielectric layer, and a first electrical connection surface of the first conductive structure is exposed on a first bonding surface of the first dielectric layer; anda second package assembly, comprising a second dielectric layer, a second chip and a second conductive structure, wherein the second chip is disposed in the second dielectric layer, and a second electrical connection surface of the second conductive structure is exposed on a second bonding surface of the second dielectric layer; andwherein the first bonding surface of the first dielectric layer is directly bonded to the second bonding surface of the second dielectric layer, and the first electrical connection surface is directly bonded to the second electrical connection surface.

2. The package structure according to claim 1, wherein the first conductive structure of the first package assembly comprises a first circuit layer, a second circuit layer and a first conductive via, the first dielectric layer comprises a molding compound, a first polymer layer and a second polymer layer, the first polymer layer and the second polymer layer are disposed on two opposite sides of the molding compound, respectively, the first chip is disposed in the molding compound, the first bonding surface is located on the second polymer layer and faces away from the molding compound, the first circuit layer and the second circuit layer are disposed in the first polymer layer and the second polymer layer, respectively, the first electrical connection surface is located on the second circuit layer, and the first conductive via penetrates through the molding compound and electrically connects the first circuit layer and the second circuit layer.

3. The package structure according to claim 2, wherein the first package assembly further comprises at least one capacitive structure disposed on the first polymer layer and electrically connected to the first chip.

4. The package structure according to claim 3, wherein the at least one capacitive structure is entirely not overlapped with the first chip along a stacking direction of the molding compound, the first polymer layer and the second polymer layer.

5. The package structure according to claim 3, wherein the at least one capacitive structure comprises a plurality of capacitive structures located between the first chip and the first polymer layer.

6. The package structure according to claim 2, wherein the first package assembly further comprises a second conductive via, the second conductive via penetrates through the first chip and electrically connects the first chip and the second circuit layer.

7. The package structure according to claim 2, wherein the molding compound, the first polymer layer and the second polymer layer are made of same material.

8. The package structure according to claim 7, wherein the molding compound, the first polymer layer and the second polymer layer are made of ABF or Epoxy.

9. The package structure according to claim 1, further comprising a third package assembly, wherein the second package assembly further comprises a third conductive structure, a third electrical connection surface of the third conductive structure is exposed on a third bonding surface of the second dielectric layer facing away from the second bonding surface, the third package assembly comprises a third dielectric layer, a third chip and a fourth conductive structure, the third chip is disposed in the third dielectric layer, a fourth electrical connection surface of the fourth conductive structure is exposed on a fourth bonding surface of the third dielectric layer, the third bonding surface of the second dielectric layer is directly bonded to the fourth bonding surface of the third dielectric layer, and the third electrical connection surface is directly bonded to the fourth electrical connection surface.

10. The package structure according to claim 1, wherein the first bonding surface is directly bonded to the second bonding surface when a part of the first dielectric layer and a part of the second dielectric layer are melted.

11. A manufacturing method of a package structure, comprising: providing a first package assembly and a second package assembly, wherein the first package assembly comprises a first dielectric layer, a first chip and a first conductive structure, the first chip is disposed in the first dielectric layer, a first electrical connection surface of the first conductive structure is exposed on a first bonding surface of the first dielectric layer, the second package assembly comprises a second dielectric layer, a second chip and a second conductive structure, the second chip is disposed in the second dielectric layer, and a second electrical connection surface of the second conductive structure is exposed on a second bonding surface of the second dielectric layer; anddirectly bonding the first bonding surface of the first dielectric layer to the second bonding surface of the second dielectric layer, and directly bonding the first electrical connection surface of the first conductive structure to the second electrical connection surface of the second conductive structure to form a package structure.

12. The manufacturing method of a package structure according to claim 11, wherein in a step of providing the first package assembly and the second package assembly, the first electrical connection surface is flush with the first bonding surface and the second electrical connection surface is flush with the second bonding surface.

13. The manufacturing method of a package structure according to claim 11, wherein in a step of providing the first package assembly and the second package assembly, the first electrical connection surface protrudes from the first bonding surface along a direction away from the first chip, and the second electrical connection surface protrudes from the second bonding surface along a direction away from the second chip.

14. The manufacturing method of a package structure according to claim 11, wherein the first bonding surface is directly bonded to the second bonding surface under a temperature ranging from 100 degrees Celsius to 250 degrees Celsius when a part of the first dielectric layer and a part of the second dielectric layer are melted.

15. The manufacturing method of a package structure according to claim 11, wherein the first electrical connection surface is directly bonded to the second electrical connection surface under a temperature ranging from 150 degrees Celsius to 400 degrees Celsius.