Patent Application
20150130084
The present invention relates to a semiconductor package, and particularly relates to a fan-out package structure having a heat radiating side edge.
In order to meet current requirements for the portability and versatility of computer and consumer electronics products, the size hereof is required to be further reduced as the integration density of integrated circuit chips becomes greater. Due to the limitation of available space, various packaging methods have emerged; for example, the multi-chip module (MCM), flip chip package, three-dimensional (3D) stack package, and wafer level chip scale package (WLCSP). Basically, the concept of the wafer level packaging technology consists of chip scale packaging being executed on wafers. Most of the packaging work, such as directly forming solder balls on an integrated circuit chip, is completed during the wafer stage. This not only omits the chip carrier, such as a substrate or a lead frame in the conventional packaging technology, but also simplifies the packaging process. Therefore, the WLCSP can decrease the package size and has considerable advantages regarding the process and the material costs.
In general, a package structure requires polishing and dicing processes in the backend. In order to radiate the heat that is generated in the operations, a heat sink 5 and thermal paste 7 are attached on the backside of the package structure as shown in
In a conventional embodiment, the thermal paste 7 and the heat sink 5 provide a longitudinal direction (an arrow in
Examples of the present disclosure provide a fan-out package structure having a heat radiating side edge that includes a semiconductor substrate; a bond pad located on the semiconductor substrate; and a redistribution layer connected with the bond pad and located on the semiconductor substrate, wherein an end of the redistribution layer extends to a sidewall of the semiconductor substrate, and in which the end is coplanar with the sidewall.
In some embodiments, the sidewall includes a rough surface.
In some embodiments, the semiconductor substrate has a backside with a rough surface.
In some embodiments, the redistribution layer is located on a periphery of the semiconductor substrate.
Examples of the present disclosure provide a package structure having a heat radiating pattern that includes a semiconductor substrate; a bond pad located on the semiconductor substrate; and a heat radiating pattern located on the semiconductor substrate, wherein the heat radiating pattern includes a redistribution layer connected with the bond pad and located on a periphery of the semiconductor substrate, and in which an end of the redistribution layer is coplanar with a sidewall of the semiconductor substrate.
In some embodiments, the heat radiating pattern is a circular structure surrounding the periphery of the semiconductor substrate.
Examples of the present disclosure provide a method for manufacturing a fan-out package structure having a heat radiating side edge that includes providing a semiconductor substrate having a bond pad on a front side of the semiconductor substrate; forming a first dielectric layer on the front side of the semiconductor substrate; and forming a redistribution layer connected with the bond pad and located on the first dielectric layer and periphery of the semiconductor substrate, wherein an end of the redistribution layer is coplanar with a sidewall of the semiconductor substrate.
In some embodiments, the method further includes forming a protection layer on the front side of the semiconductor substrate, wherein a backside of the semiconductor substrate and the sidewall are exposed.
In some embodiments, the method further includes immersing the semiconductor substrate in an etching solution so as to wet micro etch the backside and the sidewall.
In some embodiments, the method further includes electroless plating the backside and the sidewall.
In some embodiments, the method further includes forming a protection layer on the backside of the semiconductor substrate.
In some embodiments, the method further includes immersing the semiconductor substrate in an etching solution so as to wet micro etch the sidewall.
In some embodiments, the method further includes electroless plating the sidewall.
Aspects of the present disclosure are described with reference to the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The making and using of various embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.
In some embodiments, as shown in
In this embodiment, the second dielectric layer 51 covers the redistribution layer 41. The second dielectric layer 51 extends to the sidewall 26. In addition, an end of the second dielectric layer 51 is coplanar with the sidewall 26. The second dielectric layer 51 includes an opening 55. The opening 55 exposes a portion of the redistribution layer 41. The opening 55 serves as a position for the solder ball 61. In some embodiments, an under bump metallization (UBM, not shown) is formed in the opening 55. Later, the solder ball 61 is formed on the under bump metallization. Therefore, the solder ball 61 electrically connects to the redistribution layer 41.
The redistribution layer 41 not only serves as an internal and electrical connection of the package structure 10, but also provides a heat radiating path. The solder ball 61 and the bond pad 22 are major heat generating regions. The electrical transmission will bring out heat generation. Effectively, the redistribution layer 41 provides a thermally conductive path. The redistribution layer 41 transmits not only electrical signals, but also heat. Furthermore, the redistribution layer 41 is made of metal that provides higher thermal conductivity than dielectric materials. During electrical transmission, the heat is guided to a periphery of the semiconductor substrate 21 and the sidewall 26 by paths of the redistribution layer 41. Further, the redistribution layer 41 radiates the heat by convection or conduction with external environments so that heat dissipation is accelerated.
In some embodiments, the sidewall 26 is a rough surface. The semiconductor substrate 21 bears heat generated by internal circuits. Effectively, the rough surface of the sidewall 26 increases surface area for heat that is radiated. The rough surface of the sidewall 26 accelerates convection or conduction with external environments so that the heat is removed from the semiconductor substrate 21. The sidewall 26 with the rough surface prevents overheating of the semiconductor substrate 21, wherein the overheating would cause electrical deviation or noise. Moreover, the sidewall 26 with the rough surface provides a laterally cooling mechanism. In other words, the sidewall 26 provides a lateral heat radiating path for heat dissipation. In some embodiments, the rough surface is plated with metal having a better thermal conductivity so as to increase convection with outside environments.
Further, in some embodiments, the sidewall 26 and the backside 28 are both rough surfaces so as to increase surface area for heat radiating. With the redistribution layer 41 and the rough surfaces, radiation ability of the package structure 10 is improved. In comparison to prior arts, package structures of prior arts require a polishing or planarization for the backside and attachment of a heat sink. In the present disclosure, the backside 28 omits additional polishing or planarization, and thereby reduces the cost and complexity of the manufacturing process. Further, the backside 28 is performed to form a rough surface instead of polishing. As such, the backside 28 with the rough surface serves as a heat radiating path for the heat of the semiconductor substrate 21. In addition, the backside 28 occupies most of the surface of the package structure 10 so that the backside 28 provides a large area for heat dissipation. The backside 28 with the rough surface provides a longitudinally cooling mechanism that replaces the heat sink. In some embodiments, the backside 28 with the rough surface is plated with metal having a better thermal conductivity so as to increase convection with outside environments.
Manufacturing methods of the package structure 10 in
A passivation layer 23 is formed on the semiconductor substrate 21. Later, the passivation layer 23 is patterned to expose a portion of the bond pad 22. The passivation layer 23 is made of passivation materials, such as silicon oxide or nitride. The passivation layer 23 is formed by sputtering, vapor deposition or coating. Later, a patterned photoresist layer or a mask is formed on the passivation layer 23. An etching process is performed to expose a portion of the bond pad 22. Next, the patterned photoresist layer or the mask is removed.
Afterward, a pattern layer 24 is deposited on the passivation layer 23. The pattern layer 24 includes a predetermined opening above the bond pad 22. The pattern layer 24 is made of a polymer dielectric layer, but is not limited thereto. The pattern layer 24 is formed by coating. Liquid polymer is uniformly coated on the semiconductor substrate 21 by a spin coating machine. A mask shields some predetermined positions for openings.
An exposure process is performed. Later, a development process is performed to remove unexposed regions to form the predetermined opening above the bond pad 22. Further, the liquid polymer is baked by an oven so that the polymer is solidified to form the pattern layer 24. A side edge of the passivation layer 23 and a side edge of the pattern layer 24 form an end surface 25. In other words, an end of the passivation layer 23 is coplanar with an end of the pattern layer 24 so as to form the end surface 25.
Subsequently, a first dielectric layer 31 is formed on the front side 27 of the semiconductor substrate 21. The first dielectric layer 31 includes, for example, an oxide layer, a nitride layer or a polymer layer. The first dielectric layer 31 is formed by a variation method, such as CVD, PVD or a spin coating process, depending on different requirements. The first dielectric layer 31 covers the pattern layer 24 and a portion of the semiconductor substrate 21. The first dielectric layer 31 includes an extended dielectric layer 32. The extended dielectric layer 32 covers the end surface 25 and extends to the sidewall 26. An end of the extended dielectric layer 32 is coplanar with the sidewall 26. The first dielectric layer 31 conforms to height difference of layers so as to form an approximately trapezoidal distribution.
Then, a redistribution layer 41 connected with the bond pad 22 is formed. The redistribution layer 41 is located on the first dielectric layer 31 and a periphery of the semiconductor substrate 21. An end of the redistribution layer 41 is coplanar with the sidewall 26 of the semiconductor substrate 21. The redistribution layer 41 provides a current path and a heat transmission path. The redistribution layer 41 dissipates internal heat generated by the electrical connection to the periphery regions. The redistribution layer 41 includes metal, such as copper, silver, palladium, gold or alloys thereof. The redistribution layer 41 is formed by a variation method, such as CVD or PVD.
A second dielectric layer 51 is formed on the redistribution layer 41. Later, a photoresist layer or a mask is patterned to define an opening 55. An etching process, such as a dry etch, a wet etch or an optical etch, is performed to expose a portion of the redistribution layer 41. In some embodiments, an under bump metallization (UBM) is formed in the opening 55. The UBM includes at least two metal layers, an adhesive layer and a seed layer. The adhesive layer directly connects with the redistribution layer 41. The adhesive layer is usually made of titanium or titanium tungsten (TiW) in order to provide a better mechanically connection and better adhesion between the redistribution layer 41 and a solder ball 61. The seed layer is made of metal, such as gold, copper, nickel or alloy thereof. The UBM is formed by a metal sputtering process, vapor deposition process or printing process.
Next, the solder ball 61 is formed on the UBM or directly on the redistribution layer 41. In this embodiment, the solder ball 61 is made of tin. The solder ball 61 is formed by, for example, screen printing, vapor deposition, electroplating, dropping ball, or spray ball process.
As shown in a right diagram in
The backside 28 with a rough surface serves as a heat radiating path for heat dissipation. In comparison, the present disclosure omits backside grinding, thermal paste and attachments of a heat sink; thereby significantly reducing the cost and complexity of the manufacturing process.
In some embodiments, after the solder ball 61 is formed, a protection layer 71 is formed on the front side 27 of the semiconductor substrate 21. In addition, a protection layer 72 is formed on the backside 28 as shown in
The above description includes exemplary operations, but these operations are not necessarily required to be performed in the order shown. Operations may be added, replaced, changed order, skipped, and/or eliminated as appropriate, in accordance with the spirit and scope of the disclosure. Accordingly, the scope of the disclosure should be determined with reference to the following claims, along with the full scope of equivalences to which such claims are entitled.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102141194 | Nov 2013 | TW | national |
