Patent Application
20250079282
Semiconductor wafers are circular pieces of semiconductor material, such as silicon, that are used to manufacture semiconductor chips. Generally, complex manufacturing processes are used to form numerous integrated circuits on a single wafer. The formation of such circuits on a wafer is called fabrication. After wafer fabrication, the wafer is cut into multiple pieces, called semiconductor dies, with each die containing one of the circuits. The cutting, or sawing, of the wafer into individual dies is called singulation.
In examples, a package comprises a semiconductor die having a device side including circuitry formed therein. The package comprises a substrate facing and coupled to the device side. The substrate includes first and second metal layers. The first metal layer is positioned closer to the device side than the second metal layer and is coupled to the second metal layer by way of a via. At least one of the first and second metal layers has a top surface facing the semiconductor die. The top surface includes a notch etched therein. The substrate also includes a dielectric contacting the notch and at least part of the first and second metal layers and the via. The package includes a mold compound covering the semiconductor die and the substrate. The package includes a lateral surface approximately perpendicular to the first and second metal layers of the substrate. The mold compound, the dielectric, and the second metal layer are exposed to the lateral surface. A segment of the dielectric is positioned between the first metal layer and the lateral surface. The segment of the dielectric contacts the mold compound at the lateral surface.
In examples, a method of manufacturing a package comprises forming a package substrate. Forming the package substrate includes: plating first and second metal layers in a first metal stack and a third metal layer in a second metal stack, the second metal layer having a lateral end that is displaced from a saw street closest to the lateral end by a distance of at least 100 microns, at least one metal layer in the first metal stack partially overlapping in a vertical direction with the third metal layer; applying a dry film to at least one of the first, second, and third metal layers; patterning the dry film to form a dry film opening; etching at least one of the first, second, and third metal layers through the dry film opening to form a notch; removing the dry film; plating the notch; and applying a dielectric layer to at least one of the first, second, and third metal layers. The method also includes: coupling a semiconductor die to the package substrate; covering the die and the substrate with a mold compound; and sawing along the saw street so as to saw through the mold compound and the dielectric layer, but not through the second metal layer.
Many semiconductor packages include a semiconductor die and conductive terminals exposed to an exterior surface of the package. The semiconductor die exchanges electrical signals with the conductive terminals so the die can communicate with components outside of the package, such as other chips that may be co-mounted on a printed circuit board (PCB) with the package. To provide electrical pathways between the semiconductor die and the conductive terminals, various structures may be useful, such as bond wires, redistribution layers, etc.
Some packages contain a substrate that has multiple metal layers (also known as a metal stack) to provide the aforementioned electrical pathway between the semiconductor die and the conductive terminals. In such packages, electrical currents may flow from the conductive terminal, through the metal stack in the substrate, and to the semiconductor die, or from the semiconductor die, through the metal stack in the substrate, and to the conductive terminal. Such substrates may contain a network of metal layers that are covered by an insulative film, such as AJINOMOTO® build-up film (ABF). These substrates are manufactured by forming a first metal layer, covering the first metal layer with ABF, then forming a second metal layer and covering the second metal layer with ABF, and so on, until a fully customized substrate is formed. Such substrates provide significant design flexibility.
Generally, during manufacture, the substrates are formed in sets or arrays, and then sets or arrays of semiconductor dies are coupled to the sets or arrays of substrates, with one semiconductor die coupled to each substrate. A mold compound is applied to cover the semiconductor dies and the substrates, thus forming a mold compound bar that contains within it the array of semiconductor dies and substrates. The mold compound bar has saw streets or other markings that indicate where singulation should occur to separate the substrates and dies from each other to form individual semiconductor packages.
In some cases, the metal layers in the substrates are formed in vertical alignment with the saw streets. Stated another way, when a sawing process is performed on the mold compound bar, the sawing tool (e.g., mechanical saw or laser) cuts through the metal layers of the substrate as the sawing tool cuts through the mold compound bar. This act of cutting through the metal layers, particularly when those metal layers are positioned in vertical proximity to the interface between the mold compound and the substrate film, imparts substantial stress to the mold compound bar. This stress is significant enough to cause irreparable damage to the mold compound bar, especially at the mold compound-substrate interface. For example, significant delamination may occur. These deleterious effects reduce yield and present a meaningful technical problem.
Furthermore, stresses experienced during sawing, during handling or use, and in various other conditions can introduce cracks into the package. For example, cracks may originate in a particular area of substrate dielectric material in the package, and then the cracks may extend themselves by propagating through the dielectric. Poor mechanical coupling between metal layers and dielectric material within the package can also encourage crack formation. Such cracks pose another meaningful technical problem. Together, delamination and cracking substantially reduce the robustness of semiconductor packages and represent significant technical challenges in the semiconductor industry.
This disclosure describes various examples of packages with notched, interdigitated, and retracted substrate metal layers. In examples, a package includes a semiconductor die having a device side including circuitry formed therein. The package includes a substrate facing and coupled to the device side. The substrate includes first and second metal layers, and the first metal layer is positioned closer to the device side than the second metal layer and is coupled to the second metal layer by way of a via. At least one of the first and second metal layers has a top surface facing the semiconductor die. The top surface includes a notch etched therein. The substrate also includes third and fourth metal layers. The third metal layer is positioned closer to the device side than the fourth metal layer, with the third and fourth metal layers spaced apart from the first and second metal layers. The first metal layer is at least partially overlapping the fourth metal layer in the vertical direction. The first and fourth metal layers are in different levels of the substrate. The substrate further includes a dielectric contacting at least part of the first and second metal layers and the via. The package includes a mold compound covering the semiconductor die and the substrate. The package includes a lateral surface approximately perpendicular to the first and second metal layers of the substrate. The mold compound, the dielectric, and the second metal layer are exposed to the lateral surface. A segment of the dielectric is positioned between the first metal layer and the lateral surface. The segment of the dielectric contacts the mold compound at the lateral surface. These and other examples are now described with reference to the drawings.
The semiconductor package 104 includes a substrate 205. The substrate 205 comprises dielectric material 206 and a network of metal layers designed to implement application-specific electrical pathways (e.g., electrical pathways between solder bumps 204, 220, 234, 240 and metal layers exposed to a surface of the semiconductor package 104 to facilitate communications with devices outside of the semiconductor package 104). The dielectric material 206 may comprise, for example, AJINOMOTO® build-up film (ABF), although other films and materials with similar properties are contemplated. The network of metal layers includes internal metal stacks 236 and 242, which are positioned away from lateral surfaces of the semiconductor package 104. The network of metal layers also includes external metal stacks 237 and 241, which are positioned adjacent to the lateral surfaces of the semiconductor package 104. The metal layers in the metal stacks 236, 237, 241, and 242 may comprise any suitable metal, such as the plateable metals aluminum and copper.
The substrate 205 differs from a PCB because the substrate 205 is within the semiconductor package 104, whereas the PCB (e.g., PCB 102) is outside the semiconductor package 104. The substrate 205 includes multiple metal layers that are covered by a solid, tangible dielectric material 206, whereas the PCB may contain multiple layers of printed circuit board that may not be separated by a dielectric material other than air.
The metal stack 237 includes metal layers 208, 210, 212, 214, and 216. Some of the metal layers 208, 210, 212, 214, and 216 may comprise metal traces and others of these metal layers may comprise metal vias, but this distinction between metal traces and vias is minimally relevant in this disclosure, and they are collectively referred to herein as “metal layers.” The metal stack 241 includes metal layers 222, 224, 226, 228, and 230. Some of the metal layers 222, 224, 226, 228, and 230 may comprise metal traces and others of these metal layers may comprise metal vias, but this distinction between metal traces and vias is minimally relevant in this disclosure, and they are collectively referred to herein as “metal layers.” Solder bumps 204 and 220 couple to metal layers 208 and 222, respectively. Solder bumps 234 and 240 couple to the top metal layers in metal stacks 236 and 242, respectively. The semiconductor package 104 may be coupled to a PCB, such as PCB 102 (
As
Similar to the retraction of the metal layers 222, 224 and 226, the retraction of the metal layers 208, 210, and 212 from a closest lateral surface (such as lateral surface 248) is beneficial for similar reasons, and the retraction of the metal layer 210 from the closest lateral surface (e.g., lateral surface 248) is at least 100 microns (at least 125 microns in the case of metal layers 208, 212) to achieve the benefits described herein, with the area between these metal layers and the lateral surface 248 being filled with dielectric material. In examples, the various metal layers lie in horizontal planes that are perpendicular to the lateral surfaces 246 and 248. In examples, the mold compound 244 contacts the dielectric material 206 at the lateral surfaces 246, 248.
Multiple metal layers in the metal stacks 237, 242, 236, and 241 may be interdigitated. The term “interdigitated” means that two metal layers in different metal stacks partially overlap with each other in the vertical direction. Stated another way, a vertical line extends through both such interdigitated metal layers. In the example shown in
When any two metal layers are interdigitated with each other, the interdigitation blocks the propagation of cracks that may form in the dielectric material 206. For example, if a crack were to form in the dielectric material 206 at the top of the substrate 205 between solder bumps 220 and 234, a lack of interdigitation between the metal stacks 236, 241 leaves a pathway for the crack to propagate downward toward the bottom of the substrate 205, between the metal stacks 236, 241. However, because the metal layers 294, 224 are interdigitated with each other, any such formed crack will be blocked from propagating between the metal stacks 236, 241, because when the propagating crack encounters either of the interdigitated metal layers 294, 224, the metal layer(s) will arrest the crack propagation. In this way, interdigitation preserves the mechanical and functional integrity of the semiconductor package 104. Any suitable number of metal layers may be interdigitated in this manner. Interdigitated metal layers may be in the same metal stack or in different metal stacks. However, they cannot be co-located at the same vertical level, meaning that interdigitated metal layers must be vertically offset from each other such that they can vertically overlap with each other as described above without coming into contact with each other (thus avoiding short circuits).
One or more of the metal layers in the substrate 205 may include notches. A notch is a cavity in a top surface of a metal layer in the substrate 205 and/or in a combination of top and lateral surfaces of a metal layer in the substrate 205 (i.e., on a metal layer edge at which the top and lateral surfaces of a metal layer meet). In
The method 300 includes plating second and third metal layers in the first metal stack and plating fourth and fifth metal layers in a second metal stack that is separate from the first metal stack (306). A lateral end of the third metal layer is displaced from a saw street closest to the lateral end by a distance of at least 100 microns (306).
The method 300 includes applying a first dry film to the third and fifth metal layers (308).
The method 300 includes applying a second dielectric layer to the second, third, fourth, and fifth metal layers (318).
The method 300 includes plating sixth and seventh metal layers in the first metal stack and plating eighth and ninth metal layers in the second metal stack (320). The sixth and seventh metal layers have lateral ends that are displaced from the saw street by at least 100 microns (320). The sixth metal layer partially overlaps with the fourth metal layer in the vertical direction (320).
The method 300 includes applying a second dry film to the seventh and ninth metal layers (322) and patterning the second dry film to form a second dry film opening (324).
The method 300 includes performing an etching process through the second dry film opening to form a second notch in at least one of the sixth, seventh, eighth, and ninth metal layers (326), followed by removing the second dry film (328) and plating the second notch (330).
The method 300 includes applying a third dielectric layer to the sixth, seventh, eighth, and ninth metal layers (332).
The method 300 includes coupling a semiconductor die to the package substrate (334), covering the die and the substrate with a mold compound (336), and sawing along the saw street so as to saw through the mold compound, the second and third dielectric layers, and the first and second metal layers, but not through the third, sixth, and seventh metal layers (338).
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.
