Patent Application
20110244398
1. Field of Invention
The present invention relates to a semiconductor process, and more particularly to a patterning method.
2. Description of Related Art
As the level of integration of a semiconductor device is getting higher, the critical dimension of the same is getting smaller. Minimizing the critical dimension and increasing the level of integration have become the mainstream in the industry, and the key technology is in photolithography and etching.
In a photolithography process, it is known that raising a line or space resolution beyond 40 nm in the current state of semiconductor technology is rather difficult, unless a light source having a shorter wavelength and a corresponding photoresist are used. However, it is very costly to replace existing equipment entirely with new machines for this purpose. Therefore, how to use an etching process to meet the purpose of minimizing the critical dimension has been one of the main topics in the industry.
In the process of forming a gate, one known method includes sequentially forming a polysilicon layer, a SiN mask layer and a patterned photoresist layer on a substrate. Thereafter, the SiN mask layer is etched by using the patterned photoresist layer as a mask, so as to form a patterned SiN mask layer. Afterwards, a trimming process is performed to the patterned SiN mask layer. Further, the polysilicon layer is etched by using the trimmed patterned SiN mask layer, so as to form the gate.
In one case, a thinner SiN mask layer is used, and the purpose of trimming the line width of the patterned SiN mask layer is easily met. However, during the step of forming the patterned SiN mask layer, the patterned photoresist layer is subjected to the lateral etching more than the thickness reduction thereof, so that a high aspect ratio of the patterned photoresist layer is caused and photoresist collapse occurs.
In another case, a thicker SiN mask layer is used. During the step of forming the patterned SiN mask layer, the patterned photoresist layer is subjected to the thickness reduction more than the lateral etching thereof, so that photoresist collapse is not observed. However, the purpose of trimming the line width of the patterned SiN mask layer is difficultly met due to the larger thickness of the SiN mask layer.
The process window of the above-mentioned patterning method is narrow. Even though the critical dimension is reduced to below 40 nm by the above-mentioned patterning method, the formed patterns are distorted, as referred to scanning electron microscope (SEM) pictures of testing patterns A-F in
Accordingly, the present invention provides a patterning method, in which photoresist collapse does not occur to form distorted patterns during the etching process, the critical dimension can be reduced easily and the process window is wide enough.
The present invention provides a patterning method. First, a first mask layer, a second mask layer and a patterned photoresist layer are sequentially formed on a target layer. Thereafter, the second mask layer is etched by using the patterned photoresist layer as a mask, so as to form a patterned second mask layer. Afterwards, a trimming process is performed to the patterned second mask layer. Further, the first mask layer is etched by using the trimmed patterned second mask layer as a mask, so as to form a patterned first mask layer. The patterned photoresist layer is then removed. Next, the target layer is etched by using the patterned first mask layer as a mask.
According to an embodiment of the present invention, the target layer includes polysilicon, for example.
According to an embodiment of the present invention, the first mask layer and the second mask layer include different materials.
According to an embodiment of the present invention, the first mask layer includes silicon nitride, and the second mask layer includes silicon oxide, for example.
According to an embodiment of the present invention, the first mask layer includes silicon oxide, and the second mask layer includes silicon nitride, for example.
According to an embodiment of the present invention, the patterned photoresist layer has multiple layers. For example, the patterned photoresist layer includes, from bottom to top, a 365 nm photoresist layer, a Si-containing hard-mask bottom anti-reflection coating (SHB) layer and a 193 nm photoresist layer.
According to an embodiment of the present invention, the step of forming the patterned first mask layer and the step of forming the patterned second mask layer each include performing a dry etching process, in which the reaction gases include CF4, HBr, CHF3, He or a combination thereof.
According to an embodiment of the present invention, the step of forming the patterned second mask layer includes using HBr gas, so as to prevent the patterned photoresist layer from collapsing.
According to an embodiment of the present invention, the flow rate of HBr gas is about 100-150 sccm, for example.
According to an embodiment of the present invention, the time of the trimming process is about 40-60 seconds, for example.
The present invention further provides a patterning method. First, a first mask layer, a second mask layer and a patterned photoresist layer are sequentially formed on a target layer. Thereafter, the second mask layer and the first mask layer are sequentially etched by using the patterned photoresist layer as a mask, so as to form a patterned second mask layer and a patterned first mask layer. Afterwards, a trimming process is performed to the patterned second mask layer and the patterned first mask layer. The patterned photoresist layer is then removed. Next, the target layer is etched by using the trimmed patterned first mask layer as a mask.
According to an embodiment of the present invention, the target layer includes polysilicon, for example.
According to an embodiment of the present invention, the first mask layer and the second mask layer include different materials.
According to an embodiment of the present invention, the first mask layer includes silicon nitride, and the second mask layer includes silicon oxide, for example.
According to an embodiment of the present invention, the first mask layer includes silicon oxide, and the second mask layer includes silicon nitride, for example.
According to an embodiment of the present invention, the patterned photoresist layer has multiple layers. For example, the patterned photoresist layer includes, from bottom to top, a 365 nm photoresist layer, a SHB layer and a 193 nm photoresist layer.
According to an embodiment of the present invention, the step of forming the patterned second mask layer and the patterned first mask layer does not include using HBr gas.
According to an embodiment of the present invention, the time of trimming process is about 50-70 seconds, for example.
In view of above, the patterning method of the present invention can reduce the critical dimension with the existing equipment by using a trimming process and a stacked structure including dual mask layers. Further, the patterning method of the present invention is very competitive due to the simple process and wide process window thereof.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Referring to
The patterned photoresist layer 108 includes, from bottom to top, a 365 nm photoresist layer 109 (reactive to 365 nm wavelength light) of 1500 Å, a Si-containing hard-mask bottom anti-reflection coating (SHB) layer 110 of 300 Å and a 193 nm photoresist layer (reactive to 193 nm wavelength light) 111 of 800 Å. Further, the line width of the patterned photoresist layer is L1.
Referring to
Referring to
Referring to
Referring to
It is noted that a plurality of the stacked structures 120 is substantially arranged in strips, as shown in the top view of
Further, the trimmed patterned second mask layer 116a is removed, so that the patterned first mask layer 104a remaining on the patterned target layer 102a is beneficial for the following processes, such as a self-aligned suicide (salicide) process.
The above-mentioned embodiment in which the first mask layer is a SiN mask layer and the second mask layer is a SiO mask layer is provided for illustration purposes, and is not construed as limiting the present invention. It is appreciated by persons skilled in the art that the materials of the first and second mask layers can be determined by the material to be left on the patterned target layer. For example, if the following process requires to form a SiO mask layer on the patterned target layer, the SiO mask layer can be used as the first mask layer, and the SiN mask layer can be used as the second mask layer.
As described above, according to the patterning method of the present invention, a stacked structure including dual mask layers replaces the conventional single mask layer. A large amount of HBr gas is used during the step of patterning the second mask layer (i.e. upper mask layer), so that distorted patterns of the patterned second mask layer caused by photoresist collapse of the patterned photoresist layer do not occur, and thus, patterns of the patterned first mask layer and patterns of the patterned target layer which are sequentially formed are not distorted. Further, the trimming process is performed to the second mask layer with smaller thickness, so that the purpose of trimming the line width of the patterned second mask layer is easily met. In addition, the material of the first mask layer (i.e. lower mask layer) remaining on the patterned target layer can be chosen upon the process requirement, so as to benefit the following processes such as a salicide process.
Several examples are numerated to prove the performance of the patterning method according to the first embodiment of the present invention.
First, a polysilicon layer of 600 Å, a SiN mask layer of 450 Å, a SiO mask layer of 200 Å and a patterned photoresist layer are sequentially formed on a substrate. The patterned photoresist layer includes, from bottom to top, a 365 nm photoresist layer of 1500 Å, a SHB layer of 300 Å and a 193 nm photoresist layer of 800 Å. Thereafter, the SiO mask layer is etched by using the patterned photoresist layer as a mask, so as to form a patterned SiO mask layer. Thereafter, a trimming process is performed to the patterned SiO mask layer. Further, the SiN mask layer is etched by using the trimmed patterned SiO mask layer as a mask, so as to form a patterned SiN mask layer. The patterned photoresist layer is then removed. Next, the polysilicon layer is etched by using the patterned SiN mask layer as a mask.
Table 1 shows pressure, transfer coupling plasma (TCP) power, bias power (BP), gas species and flow rates thereof and time for each etching step.
The materials and thicknesses of the layers and the etching methods are the same in Examples 2 and 1, except that additional 30 sccm of HBr gas is used during the step of etching the SiO mask layer. Table 2 only lists the step of etching the SiO mask layer, and other same steps are not iterated herein.
The materials and thicknesses of the layers and the etching methods are the same in Examples 3 and 1, except that additional 100 sccm of HBr gas is used during the step of etching the SiO mask layer. Table 3 only lists the step of etching the SiO mask layer, and other same steps are not iterated herein.
Referring to
Referring to
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Referring to
In addition, another patterning process can be performed to the strip-shaped stacked structures 121, so as to form block-shaped stacked structures, as referred to
As described above, according to the patterning method of the present invention, a stacked structure including dual mask layers replaces the conventional single mask layer. No HBr gas is used during the step of patterning the second mask layer and the first mask layer, so that the patterned photoresist layer is much thinned out, and thus, distorted patterns caused by photoresist collapse do not occur. Accordingly, patterns of the patterned target layer which is sequentially formed are not distorted. Further, during the step of trimming the patterned second mask layer and the patterned first mask layer, the patterned second mask layer and the patterned first mask layer include different materials, so that polymer accumulated on the sidewall thereof is less than that accumulated on the sidewall of the single SiN mask layer of the same thickness, and thus, the purpose of trimming the line width of the patterned second mask layer and the patterned first mask layer can be easily met. In addition, the material of the first mask layer (i.e. lower mask layer) remaining on the patterned target layer can be chosen upon the process requirement, so as to benefit the following processes such as a salicide process.
Several examples are numerated to prove the performance of the patterning method according to the second embodiment of the present invention.
First, a polysilicon layer of 600 Å, a SiN mask layer of 450 Å, a SiO mask layer of 200 Å and a patterned photoresist layer are sequentially formed on a substrate. The patterned photoresist layer includes, from bottom to top, a 365 nm photoresist layer of 1500 Å, a SHB layer of 300 Å and a 193 nm photoresist layer of 800 Å. Thereafter, the SiO mask layer and the SiN mask layer are sequentially etched by using the patterned photoresist layer as a mask, so as to form a patterned SiO mask layer and a patterned SiN mask layer. Thereafter, a trimming process is performed to the patterned SiO mask layer and the patterned SiN mask layer. The patterned photoresist layer is then removed. Next, the polysilicon layer is etched by using the trimmed patterned SiN mask layer as a mask.
Table 4 shows pressure, transfer coupling plasma (TCP) power, bias power (BP), gas species and flow rates thereof and time for each etching step.
The materials and thicknesses of the layers and the etching methods are the same in Examples 5 and 4, except that the trimming process is omitted.
The materials and thicknesses of the layers and the etching methods are the same in Examples 6 and 4, except that no HBr gas is used during the step of etching the SiO mask layer and the SiN mask layer. Table 5 only lists the step of etching the SiO mask layer and the SiN mask layer, and other same steps are not iterated herein.
The materials and thicknesses of the layers and the etching methods are the same in Examples 7 and 4, except that no HBr gas is used during the step of etching the SiO mask layer and the SiN mask layer and the time of the trimming process is 60 seconds instead of 50 seconds in Example 4. Table 6 only lists the step of etching the SiO mask layer and the SiN mask layer and the step of the trimming process, and other same steps are not iterated herein.
In summary, the patterning method of the present invention uses a trimming process and a stacked structure including dual mask layers, so that photoresist collapse does not occur to form distorted patterns during the etching process, and the critical dimension can be reduced easily. Further, the patterning method in accordance with the present invention can be done in a single etching chamber. The process is simple and the process window thereof is wide enough. In addition, the patterning method of the present invention can effectively reduce the critical dimension without replacing any existing manufacturing equipment in the fabrication. Thus, the process cost is greatly saved, and the competitive advantage is achieved.
This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.
